1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
34 The Linux client driver is based on the 3c589_cs.c client driver by
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
44 Special thanks for testing and help in debugging this driver goes
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
63 4. There is a bad slow-down problem in this driver.
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
68 -------------------------------------------------------------------------------
70 -------------------------------------------------------------------------------
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
87 * Revision 0.13 1995/05/18 05:56:34 rpao
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
106 Bug fix: Make all non-exported functions private by using
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
112 ---------------------------------------------------------------------------- */
114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
116 #define DRV_NAME "nmclan_cs"
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
127 /* ----------------------------------------------------------------------------
129 ---------------------------------------------------------------------------- */
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/ptrace.h>
134 #include <linux/slab.h>
135 #include <linux/string.h>
136 #include <linux/timer.h>
137 #include <linux/interrupt.h>
138 #include <linux/in.h>
139 #include <linux/delay.h>
140 #include <linux/ethtool.h>
141 #include <linux/netdevice.h>
142 #include <linux/etherdevice.h>
143 #include <linux/skbuff.h>
144 #include <linux/if_arp.h>
145 #include <linux/ioport.h>
146 #include <linux/bitops.h>
148 #include <pcmcia/cisreg.h>
149 #include <pcmcia/cistpl.h>
150 #include <pcmcia/ds.h>
152 #include <linux/uaccess.h>
155 /* ----------------------------------------------------------------------------
157 ---------------------------------------------------------------------------- */
159 #define MACE_LADRF_LEN 8
160 /* 8 bytes in Logical Address Filter */
162 /* Loop Control Defines */
163 #define MACE_MAX_IR_ITERATIONS 10
164 #define MACE_MAX_RX_ITERATIONS 12
166 TBD: Dean brought this up, and I assumed the hardware would
169 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
170 non-zero when the isr exits. We may not get another interrupt
171 to process the remaining packets for some time.
175 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
176 which manages the interface between the MACE and the PCMCIA bus. It
177 also includes buffer management for the 32K x 8 SRAM to control up to
178 four transmit and 12 receive frames at a time.
180 #define AM2150_MAX_TX_FRAMES 4
181 #define AM2150_MAX_RX_FRAMES 12
183 /* Am2150 Ethernet Card I/O Mapping */
184 #define AM2150_RCV 0x00
185 #define AM2150_XMT 0x04
186 #define AM2150_XMT_SKIP 0x09
187 #define AM2150_RCV_NEXT 0x0A
188 #define AM2150_RCV_FRAME_COUNT 0x0B
189 #define AM2150_MACE_BANK 0x0C
190 #define AM2150_MACE_BASE 0x10
193 #define MACE_RCVFIFO 0
194 #define MACE_XMTFIFO 1
200 #define MACE_FIFOFC 7
204 #define MACE_BIUCC 11
205 #define MACE_FIFOCC 12
206 #define MACE_MACCC 13
207 #define MACE_PLSCC 14
208 #define MACE_PHYCC 15
209 #define MACE_CHIPIDL 16
210 #define MACE_CHIPIDH 17
213 #define MACE_LADRF 20
219 #define MACE_RNTPC 26
220 #define MACE_RCVCC 27
227 #define MACE_XMTRC_EXDEF 0x80
228 #define MACE_XMTRC_XMTRC 0x0F
230 #define MACE_XMTFS_XMTSV 0x80
231 #define MACE_XMTFS_UFLO 0x40
232 #define MACE_XMTFS_LCOL 0x20
233 #define MACE_XMTFS_MORE 0x10
234 #define MACE_XMTFS_ONE 0x08
235 #define MACE_XMTFS_DEFER 0x04
236 #define MACE_XMTFS_LCAR 0x02
237 #define MACE_XMTFS_RTRY 0x01
239 #define MACE_RCVFS_RCVSTS 0xF000
240 #define MACE_RCVFS_OFLO 0x8000
241 #define MACE_RCVFS_CLSN 0x4000
242 #define MACE_RCVFS_FRAM 0x2000
243 #define MACE_RCVFS_FCS 0x1000
245 #define MACE_FIFOFC_RCVFC 0xF0
246 #define MACE_FIFOFC_XMTFC 0x0F
248 #define MACE_IR_JAB 0x80
249 #define MACE_IR_BABL 0x40
250 #define MACE_IR_CERR 0x20
251 #define MACE_IR_RCVCCO 0x10
252 #define MACE_IR_RNTPCO 0x08
253 #define MACE_IR_MPCO 0x04
254 #define MACE_IR_RCVINT 0x02
255 #define MACE_IR_XMTINT 0x01
257 #define MACE_MACCC_PROM 0x80
258 #define MACE_MACCC_DXMT2PD 0x40
259 #define MACE_MACCC_EMBA 0x20
260 #define MACE_MACCC_RESERVED 0x10
261 #define MACE_MACCC_DRCVPA 0x08
262 #define MACE_MACCC_DRCVBC 0x04
263 #define MACE_MACCC_ENXMT 0x02
264 #define MACE_MACCC_ENRCV 0x01
266 #define MACE_PHYCC_LNKFL 0x80
267 #define MACE_PHYCC_DLNKTST 0x40
268 #define MACE_PHYCC_REVPOL 0x20
269 #define MACE_PHYCC_DAPC 0x10
270 #define MACE_PHYCC_LRT 0x08
271 #define MACE_PHYCC_ASEL 0x04
272 #define MACE_PHYCC_RWAKE 0x02
273 #define MACE_PHYCC_AWAKE 0x01
275 #define MACE_IAC_ADDRCHG 0x80
276 #define MACE_IAC_PHYADDR 0x04
277 #define MACE_IAC_LOGADDR 0x02
279 #define MACE_UTR_RTRE 0x80
280 #define MACE_UTR_RTRD 0x40
281 #define MACE_UTR_RPA 0x20
282 #define MACE_UTR_FCOLL 0x10
283 #define MACE_UTR_RCVFCSE 0x08
284 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
285 #define MACE_UTR_LOOP_NO_MENDEC 0x04
286 #define MACE_UTR_LOOP_EXTERNAL 0x02
287 #define MACE_UTR_LOOP_NONE 0x00
288 #define MACE_UTR_RESERVED 0x01
290 /* Switch MACE register bank (only 0 and 1 are valid) */
291 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
293 #define MACE_IMR_DEFAULT \
304 #undef MACE_IMR_DEFAULT
305 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
307 #define TX_TIMEOUT ((400*HZ)/1000)
309 /* ----------------------------------------------------------------------------
311 ---------------------------------------------------------------------------- */
313 typedef struct _mace_statistics {
328 /* RFS1--Receive Status (RCVSTS) */
334 /* RFS2--Runt Packet Count (RNTPC) */
337 /* RFS3--Receive Collision Count (RCVCC) */
358 typedef struct _mace_private {
359 struct pcmcia_device *p_dev;
360 mace_statistics mace_stats; /* MACE chip statistics counters */
362 /* restore_multicast_list() state variables */
363 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
364 int multicast_num_addrs;
366 char tx_free_frames; /* Number of free transmit frame buffers */
367 char tx_irq_disabled; /* MACE TX interrupt disabled */
369 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
372 /* ----------------------------------------------------------------------------
373 Private Global Variables
374 ---------------------------------------------------------------------------- */
376 static const char *if_names[]={
377 "Auto", "10baseT", "BNC",
380 /* ----------------------------------------------------------------------------
382 These are the parameters that can be set during loading with
384 ---------------------------------------------------------------------------- */
386 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
387 MODULE_LICENSE("GPL");
389 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
391 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
392 INT_MODULE_PARM(if_port, 0);
395 /* ----------------------------------------------------------------------------
397 ---------------------------------------------------------------------------- */
399 static int nmclan_config(struct pcmcia_device *link);
400 static void nmclan_release(struct pcmcia_device *link);
402 static void nmclan_reset(struct net_device *dev);
403 static int mace_config(struct net_device *dev, struct ifmap *map);
404 static int mace_open(struct net_device *dev);
405 static int mace_close(struct net_device *dev);
406 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
407 struct net_device *dev);
408 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue);
409 static irqreturn_t mace_interrupt(int irq, void *dev_id);
410 static struct net_device_stats *mace_get_stats(struct net_device *dev);
411 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
412 static void restore_multicast_list(struct net_device *dev);
413 static void set_multicast_list(struct net_device *dev);
414 static const struct ethtool_ops netdev_ethtool_ops;
417 static void nmclan_detach(struct pcmcia_device *p_dev);
419 static const struct net_device_ops mace_netdev_ops = {
420 .ndo_open = mace_open,
421 .ndo_stop = mace_close,
422 .ndo_start_xmit = mace_start_xmit,
423 .ndo_tx_timeout = mace_tx_timeout,
424 .ndo_set_config = mace_config,
425 .ndo_get_stats = mace_get_stats,
426 .ndo_set_rx_mode = set_multicast_list,
427 .ndo_set_mac_address = eth_mac_addr,
428 .ndo_validate_addr = eth_validate_addr,
431 static int nmclan_probe(struct pcmcia_device *link)
434 struct net_device *dev;
436 dev_dbg(&link->dev, "nmclan_attach()\n");
438 /* Create new ethernet device */
439 dev = alloc_etherdev(sizeof(mace_private));
442 lp = netdev_priv(dev);
446 spin_lock_init(&lp->bank_lock);
447 link->resource[0]->end = 32;
448 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
449 link->config_flags |= CONF_ENABLE_IRQ;
450 link->config_index = 1;
451 link->config_regs = PRESENT_OPTION;
453 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
455 dev->netdev_ops = &mace_netdev_ops;
456 dev->ethtool_ops = &netdev_ethtool_ops;
457 dev->watchdog_timeo = TX_TIMEOUT;
459 return nmclan_config(link);
460 } /* nmclan_attach */
462 static void nmclan_detach(struct pcmcia_device *link)
464 struct net_device *dev = link->priv;
466 dev_dbg(&link->dev, "nmclan_detach\n");
468 unregister_netdev(dev);
470 nmclan_release(link);
473 } /* nmclan_detach */
475 /* ----------------------------------------------------------------------------
477 Reads a MACE register. This is bank independent; however, the
478 caller must ensure that this call is not interruptable. We are
479 assuming that during normal operation, the MACE is always in
481 ---------------------------------------------------------------------------- */
482 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
488 case 0: /* register 0-15 */
489 data = inb(ioaddr + AM2150_MACE_BASE + reg);
491 case 1: /* register 16-31 */
492 spin_lock_irqsave(&lp->bank_lock, flags);
494 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
496 spin_unlock_irqrestore(&lp->bank_lock, flags);
502 /* ----------------------------------------------------------------------------
504 Writes to a MACE register. This is bank independent; however,
505 the caller must ensure that this call is not interruptable. We
506 are assuming that during normal operation, the MACE is always in
508 ---------------------------------------------------------------------------- */
509 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
515 case 0: /* register 0-15 */
516 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
518 case 1: /* register 16-31 */
519 spin_lock_irqsave(&lp->bank_lock, flags);
521 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
523 spin_unlock_irqrestore(&lp->bank_lock, flags);
528 /* ----------------------------------------------------------------------------
530 Resets the MACE chip.
531 ---------------------------------------------------------------------------- */
532 static int mace_init(mace_private *lp, unsigned int ioaddr,
533 const char *enet_addr)
538 /* MACE Software reset */
539 mace_write(lp, ioaddr, MACE_BIUCC, 1);
540 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
541 /* Wait for reset bit to be cleared automatically after <= 200ns */;
544 pr_err("reset failed, card removed?\n");
549 mace_write(lp, ioaddr, MACE_BIUCC, 0);
551 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
552 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
554 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
555 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
558 * Bit 2-1 PORTSEL[1-0] Port Select.
561 * 10 DAI Port (reserved in Am2150)
563 * For this card, only the first two are valid.
564 * So, PLSCC should be set to
567 * Or just set ASEL in PHYCC below!
571 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
574 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
577 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
578 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
579 and the MACE device will automatically select the operating media
584 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
585 /* Poll ADDRCHG bit */
587 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
591 pr_err("ADDRCHG timeout, card removed?\n");
595 /* Set PADR register */
596 for (i = 0; i < ETH_ALEN; i++)
597 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
599 /* MAC Configuration Control Register should be written last */
600 /* Let set_multicast_list set this. */
601 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
602 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
606 static int nmclan_config(struct pcmcia_device *link)
608 struct net_device *dev = link->priv;
609 mace_private *lp = netdev_priv(dev);
615 dev_dbg(&link->dev, "nmclan_config\n");
618 ret = pcmcia_request_io(link);
621 ret = pcmcia_request_irq(link, mace_interrupt);
624 ret = pcmcia_enable_device(link);
628 dev->irq = link->irq;
629 dev->base_addr = link->resource[0]->start;
631 ioaddr = dev->base_addr;
633 /* Read the ethernet address from the CIS. */
634 len = pcmcia_get_tuple(link, 0x80, &buf);
635 if (!buf || len < ETH_ALEN) {
639 eth_hw_addr_set(dev, buf);
642 /* Verify configuration by reading the MACE ID. */
646 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
647 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
648 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
649 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
652 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
658 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
661 /* The if_port symbol can be set when the module is loaded */
663 dev->if_port = if_port;
665 pr_notice("invalid if_port requested\n");
667 SET_NETDEV_DEV(dev, &link->dev);
669 i = register_netdev(dev);
671 pr_notice("register_netdev() failed\n");
675 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
676 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
680 nmclan_release(link);
682 } /* nmclan_config */
684 static void nmclan_release(struct pcmcia_device *link)
686 dev_dbg(&link->dev, "nmclan_release\n");
687 pcmcia_disable_device(link);
690 static int nmclan_suspend(struct pcmcia_device *link)
692 struct net_device *dev = link->priv;
695 netif_device_detach(dev);
700 static int nmclan_resume(struct pcmcia_device *link)
702 struct net_device *dev = link->priv;
706 netif_device_attach(dev);
713 /* ----------------------------------------------------------------------------
715 Reset and restore all of the Xilinx and MACE registers.
716 ---------------------------------------------------------------------------- */
717 static void nmclan_reset(struct net_device *dev)
719 mace_private *lp = netdev_priv(dev);
722 struct pcmcia_device *link = &lp->link;
725 /* Save original COR value */
726 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
729 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
731 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
732 /* Need to wait for 20 ms for PCMCIA to finish reset. */
734 /* Restore original COR configuration index */
735 pcmcia_write_config_byte(link, CISREG_COR,
736 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
737 /* Xilinx is now completely reset along with the MACE chip. */
738 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
740 #endif /* #if RESET_XILINX */
742 /* Xilinx is now completely reset along with the MACE chip. */
743 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
745 /* Reinitialize the MACE chip for operation. */
746 mace_init(lp, dev->base_addr, dev->dev_addr);
747 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
749 /* Restore the multicast list and enable TX and RX. */
750 restore_multicast_list(dev);
753 /* ----------------------------------------------------------------------------
755 [Someone tell me what this is supposed to do? Is if_port a defined
756 standard? If so, there should be defines to indicate 1=10Base-T,
757 2=10Base-2, etc. including limited automatic detection.]
758 ---------------------------------------------------------------------------- */
759 static int mace_config(struct net_device *dev, struct ifmap *map)
761 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
762 if (map->port <= 2) {
763 dev->if_port = map->port;
764 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
771 /* ----------------------------------------------------------------------------
774 ---------------------------------------------------------------------------- */
775 static int mace_open(struct net_device *dev)
777 unsigned int ioaddr = dev->base_addr;
778 mace_private *lp = netdev_priv(dev);
779 struct pcmcia_device *link = lp->p_dev;
781 if (!pcmcia_dev_present(link))
788 netif_start_queue(dev);
791 return 0; /* Always succeed */
794 /* ----------------------------------------------------------------------------
796 Closes device driver.
797 ---------------------------------------------------------------------------- */
798 static int mace_close(struct net_device *dev)
800 unsigned int ioaddr = dev->base_addr;
801 mace_private *lp = netdev_priv(dev);
802 struct pcmcia_device *link = lp->p_dev;
804 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
806 /* Mask off all interrupts from the MACE chip. */
807 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
810 netif_stop_queue(dev);
815 static void netdev_get_drvinfo(struct net_device *dev,
816 struct ethtool_drvinfo *info)
818 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
819 snprintf(info->bus_info, sizeof(info->bus_info),
820 "PCMCIA 0x%lx", dev->base_addr);
823 static const struct ethtool_ops netdev_ethtool_ops = {
824 .get_drvinfo = netdev_get_drvinfo,
827 /* ----------------------------------------------------------------------------
829 This routine begins the packet transmit function. When completed,
830 it will generate a transmit interrupt.
832 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
833 returns 0, the "packet is now solely the responsibility of the
834 driver." If _start_xmit returns non-zero, the "transmission
835 failed, put skb back into a list."
836 ---------------------------------------------------------------------------- */
838 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue)
840 mace_private *lp = netdev_priv(dev);
841 struct pcmcia_device *link = lp->p_dev;
843 netdev_notice(dev, "transmit timed out -- ");
845 pr_cont("resetting card\n");
846 pcmcia_reset_card(link->socket);
847 #else /* #if RESET_ON_TIMEOUT */
848 pr_cont("NOT resetting card\n");
849 #endif /* #if RESET_ON_TIMEOUT */
850 netif_trans_update(dev); /* prevent tx timeout */
851 netif_wake_queue(dev);
854 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
855 struct net_device *dev)
857 mace_private *lp = netdev_priv(dev);
858 unsigned int ioaddr = dev->base_addr;
860 netif_stop_queue(dev);
862 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
863 dev->name, (long)skb->len);
865 #if (!TX_INTERRUPTABLE)
866 /* Disable MACE TX interrupts. */
867 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
868 ioaddr + AM2150_MACE_BASE + MACE_IMR);
869 lp->tx_irq_disabled=1;
870 #endif /* #if (!TX_INTERRUPTABLE) */
873 /* This block must not be interrupted by another transmit request!
874 mace_tx_timeout will take care of timer-based retransmissions from
875 the upper layers. The interrupt handler is guaranteed never to
876 service a transmit interrupt while we are in here.
879 dev->stats.tx_bytes += skb->len;
880 lp->tx_free_frames--;
882 /* WARNING: Write the _exact_ number of bytes written in the header! */
883 /* Put out the word header [must be an outw()] . . . */
884 outw(skb->len, ioaddr + AM2150_XMT);
885 /* . . . and the packet [may be any combination of outw() and outb()] */
886 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
888 /* Odd byte transfer */
889 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
893 if (lp->tx_free_frames > 0)
894 netif_start_queue(dev);
895 #endif /* #if MULTI_TX */
898 #if (!TX_INTERRUPTABLE)
899 /* Re-enable MACE TX interrupts. */
900 lp->tx_irq_disabled=0;
901 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
902 #endif /* #if (!TX_INTERRUPTABLE) */
907 } /* mace_start_xmit */
909 /* ----------------------------------------------------------------------------
911 The interrupt handler.
912 ---------------------------------------------------------------------------- */
913 static irqreturn_t mace_interrupt(int irq, void *dev_id)
915 struct net_device *dev = (struct net_device *) dev_id;
916 mace_private *lp = netdev_priv(dev);
919 int IntrCnt = MACE_MAX_IR_ITERATIONS;
922 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
927 ioaddr = dev->base_addr;
929 if (lp->tx_irq_disabled) {
931 if (lp->tx_irq_disabled)
932 msg = "Interrupt with tx_irq_disabled";
934 msg = "Re-entering the interrupt handler";
935 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
937 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
938 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
939 /* WARNING: MACE_IR has been read! */
943 if (!netif_device_present(dev)) {
944 netdev_dbg(dev, "interrupt from dead card\n");
949 /* WARNING: MACE_IR is a READ/CLEAR port! */
950 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
951 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
954 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
956 if (status & MACE_IR_RCVINT) {
957 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
960 if (status & MACE_IR_XMTINT) {
961 unsigned char fifofc;
965 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
966 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
967 dev->stats.tx_errors++;
968 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
971 /* Transmit Retry Count (XMTRC, reg 4) */
972 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
973 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
974 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
977 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
978 MACE_XMTFS_XMTSV /* Transmit Status Valid */
980 lp->mace_stats.xmtsv++;
982 if (xmtfs & ~MACE_XMTFS_XMTSV) {
983 if (xmtfs & MACE_XMTFS_UFLO) {
984 /* Underflow. Indicates that the Transmit FIFO emptied before
985 the end of frame was reached. */
986 lp->mace_stats.uflo++;
988 if (xmtfs & MACE_XMTFS_LCOL) {
990 lp->mace_stats.lcol++;
992 if (xmtfs & MACE_XMTFS_MORE) {
993 /* MORE than one retry was needed */
994 lp->mace_stats.more++;
996 if (xmtfs & MACE_XMTFS_ONE) {
997 /* Exactly ONE retry occurred */
998 lp->mace_stats.one++;
1000 if (xmtfs & MACE_XMTFS_DEFER) {
1001 /* Transmission was defered */
1002 lp->mace_stats.defer++;
1004 if (xmtfs & MACE_XMTFS_LCAR) {
1005 /* Loss of carrier */
1006 lp->mace_stats.lcar++;
1008 if (xmtfs & MACE_XMTFS_RTRY) {
1009 /* Retry error: transmit aborted after 16 attempts */
1010 lp->mace_stats.rtry++;
1012 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1014 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1016 dev->stats.tx_packets++;
1017 lp->tx_free_frames++;
1018 netif_wake_queue(dev);
1019 } /* if (status & MACE_IR_XMTINT) */
1021 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1022 if (status & MACE_IR_JAB) {
1023 /* Jabber Error. Excessive transmit duration (20-150ms). */
1024 lp->mace_stats.jab++;
1026 if (status & MACE_IR_BABL) {
1027 /* Babble Error. >1518 bytes transmitted. */
1028 lp->mace_stats.babl++;
1030 if (status & MACE_IR_CERR) {
1031 /* Collision Error. CERR indicates the absence of the
1032 Signal Quality Error Test message after a packet
1034 lp->mace_stats.cerr++;
1036 if (status & MACE_IR_RCVCCO) {
1037 /* Receive Collision Count Overflow; */
1038 lp->mace_stats.rcvcco++;
1040 if (status & MACE_IR_RNTPCO) {
1041 /* Runt Packet Count Overflow */
1042 lp->mace_stats.rntpco++;
1044 if (status & MACE_IR_MPCO) {
1045 /* Missed Packet Count Overflow */
1046 lp->mace_stats.mpco++;
1048 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1050 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1053 } /* mace_interrupt */
1055 /* ----------------------------------------------------------------------------
1058 ---------------------------------------------------------------------------- */
1059 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1061 mace_private *lp = netdev_priv(dev);
1062 unsigned int ioaddr = dev->base_addr;
1063 unsigned char rx_framecnt;
1064 unsigned short rx_status;
1067 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1068 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1071 rx_status = inw(ioaddr + AM2150_RCV);
1073 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1074 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1076 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1077 dev->stats.rx_errors++;
1078 if (rx_status & MACE_RCVFS_OFLO) {
1079 lp->mace_stats.oflo++;
1081 if (rx_status & MACE_RCVFS_CLSN) {
1082 lp->mace_stats.clsn++;
1084 if (rx_status & MACE_RCVFS_FRAM) {
1085 lp->mace_stats.fram++;
1087 if (rx_status & MACE_RCVFS_FCS) {
1088 lp->mace_stats.fcs++;
1091 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1092 /* Auto Strip is off, always subtract 4 */
1093 struct sk_buff *skb;
1095 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1096 /* runt packet count */
1097 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1098 /* rcv collision count */
1100 pr_debug(" receiving packet size 0x%X rx_status"
1101 " 0x%X.\n", pkt_len, rx_status);
1103 skb = netdev_alloc_skb(dev, pkt_len + 2);
1106 skb_reserve(skb, 2);
1107 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1109 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1110 skb->protocol = eth_type_trans(skb, dev);
1112 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1114 dev->stats.rx_packets++;
1115 dev->stats.rx_bytes += pkt_len;
1116 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1119 pr_debug("%s: couldn't allocate a sk_buff of size"
1120 " %d.\n", dev->name, pkt_len);
1121 dev->stats.rx_dropped++;
1124 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1130 /* ----------------------------------------------------------------------------
1132 ---------------------------------------------------------------------------- */
1133 static void pr_linux_stats(struct net_device_stats *pstats)
1135 pr_debug("pr_linux_stats\n");
1136 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1137 (long)pstats->rx_packets, (long)pstats->tx_packets);
1138 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1139 (long)pstats->rx_errors, (long)pstats->tx_errors);
1140 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1141 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1142 pr_debug(" multicast=%-7ld collisions=%ld\n",
1143 (long)pstats->multicast, (long)pstats->collisions);
1145 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1146 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1147 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1148 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1149 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1150 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1152 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1153 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1154 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1155 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1156 pr_debug(" tx_window_errors=%ld\n",
1157 (long)pstats->tx_window_errors);
1158 } /* pr_linux_stats */
1160 /* ----------------------------------------------------------------------------
1162 ---------------------------------------------------------------------------- */
1163 static void pr_mace_stats(mace_statistics *pstats)
1165 pr_debug("pr_mace_stats\n");
1167 pr_debug(" xmtsv=%-7d uflo=%d\n",
1168 pstats->xmtsv, pstats->uflo);
1169 pr_debug(" lcol=%-7d more=%d\n",
1170 pstats->lcol, pstats->more);
1171 pr_debug(" one=%-7d defer=%d\n",
1172 pstats->one, pstats->defer);
1173 pr_debug(" lcar=%-7d rtry=%d\n",
1174 pstats->lcar, pstats->rtry);
1177 pr_debug(" exdef=%-7d xmtrc=%d\n",
1178 pstats->exdef, pstats->xmtrc);
1180 /* RFS1--Receive Status (RCVSTS) */
1181 pr_debug(" oflo=%-7d clsn=%d\n",
1182 pstats->oflo, pstats->clsn);
1183 pr_debug(" fram=%-7d fcs=%d\n",
1184 pstats->fram, pstats->fcs);
1186 /* RFS2--Runt Packet Count (RNTPC) */
1187 /* RFS3--Receive Collision Count (RCVCC) */
1188 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1189 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1192 pr_debug(" jab=%-7d babl=%d\n",
1193 pstats->jab, pstats->babl);
1194 pr_debug(" cerr=%-7d rcvcco=%d\n",
1195 pstats->cerr, pstats->rcvcco);
1196 pr_debug(" rntpco=%-7d mpco=%d\n",
1197 pstats->rntpco, pstats->mpco);
1200 pr_debug(" mpc=%d\n", pstats->mpc);
1203 pr_debug(" rntpc=%d\n", pstats->rntpc);
1206 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1208 } /* pr_mace_stats */
1210 /* ----------------------------------------------------------------------------
1212 Update statistics. We change to register window 1, so this
1213 should be run single-threaded if the device is active. This is
1214 expected to be a rare operation, and it's simpler for the rest
1215 of the driver to assume that window 0 is always valid rather
1216 than use a special window-state variable.
1218 oflo & uflo should _never_ occur since it would mean the Xilinx
1219 was not able to transfer data between the MACE FIFO and the
1220 card's SRAM fast enough. If this happens, something is
1221 seriously wrong with the hardware.
1222 ---------------------------------------------------------------------------- */
1223 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1225 mace_private *lp = netdev_priv(dev);
1227 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1228 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1229 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1230 /* At this point, mace_stats is fully updated for this call.
1231 We may now update the netdev stats. */
1233 /* The MACE has no equivalent for netdev stats field which are commented
1236 /* dev->stats.multicast; */
1237 dev->stats.collisions =
1238 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1239 /* Collision: The MACE may retry sending a packet 15 times
1240 before giving up. The retry count is in XMTRC.
1241 Does each retry constitute a collision?
1242 If so, why doesn't the RCVCC record these collisions? */
1244 /* detailed rx_errors: */
1245 dev->stats.rx_length_errors =
1246 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1247 /* dev->stats.rx_over_errors */
1248 dev->stats.rx_crc_errors = lp->mace_stats.fcs;
1249 dev->stats.rx_frame_errors = lp->mace_stats.fram;
1250 dev->stats.rx_fifo_errors = lp->mace_stats.oflo;
1251 dev->stats.rx_missed_errors =
1252 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1254 /* detailed tx_errors */
1255 dev->stats.tx_aborted_errors = lp->mace_stats.rtry;
1256 dev->stats.tx_carrier_errors = lp->mace_stats.lcar;
1257 /* LCAR usually results from bad cabling. */
1258 dev->stats.tx_fifo_errors = lp->mace_stats.uflo;
1259 dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1260 /* dev->stats.tx_window_errors; */
1261 } /* update_stats */
1263 /* ----------------------------------------------------------------------------
1265 Gathers ethernet statistics from the MACE chip.
1266 ---------------------------------------------------------------------------- */
1267 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1269 mace_private *lp = netdev_priv(dev);
1271 update_stats(dev->base_addr, dev);
1273 pr_debug("%s: updating the statistics.\n", dev->name);
1274 pr_linux_stats(&dev->stats);
1275 pr_mace_stats(&lp->mace_stats);
1278 } /* net_device_stats */
1280 /* ----------------------------------------------------------------------------
1282 Modified from Am79C90 data sheet.
1283 ---------------------------------------------------------------------------- */
1285 #ifdef BROKEN_MULTICAST
1287 static void updateCRC(int *CRC, int bit)
1289 static const int poly[]={
1294 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1295 CRC generator polynomial. */
1299 /* shift CRC and control bit (CRC[32]) */
1300 for (j = 32; j > 0; j--)
1304 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1306 for (j = 0; j < 32; j++)
1310 /* ----------------------------------------------------------------------------
1312 Build logical address filter.
1313 Modified from Am79C90 data sheet.
1316 ladrf: logical address filter (contents initialized to 0)
1317 adr: ethernet address
1318 ---------------------------------------------------------------------------- */
1319 static void BuildLAF(int *ladrf, int *adr)
1321 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1323 int i, byte; /* temporary array indices */
1324 int hashcode; /* the output object */
1328 for (byte = 0; byte < 6; byte++)
1329 for (i = 0; i < 8; i++)
1330 updateCRC(CRC, (adr[byte] >> i) & 1);
1333 for (i = 0; i < 6; i++)
1334 hashcode = (hashcode << 1) + CRC[i];
1336 byte = hashcode >> 3;
1337 ladrf[byte] |= (1 << (hashcode & 7));
1341 printk(KERN_DEBUG " adr =%pM\n", adr);
1342 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1343 for (i = 0; i < 8; i++)
1344 pr_cont(" %02X", ladrf[i]);
1349 /* ----------------------------------------------------------------------------
1350 restore_multicast_list
1351 Restores the multicast filter for MACE chip to the last
1352 set_multicast_list() call.
1357 ---------------------------------------------------------------------------- */
1358 static void restore_multicast_list(struct net_device *dev)
1360 mace_private *lp = netdev_priv(dev);
1361 int num_addrs = lp->multicast_num_addrs;
1362 int *ladrf = lp->multicast_ladrf;
1363 unsigned int ioaddr = dev->base_addr;
1366 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1367 dev->name, num_addrs);
1369 if (num_addrs > 0) {
1371 pr_debug("Attempt to restore multicast list detected.\n");
1373 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1374 /* Poll ADDRCHG bit */
1375 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1377 /* Set LADRF register */
1378 for (i = 0; i < MACE_LADRF_LEN; i++)
1379 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1381 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1382 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1384 } else if (num_addrs < 0) {
1386 /* Promiscuous mode: receive all packets */
1387 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1388 mace_write(lp, ioaddr, MACE_MACCC,
1389 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1395 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1396 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1399 } /* restore_multicast_list */
1401 /* ----------------------------------------------------------------------------
1403 Set or clear the multicast filter for this adaptor.
1406 num_addrs == -1 Promiscuous mode, receive all packets
1407 num_addrs == 0 Normal mode, clear multicast list
1408 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1409 best-effort filtering.
1413 ---------------------------------------------------------------------------- */
1415 static void set_multicast_list(struct net_device *dev)
1417 mace_private *lp = netdev_priv(dev);
1418 int adr[ETH_ALEN] = {0}; /* Ethernet address */
1419 struct netdev_hw_addr *ha;
1424 if (netdev_mc_count(dev) != old) {
1425 old = netdev_mc_count(dev);
1426 pr_debug("%s: setting Rx mode to %d addresses.\n",
1432 /* Set multicast_num_addrs. */
1433 lp->multicast_num_addrs = netdev_mc_count(dev);
1435 /* Set multicast_ladrf. */
1436 if (num_addrs > 0) {
1437 /* Calculate multicast logical address filter */
1438 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1439 netdev_for_each_mc_addr(ha, dev) {
1440 memcpy(adr, ha->addr, ETH_ALEN);
1441 BuildLAF(lp->multicast_ladrf, adr);
1445 restore_multicast_list(dev);
1447 } /* set_multicast_list */
1449 #endif /* BROKEN_MULTICAST */
1451 static void restore_multicast_list(struct net_device *dev)
1453 unsigned int ioaddr = dev->base_addr;
1454 mace_private *lp = netdev_priv(dev);
1456 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1457 lp->multicast_num_addrs);
1459 if (dev->flags & IFF_PROMISC) {
1460 /* Promiscuous mode: receive all packets */
1461 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1462 mace_write(lp, ioaddr, MACE_MACCC,
1463 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1467 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1468 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1470 } /* restore_multicast_list */
1472 static void set_multicast_list(struct net_device *dev)
1474 mace_private *lp = netdev_priv(dev);
1479 if (netdev_mc_count(dev) != old) {
1480 old = netdev_mc_count(dev);
1481 pr_debug("%s: setting Rx mode to %d addresses.\n",
1487 lp->multicast_num_addrs = netdev_mc_count(dev);
1488 restore_multicast_list(dev);
1490 } /* set_multicast_list */
1492 static const struct pcmcia_device_id nmclan_ids[] = {
1493 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1494 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1497 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1499 static struct pcmcia_driver nmclan_cs_driver = {
1500 .owner = THIS_MODULE,
1501 .name = "nmclan_cs",
1502 .probe = nmclan_probe,
1503 .remove = nmclan_detach,
1504 .id_table = nmclan_ids,
1505 .suspend = nmclan_suspend,
1506 .resume = nmclan_resume,
1508 module_pcmcia_driver(nmclan_cs_driver);