2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/bitops.h>
37 #include <linux/etherdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/netdevice.h>
41 #include <linux/skbuff.h>
44 #include "ena_eth_com.h"
46 #define DRV_MODULE_VER_MAJOR 1
47 #define DRV_MODULE_VER_MINOR 5
48 #define DRV_MODULE_VER_SUBMINOR 0
50 #define DRV_MODULE_NAME "ena"
51 #ifndef DRV_MODULE_VERSION
52 #define DRV_MODULE_VERSION \
53 __stringify(DRV_MODULE_VER_MAJOR) "." \
54 __stringify(DRV_MODULE_VER_MINOR) "." \
55 __stringify(DRV_MODULE_VER_SUBMINOR) "K"
58 #define DEVICE_NAME "Elastic Network Adapter (ENA)"
60 /* 1 for AENQ + ADMIN */
61 #define ENA_ADMIN_MSIX_VEC 1
62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
64 #define ENA_MIN_MSIX_VEC 2
68 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
70 #define ENA_DEFAULT_RING_SIZE (1024)
72 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
73 #define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN)
75 /* limit the buffer size to 600 bytes to handle MTU changes from very
76 * small to very large, in which case the number of buffers per packet
77 * could exceed ENA_PKT_MAX_BUFS
79 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
81 #define ENA_MIN_MTU 128
83 #define ENA_NAME_MAX_LEN 20
84 #define ENA_IRQNAME_SIZE 40
86 #define ENA_PKT_MAX_BUFS 19
88 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
89 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
91 #define ENA_HASH_KEY_SIZE 40
93 /* The number of tx packet completions that will be handled each NAPI poll
94 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
96 #define ENA_TX_POLL_BUDGET_DIVIDER 4
98 /* Refill Rx queue when number of available descriptors is below
99 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
101 #define ENA_RX_REFILL_THRESH_DIVIDER 8
103 /* Number of queues to check for missing queues per timer service */
104 #define ENA_MONITORED_TX_QUEUES 4
105 /* Max timeout packets before device reset */
106 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128
108 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
110 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
111 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
112 (((idx) + (n)) & ((ring_size) - 1))
114 #define ENA_IO_TXQ_IDX(q) (2 * (q))
115 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
116 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
117 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
119 #define ENA_MGMNT_IRQ_IDX 0
120 #define ENA_IO_IRQ_FIRST_IDX 1
121 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
123 /* ENA device should send keep alive msg every 1 sec.
124 * We wait for 6 sec just to be on the safe side.
126 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ)
127 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
129 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
132 irq_handler_t handler;
136 cpumask_t affinity_hint_mask;
137 char name[ENA_IRQNAME_SIZE];
141 struct napi_struct napi ____cacheline_aligned;
142 struct ena_ring *tx_ring;
143 struct ena_ring *rx_ring;
147 struct ena_tx_buffer {
149 /* num of ena desc for this specific skb
150 * (includes data desc and metadata desc)
153 /* num of buffers used by this skb */
156 /* Used for detect missing tx packets to limit the number of prints */
158 /* Save the last jiffies to detect missing tx packets
160 * sets to non zero value on ena_start_xmit and set to zero on
161 * napi and timer_Service_routine.
163 * while this value is not protected by lock,
164 * a given packet is not expected to be handled by ena_start_xmit
165 * and by napi/timer_service at the same time.
167 unsigned long last_jiffies;
168 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
169 } ____cacheline_aligned;
171 struct ena_rx_buffer {
175 struct ena_com_buf ena_buf;
176 } ____cacheline_aligned;
178 struct ena_stats_tx {
186 u64 linearize_failed;
194 struct ena_stats_rx {
203 u64 rx_copybreak_pkt;
210 /* Holds the empty requests for TX/RX
211 * out of order completions
218 struct ena_tx_buffer *tx_buffer_info;
219 struct ena_rx_buffer *rx_buffer_info;
222 /* cache ptr to avoid using the adapter */
224 struct pci_dev *pdev;
225 struct napi_struct *napi;
226 struct net_device *netdev;
227 struct ena_com_dev *ena_dev;
228 struct ena_adapter *adapter;
229 struct ena_com_io_cq *ena_com_io_cq;
230 struct ena_com_io_sq *ena_com_io_sq;
239 /* The maximum header length the device can handle */
240 u8 tx_max_header_size;
242 bool first_interrupt;
243 u16 no_interrupt_event_cnt;
247 /* number of tx/rx_buffer_info's entries */
250 enum ena_admin_placement_policy_type tx_mem_queue_type;
252 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
253 u32 smoothed_interval;
254 u32 per_napi_packets;
256 enum ena_intr_moder_level moder_tbl_idx;
257 struct u64_stats_sync syncp;
259 struct ena_stats_tx tx_stats;
260 struct ena_stats_rx rx_stats;
263 } ____cacheline_aligned;
265 struct ena_stats_dev {
277 ENA_FLAG_DEVICE_RUNNING,
280 ENA_FLAG_MSIX_ENABLED,
281 ENA_FLAG_TRIGGER_RESET,
282 ENA_FLAG_ONGOING_RESET
285 /* adapter specific private data structure */
287 struct ena_com_dev *ena_dev;
288 /* OS defined structs */
289 struct net_device *netdev;
290 struct pci_dev *pdev;
292 /* rx packets that shorter that this len will be copied to the skb
302 u32 missing_tx_completion_threshold;
304 u32 tx_usecs, rx_usecs; /* interrupt moderation */
305 u32 tx_frames, rx_frames; /* interrupt moderation */
315 u8 mac_addr[ETH_ALEN];
317 unsigned long keep_alive_timeout;
318 unsigned long missing_tx_completion_to;
320 char name[ENA_NAME_MAX_LEN];
324 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
325 ____cacheline_aligned_in_smp;
328 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
329 ____cacheline_aligned_in_smp;
331 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
333 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
336 struct work_struct reset_task;
337 struct timer_list timer_service;
340 bool dev_up_before_reset;
341 unsigned long last_keep_alive_jiffies;
343 struct u64_stats_sync syncp;
344 struct ena_stats_dev dev_stats;
346 /* last queue index that was checked for uncompleted tx packets */
347 u32 last_monitored_tx_qid;
349 enum ena_regs_reset_reason_types reset_reason;
352 void ena_set_ethtool_ops(struct net_device *netdev);
354 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
356 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
358 int ena_get_sset_count(struct net_device *netdev, int sset);
360 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
362 * Since the max packet size the ENA handles is ~9kB limit the buffer length to
365 #if PAGE_SIZE > SZ_16K
366 #define ENA_PAGE_SIZE SZ_16K
368 #define ENA_PAGE_SIZE PAGE_SIZE
371 #endif /* !(ENA_H) */