2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 enum ena_admin_aq_opcode {
36 ENA_ADMIN_CREATE_SQ = 1,
38 ENA_ADMIN_DESTROY_SQ = 2,
40 ENA_ADMIN_CREATE_CQ = 3,
42 ENA_ADMIN_DESTROY_CQ = 4,
44 ENA_ADMIN_GET_FEATURE = 8,
46 ENA_ADMIN_SET_FEATURE = 9,
48 ENA_ADMIN_GET_STATS = 11,
51 enum ena_admin_aq_completion_status {
52 ENA_ADMIN_SUCCESS = 0,
54 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
56 ENA_ADMIN_BAD_OPCODE = 2,
58 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
60 ENA_ADMIN_MALFORMED_REQUEST = 4,
62 /* Additional status is provided in ACQ entry extended_status */
63 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
65 ENA_ADMIN_UNKNOWN_ERROR = 6,
68 enum ena_admin_aq_feature_id {
69 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
71 ENA_ADMIN_MAX_QUEUES_NUM = 2,
73 ENA_ADMIN_HW_HINTS = 3,
75 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
77 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
79 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
83 ENA_ADMIN_RSS_HASH_INPUT = 18,
85 ENA_ADMIN_INTERRUPT_MODERATION = 20,
87 ENA_ADMIN_AENQ_CONFIG = 26,
89 ENA_ADMIN_LINK_CONFIG = 27,
91 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
93 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
96 enum ena_admin_placement_policy_type {
97 /* descriptors and headers are in host memory */
98 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
100 /* descriptors and headers are in device memory (a.k.a Low Latency
103 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
106 enum ena_admin_link_types {
107 ENA_ADMIN_LINK_SPEED_1G = 0x1,
109 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
111 ENA_ADMIN_LINK_SPEED_5G = 0x4,
113 ENA_ADMIN_LINK_SPEED_10G = 0x8,
115 ENA_ADMIN_LINK_SPEED_25G = 0x10,
117 ENA_ADMIN_LINK_SPEED_40G = 0x20,
119 ENA_ADMIN_LINK_SPEED_50G = 0x40,
121 ENA_ADMIN_LINK_SPEED_100G = 0x80,
123 ENA_ADMIN_LINK_SPEED_200G = 0x100,
125 ENA_ADMIN_LINK_SPEED_400G = 0x200,
128 enum ena_admin_completion_policy_type {
129 /* completion queue entry for each sq descriptor */
130 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
132 /* completion queue entry upon request in sq descriptor */
133 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
135 /* current queue head pointer is updated in OS memory upon sq
138 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
140 /* current queue head pointer is updated in OS memory for each sq
143 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
146 /* basic stats return ena_admin_basic_stats while extanded stats return a
147 * buffer (string format) with additional statistics per queue and per
150 enum ena_admin_get_stats_type {
151 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
153 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
156 enum ena_admin_get_stats_scope {
157 ENA_ADMIN_SPECIFIC_QUEUE = 0,
159 ENA_ADMIN_ETH_TRAFFIC = 1,
162 struct ena_admin_aq_common_desc {
168 /* as appears in ena_admin_aq_opcode */
172 * 1 : ctrl_data - control buffer address valid
173 * 2 : ctrl_data_indirect - control buffer address
174 * points to list of pages with addresses of control
181 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
182 * page list chunk. Used also at the end of indirect mode page list chunks,
185 struct ena_admin_ctrl_buff_info {
188 struct ena_common_mem_addr address;
191 struct ena_admin_sq {
195 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
202 struct ena_admin_aq_entry {
203 struct ena_admin_aq_common_desc aq_common_descriptor;
206 u32 inline_data_w1[3];
208 struct ena_admin_ctrl_buff_info control_buffer;
211 u32 inline_data_w4[12];
214 struct ena_admin_acq_common_desc {
215 /* command identifier to associate it with the aq descriptor
230 /* serves as a hint what AQ entries can be revoked */
234 struct ena_admin_acq_entry {
235 struct ena_admin_acq_common_desc acq_common_descriptor;
237 u32 response_specific_data[14];
240 struct ena_admin_aq_create_sq_cmd {
241 struct ena_admin_aq_common_desc aq_common_descriptor;
243 /* 4:0 : reserved0_w1
244 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
250 /* 3:0 : placement_policy - Describing where the SQ
251 * descriptor ring and the SQ packet headers reside:
252 * 0x1 - descriptors and headers are in OS memory,
253 * 0x3 - descriptors and headers in device memory
254 * (a.k.a Low Latency Queue)
255 * 6:4 : completion_policy - Describing what policy
256 * to use for generation completion entry (cqe) in
257 * the CQ associated with this SQ: 0x0 - cqe for each
258 * sq descriptor, 0x1 - cqe upon request in sq
259 * descriptor, 0x2 - current queue head pointer is
260 * updated in OS memory upon sq descriptor request
261 * 0x3 - current queue head pointer is updated in OS
262 * memory for each sq descriptor
267 /* 0 : is_physically_contiguous - Described if the
268 * queue ring memory is allocated in physical
269 * contiguous pages or split.
270 * 7:1 : reserved17_w1
274 /* associated completion queue id. This CQ must be created prior to
279 /* submission queue depth in entries */
282 /* SQ physical base address in OS memory. This field should not be
283 * used for Low Latency queues. Has to be page aligned.
285 struct ena_common_mem_addr sq_ba;
287 /* specifies queue head writeback location in OS memory. Valid if
288 * completion_policy is set to completion_policy_head_on_demand or
289 * completion_policy_head. Has to be cache aligned
291 struct ena_common_mem_addr sq_head_writeback;
298 enum ena_admin_sq_direction {
299 ENA_ADMIN_SQ_DIRECTION_TX = 1,
301 ENA_ADMIN_SQ_DIRECTION_RX = 2,
304 struct ena_admin_acq_create_sq_resp_desc {
305 struct ena_admin_acq_common_desc acq_common_desc;
311 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
312 u32 sq_doorbell_offset;
314 /* low latency queue ring base address as an offset to PCIe MMIO
317 u32 llq_descriptors_offset;
319 /* low latency queue headers' memory as an offset to PCIe MMIO
322 u32 llq_headers_offset;
325 struct ena_admin_aq_destroy_sq_cmd {
326 struct ena_admin_aq_common_desc aq_common_descriptor;
328 struct ena_admin_sq sq;
331 struct ena_admin_acq_destroy_sq_resp_desc {
332 struct ena_admin_acq_common_desc acq_common_desc;
335 struct ena_admin_aq_create_cq_cmd {
336 struct ena_admin_aq_common_desc aq_common_descriptor;
339 * 5 : interrupt_mode_enabled - if set, cq operates
340 * in interrupt mode, otherwise - polling
345 /* 4:0 : cq_entry_size_words - size of CQ entry in
346 * 32-bit words, valid values: 4, 8.
351 /* completion queue depth in # of entries. must be power of 2 */
354 /* msix vector assigned to this cq */
357 /* cq physical base address in OS memory. CQ must be physically
360 struct ena_common_mem_addr cq_ba;
363 struct ena_admin_acq_create_cq_resp_desc {
364 struct ena_admin_acq_common_desc acq_common_desc;
368 /* actual cq depth in number of entries */
371 u32 numa_node_register_offset;
373 u32 cq_head_db_register_offset;
375 u32 cq_interrupt_unmask_register_offset;
378 struct ena_admin_aq_destroy_cq_cmd {
379 struct ena_admin_aq_common_desc aq_common_descriptor;
386 struct ena_admin_acq_destroy_cq_resp_desc {
387 struct ena_admin_acq_common_desc acq_common_desc;
390 /* ENA AQ Get Statistics command. Extended statistics are placed in control
391 * buffer pointed by AQ entry
393 struct ena_admin_aq_get_stats_cmd {
394 struct ena_admin_aq_common_desc aq_common_descriptor;
397 /* command specific inline data */
398 u32 inline_data_w1[3];
400 struct ena_admin_ctrl_buff_info control_buffer;
403 /* stats type as defined in enum ena_admin_get_stats_type */
406 /* stats scope defined in enum ena_admin_get_stats_scope */
411 /* queue id. used when scope is specific_queue */
414 /* device id, value 0xFFFF means mine. only privileged device can get
415 * stats of other device
420 /* Basic Statistics Command. */
421 struct ena_admin_basic_stats {
443 struct ena_admin_acq_get_stats_resp {
444 struct ena_admin_acq_common_desc acq_common_desc;
446 struct ena_admin_basic_stats basic_stats;
449 struct ena_admin_get_set_feature_common_desc {
450 /* 1:0 : select - 0x1 - current value; 0x3 - default
456 /* as appears in ena_admin_aq_feature_id */
462 struct ena_admin_device_attr_feature_desc {
467 /* bitmap of ena_admin_aq_feature_id */
468 u32 supported_features;
472 /* Indicates how many bits are used physical address access. */
475 /* Indicates how many bits are used virtual address access. */
478 /* unicast MAC address (in Network byte order) */
486 struct ena_admin_queue_feature_desc {
502 /* Maximum Descriptors number, including meta descriptor, allowed for
505 u16 max_packet_tx_descs;
507 /* Maximum Descriptors number allowed for a single Rx packet */
508 u16 max_packet_rx_descs;
511 struct ena_admin_set_feature_mtu_desc {
516 struct ena_admin_set_feature_host_attr_desc {
517 /* host OS info base address in OS memory. host info is 4KB of
518 * physically contiguous
520 struct ena_common_mem_addr os_info_ba;
522 /* host debug area base address in OS memory. debug area must be
523 * physically contiguous
525 struct ena_common_mem_addr debug_ba;
527 /* debug area size */
531 struct ena_admin_feature_intr_moder_desc {
532 /* interrupt delay granularity in usec */
533 u16 intr_delay_resolution;
538 struct ena_admin_get_feature_link_desc {
539 /* Link speed in Mb */
542 /* bit field of enum ena_admin_link types */
546 * 1 : duplex - Full Duplex
552 struct ena_admin_feature_aenq_desc {
553 /* bitmask for AENQ groups the device can report */
554 u32 supported_groups;
556 /* bitmask for AENQ groups to report */
560 struct ena_admin_feature_offload_desc {
561 /* 0 : TX_L3_csum_ipv4
562 * 1 : TX_L4_ipv4_csum_part - The checksum field
563 * should be initialized with pseudo header checksum
564 * 2 : TX_L4_ipv4_csum_full
565 * 3 : TX_L4_ipv6_csum_part - The checksum field
566 * should be initialized with pseudo header checksum
567 * 4 : TX_L4_ipv6_csum_full
574 /* Receive side supported stateless offload
575 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
576 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
577 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
578 * 3 : RX_hash - Hash calculation
585 enum ena_admin_hash_functions {
586 ENA_ADMIN_TOEPLITZ = 1,
591 struct ena_admin_feature_rss_flow_hash_control {
599 struct ena_admin_feature_rss_flow_hash_function {
600 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
603 /* 7:0 : selected_func - bitmask of
604 * ena_admin_hash_functions
612 /* RSS flow hash protocols */
613 enum ena_admin_flow_hash_proto {
614 ENA_ADMIN_RSS_TCP4 = 0,
616 ENA_ADMIN_RSS_UDP4 = 1,
618 ENA_ADMIN_RSS_TCP6 = 2,
620 ENA_ADMIN_RSS_UDP6 = 3,
622 ENA_ADMIN_RSS_IP4 = 4,
624 ENA_ADMIN_RSS_IP6 = 5,
626 ENA_ADMIN_RSS_IP4_FRAG = 6,
628 ENA_ADMIN_RSS_NOT_IP = 7,
630 ENA_ADMIN_RSS_PROTO_NUM = 16,
633 /* RSS flow hash fields */
634 enum ena_admin_flow_hash_fields {
635 /* Ethernet Dest Addr */
636 ENA_ADMIN_RSS_L2_DA = BIT(0),
638 /* Ethernet Src Addr */
639 ENA_ADMIN_RSS_L2_SA = BIT(1),
641 /* ipv4/6 Dest Addr */
642 ENA_ADMIN_RSS_L3_DA = BIT(2),
644 /* ipv4/6 Src Addr */
645 ENA_ADMIN_RSS_L3_SA = BIT(3),
647 /* tcp/udp Dest Port */
648 ENA_ADMIN_RSS_L4_DP = BIT(4),
650 /* tcp/udp Src Port */
651 ENA_ADMIN_RSS_L4_SP = BIT(5),
654 struct ena_admin_proto_input {
655 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
661 struct ena_admin_feature_rss_hash_control {
662 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
664 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
666 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
668 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
671 struct ena_admin_feature_rss_flow_hash_input {
672 /* supported hash input sorting
673 * 1 : L3_sort - support swap L3 addresses if DA is
675 * 2 : L4_sort - support swap L4 ports if DP smaller
678 u16 supported_input_sort;
680 /* enabled hash input sorting
681 * 1 : enable_L3_sort - enable swap L3 addresses if
683 * 2 : enable_L4_sort - enable swap L4 ports if DP
686 u16 enabled_input_sort;
689 enum ena_admin_os_type {
690 ENA_ADMIN_OS_LINUX = 1,
692 ENA_ADMIN_OS_WIN = 2,
694 ENA_ADMIN_OS_DPDK = 3,
696 ENA_ADMIN_OS_FREEBSD = 4,
698 ENA_ADMIN_OS_IPXE = 5,
701 struct ena_admin_host_info {
702 /* defined in enum ena_admin_os_type */
705 /* os distribution string format */
708 /* OS distribution numeric format */
711 /* kernel version string format */
712 u8 kernel_ver_str[32];
714 /* Kernel version numeric format */
723 /* features bitmap */
724 u32 supported_network_features[4];
727 struct ena_admin_rss_ind_table_entry {
733 struct ena_admin_feature_rss_ind_table {
734 /* min supported table size (2^min_size) */
737 /* max supported table size (2^max_size) */
740 /* table size (2^size) */
745 /* index of the inline entry. 0xFFFFFFFF means invalid */
748 /* used for updating single entry, ignored when setting the entire
749 * table through the control buffer.
751 struct ena_admin_rss_ind_table_entry inline_entry;
754 /* When hint value is 0, driver should use it's own predefined value */
755 struct ena_admin_ena_hw_hints {
757 u16 mmio_read_timeout;
760 u16 driver_watchdog_timeout;
762 /* Per packet tx completion timeout. value in ms */
763 u16 missing_tx_completion_timeout;
765 u16 missed_tx_completion_count_threshold_to_reset;
768 u16 admin_completion_tx_timeout;
770 u16 netdev_wd_timeout;
779 struct ena_admin_get_feat_cmd {
780 struct ena_admin_aq_common_desc aq_common_descriptor;
782 struct ena_admin_ctrl_buff_info control_buffer;
784 struct ena_admin_get_set_feature_common_desc feat_common;
789 struct ena_admin_get_feat_resp {
790 struct ena_admin_acq_common_desc acq_common_desc;
795 struct ena_admin_device_attr_feature_desc dev_attr;
797 struct ena_admin_queue_feature_desc max_queue;
799 struct ena_admin_feature_aenq_desc aenq;
801 struct ena_admin_get_feature_link_desc link;
803 struct ena_admin_feature_offload_desc offload;
805 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
807 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
809 struct ena_admin_feature_rss_ind_table ind_table;
811 struct ena_admin_feature_intr_moder_desc intr_moderation;
813 struct ena_admin_ena_hw_hints hw_hints;
817 struct ena_admin_set_feat_cmd {
818 struct ena_admin_aq_common_desc aq_common_descriptor;
820 struct ena_admin_ctrl_buff_info control_buffer;
822 struct ena_admin_get_set_feature_common_desc feat_common;
828 struct ena_admin_set_feature_mtu_desc mtu;
830 /* host attributes */
831 struct ena_admin_set_feature_host_attr_desc host_attr;
833 /* AENQ configuration */
834 struct ena_admin_feature_aenq_desc aenq;
836 /* rss flow hash function */
837 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
839 /* rss flow hash input */
840 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
842 /* rss indirection table */
843 struct ena_admin_feature_rss_ind_table ind_table;
847 struct ena_admin_set_feat_resp {
848 struct ena_admin_acq_common_desc acq_common_desc;
855 struct ena_admin_aenq_common_desc {
870 /* asynchronous event notification groups */
871 enum ena_admin_aenq_group {
872 ENA_ADMIN_LINK_CHANGE = 0,
874 ENA_ADMIN_FATAL_ERROR = 1,
876 ENA_ADMIN_WARNING = 2,
878 ENA_ADMIN_NOTIFICATION = 3,
880 ENA_ADMIN_KEEP_ALIVE = 4,
882 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
885 enum ena_admin_aenq_notification_syndrom {
886 ENA_ADMIN_SUSPEND = 0,
888 ENA_ADMIN_RESUME = 1,
890 ENA_ADMIN_UPDATE_HINTS = 2,
893 struct ena_admin_aenq_entry {
894 struct ena_admin_aenq_common_desc aenq_common_desc;
896 /* command specific inline data */
897 u32 inline_data_w4[12];
900 struct ena_admin_aenq_link_change_desc {
901 struct ena_admin_aenq_common_desc aenq_common_desc;
903 /* 0 : link_status */
907 struct ena_admin_aenq_keep_alive_desc {
908 struct ena_admin_aenq_common_desc aenq_common_desc;
915 struct ena_admin_ena_mmio_req_read_less_resp {
920 /* value is valid when poll is cleared */
925 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
926 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
927 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
928 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
929 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
930 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
933 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
934 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
936 /* acq_common_desc */
937 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
938 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
940 /* aq_create_sq_cmd */
941 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
942 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
943 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
944 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
945 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
946 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
948 /* aq_create_cq_cmd */
949 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
950 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
951 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
953 /* get_set_feature_common_desc */
954 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
956 /* get_feature_link_desc */
957 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
958 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
959 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
961 /* feature_offload_desc */
962 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
963 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
964 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
965 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
966 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
967 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
968 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
969 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
970 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
971 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
972 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
973 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
974 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
975 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
976 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
977 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
978 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
979 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
980 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
981 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
982 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
983 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
985 /* feature_rss_flow_hash_function */
986 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
987 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
989 /* feature_rss_flow_hash_input */
990 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
991 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
992 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
993 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
994 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
995 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
996 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
997 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1000 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1001 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1002 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1003 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1004 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1006 /* aenq_common_desc */
1007 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1009 /* aenq_link_change_desc */
1010 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1012 #endif /*_ENA_ADMIN_H_ */