1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <linux/interrupt.h>
8 * Generate TX index update each time, when TX ring is closed.
9 * Normally, this is not useful, because results in more dma (and irqs
10 * without TX_COAL_INTS_ONLY).
12 #define USE_TX_COAL_NOW 0
17 * The Tigon uses 64-bit host addresses, regardless of their actual
18 * length, and it expects a big-endian format. For 32 bit systems the
19 * upper 32 bits of the address are simply ignored (zero), however for
20 * little endian 64 bit systems (Alpha) this looks strange with the
21 * two parts of the address word being swapped.
23 * The addresses are split in two 32 bit words for all architectures
24 * as some of them are in PCI shared memory and it is necessary to use
25 * readl/writel to access them.
27 * The addressing code is derived from Pete Wyckoff's work, but
28 * modified to deal properly with readl/writel usage.
32 u32 pad0[16]; /* PCI control registers */
34 u32 HostCtrl; /* 0x40 */
39 u32 MiscCfg; /* 0x50 */
45 u32 pad3[2]; /* 0x60 */
50 u32 pad4[12]; /* 0x70 */
52 u32 DmaWriteState; /* 0xa0 */
54 u32 DmaReadState; /* 0xb0 */
60 u32 pad7[8]; /* 0x120 */
62 u32 CpuCtrl; /* 0x140 */
67 u32 SramAddr; /* 0x154 */
72 u32 MacRxState; /* 0x220 */
76 u32 CpuBCtrl; /* 0x240 */
81 u32 SramBAddr; /* 0x254 */
86 u32 pad13[32]; /* 0x400 */
89 u32 Mb0Hi; /* 0x500 */
124 u32 MacAddrHi; /* 0x600 */
128 u32 MultiCastHi; /* 0x610 */
132 u32 DmaWriteCfg; /* 0x620 */
136 u32 TuneRxCoalTicks;/* 0x630 */
140 u32 TuneMaxRxDesc; /* 0x640 */
144 u32 TracePtr; /* 0x650 */
148 u32 IfMtu; /* 0x660 */
152 u32 pad16[4]; /* 0x670 */
153 u32 RxRetCsm; /* 0x680 */
157 u32 CmdRng[64]; /* 0x700 */
168 #define ACE_WINDOW_SIZE 0x800
170 #define ACE_JUMBO_MTU 9000
171 #define ACE_STD_MTU 1500
173 #define ACE_TRACE_SIZE 0x8000
176 * Host control register bits.
181 #define HW_RESET 0x08
182 #define BYTE_SWAP 0x10
183 #define WORD_SWAP 0x20
184 #define MASK_INTS 0x40
187 * Local control register bits.
190 #define EEPROM_DATA_IN 0x800000
191 #define EEPROM_DATA_OUT 0x400000
192 #define EEPROM_WRITE_ENABLE 0x200000
193 #define EEPROM_CLK_OUT 0x100000
195 #define EEPROM_BASE 0xa0000000
197 #define EEPROM_WRITE_SELECT 0xa0
198 #define EEPROM_READ_SELECT 0xa1
200 #define SRAM_BANK_512K 0x200
204 * udelay() values for when clocking the eeprom
206 #define ACE_SHORT_DELAY 2
207 #define ACE_LONG_DELAY 4
214 #define SYNC_SRAM_TIMING 0x100000
221 #define CPU_RESET 0x01
222 #define CPU_TRACE 0x02
223 #define CPU_PROM_FAILED 0x10
224 #define CPU_HALT 0x00010000
225 #define CPU_HALTED 0xffff0000
232 #define DMA_READ_MAX_4 0x04
233 #define DMA_READ_MAX_16 0x08
234 #define DMA_READ_MAX_32 0x0c
235 #define DMA_READ_MAX_64 0x10
236 #define DMA_READ_MAX_128 0x14
237 #define DMA_READ_MAX_256 0x18
238 #define DMA_READ_MAX_1K 0x1c
239 #define DMA_WRITE_MAX_4 0x20
240 #define DMA_WRITE_MAX_16 0x40
241 #define DMA_WRITE_MAX_32 0x60
242 #define DMA_WRITE_MAX_64 0x80
243 #define DMA_WRITE_MAX_128 0xa0
244 #define DMA_WRITE_MAX_256 0xc0
245 #define DMA_WRITE_MAX_1K 0xe0
246 #define DMA_READ_WRITE_MASK 0xfc
247 #define MEM_READ_MULTIPLE 0x00020000
248 #define PCI_66MHZ 0x00080000
249 #define PCI_32BIT 0x00100000
250 #define DMA_WRITE_ALL_ALIGN 0x00800000
251 #define READ_CMD_MEM 0x06000000
252 #define WRITE_CMD_MEM 0x70000000
259 #define ACE_BYTE_SWAP_BD 0x02
260 #define ACE_WORD_SWAP_BD 0x04 /* not actually used */
261 #define ACE_WARN 0x08
262 #define ACE_BYTE_SWAP_DMA 0x10
263 #define ACE_NO_JUMBO_FRAG 0x200
264 #define ACE_FATAL 0x40000000
271 #define DMA_THRESH_1W 0x10
272 #define DMA_THRESH_2W 0x20
273 #define DMA_THRESH_4W 0x40
274 #define DMA_THRESH_8W 0x80
275 #define DMA_THRESH_16W 0x100
276 #define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */
283 #define TICKS_PER_SEC 1000000
290 #define LNK_PREF 0x00008000
291 #define LNK_10MB 0x00010000
292 #define LNK_100MB 0x00020000
293 #define LNK_1000MB 0x00040000
294 #define LNK_FULL_DUPLEX 0x00080000
295 #define LNK_HALF_DUPLEX 0x00100000
296 #define LNK_TX_FLOW_CTL_Y 0x00200000
297 #define LNK_NEG_ADVANCED 0x00400000
298 #define LNK_RX_FLOW_CTL_Y 0x00800000
299 #define LNK_NIC 0x01000000
300 #define LNK_JAM 0x02000000
301 #define LNK_JUMBO 0x04000000
302 #define LNK_ALTEON 0x08000000
303 #define LNK_NEG_FCTL 0x10000000
304 #define LNK_NEGOTIATE 0x20000000
305 #define LNK_ENABLE 0x40000000
306 #define LNK_UP 0x80000000
313 #define EVT_RING_ENTRIES 256
314 #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
317 #ifdef __LITTLE_ENDIAN_BITFIELD
334 #define E_FW_RUNNING 0x01
335 #define E_STATS_UPDATED 0x04
337 #define E_STATS_UPDATE 0x04
339 #define E_LNK_STATE 0x06
340 #define E_C_LINK_UP 0x01
341 #define E_C_LINK_DOWN 0x02
342 #define E_C_LINK_10_100 0x03
345 #define E_C_ERR_INVAL_CMD 0x01
346 #define E_C_ERR_UNIMP_CMD 0x02
347 #define E_C_ERR_BAD_CFG 0x03
349 #define E_MCAST_LIST 0x08
350 #define E_C_MCAST_ADDR_ADD 0x01
351 #define E_C_MCAST_ADDR_DEL 0x02
353 #define E_RESET_JUMBO_RNG 0x09
360 #define CMD_RING_ENTRIES 64
363 #ifdef __LITTLE_ENDIAN_BITFIELD
375 #define C_HOST_STATE 0x01
376 #define C_C_STACK_UP 0x01
377 #define C_C_STACK_DOWN 0x02
379 #define C_FDR_FILTERING 0x02
380 #define C_C_FDR_FILT_ENABLE 0x01
381 #define C_C_FDR_FILT_DISABLE 0x02
383 #define C_SET_RX_PRD_IDX 0x03
384 #define C_UPDATE_STATS 0x04
385 #define C_RESET_JUMBO_RNG 0x05
386 #define C_ADD_MULTICAST_ADDR 0x08
387 #define C_DEL_MULTICAST_ADDR 0x09
389 #define C_SET_PROMISC_MODE 0x0a
390 #define C_C_PROMISC_ENABLE 0x01
391 #define C_C_PROMISC_DISABLE 0x02
393 #define C_LNK_NEGOTIATION 0x0b
394 #define C_C_NEGOTIATE_BOTH 0x00
395 #define C_C_NEGOTIATE_GIG 0x01
396 #define C_C_NEGOTIATE_10_100 0x02
398 #define C_SET_MAC_ADDR 0x0c
399 #define C_CLEAR_PROFILE 0x0d
401 #define C_SET_MULTICAST_MODE 0x0e
402 #define C_C_MCAST_ENABLE 0x01
403 #define C_C_MCAST_DISABLE 0x02
405 #define C_CLEAR_STATS 0x0f
406 #define C_SET_RX_JUMBO_PRD_IDX 0x10
407 #define C_REFRESH_STATS 0x11
413 #define BD_FLG_TCP_UDP_SUM 0x01
414 #define BD_FLG_IP_SUM 0x02
415 #define BD_FLG_END 0x04
416 #define BD_FLG_MORE 0x08
417 #define BD_FLG_JUMBO 0x10
418 #define BD_FLG_UCAST 0x20
419 #define BD_FLG_MCAST 0x40
420 #define BD_FLG_BCAST 0x60
421 #define BD_FLG_TYP_MASK 0x60
422 #define BD_FLG_IP_FRAG 0x80
423 #define BD_FLG_IP_FRAG_END 0x100
424 #define BD_FLG_VLAN_TAG 0x200
425 #define BD_FLG_FRAME_ERROR 0x400
426 #define BD_FLG_COAL_NOW 0x800
427 #define BD_FLG_MINI 0x1000
431 * Ring Control block flags
433 #define RCB_FLG_TCP_UDP_SUM 0x01
434 #define RCB_FLG_IP_SUM 0x02
435 #define RCB_FLG_NO_PSEUDO_HDR 0x08
436 #define RCB_FLG_VLAN_ASSIST 0x10
437 #define RCB_FLG_COAL_INT_ONLY 0x20
438 #define RCB_FLG_TX_HOST_RING 0x40
439 #define RCB_FLG_IEEE_SNAP_SUM 0x80
440 #define RCB_FLG_EXT_RX_BD 0x100
441 #define RCB_FLG_RNG_DISABLE 0x200
445 * TX ring - maximum TX ring entries for Tigon I's is 128
447 #define MAX_TX_RING_ENTRIES 256
448 #define TIGON_I_TX_RING_ENTRIES 128
449 #define TX_RING_SIZE (MAX_TX_RING_ENTRIES * sizeof(struct tx_desc))
450 #define TX_RING_BASE 0x3800
457 * This is in PCI shared mem and must be accessed with readl/writel
476 #define RX_STD_RING_ENTRIES 512
477 #define RX_STD_RING_SIZE (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
479 #define RX_JUMBO_RING_ENTRIES 256
480 #define RX_JUMBO_RING_SIZE (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
482 #define RX_MINI_RING_ENTRIES 1024
483 #define RX_MINI_RING_SIZE (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
485 #define RX_RETURN_RING_ENTRIES 2048
486 #define RX_RETURN_RING_SIZE (RX_MAX_RETURN_RING_ENTRIES * \
487 sizeof(struct rx_desc))
491 #ifdef __LITTLE_ENDIAN
498 #ifdef __LITTLE_ENDIAN
505 #ifdef __LITTLE_ENDIAN
512 #ifdef __LITTLE_ENDIAN
525 * This struct is shared with the NIC firmware.
529 #ifdef __LITTLE_ENDIAN
540 struct ace_mac_stats {
578 struct ring_ctrl evt_ctrl;
579 struct ring_ctrl cmd_ctrl;
580 struct ring_ctrl tx_ctrl;
581 struct ring_ctrl rx_std_ctrl;
582 struct ring_ctrl rx_jumbo_ctrl;
583 struct ring_ctrl rx_mini_ctrl;
584 struct ring_ctrl rx_return_ctrl;
586 aceaddr rx_ret_prd_ptr;
594 DEFINE_DMA_UNMAP_ADDR(mapping);
599 * Funny... As soon as we add maplen on alpha, it starts to work
600 * much slower. Hmm... is it because struct does not fit to one cacheline?
601 * So, split tx_ring_info.
603 struct tx_ring_info {
605 DEFINE_DMA_UNMAP_ADDR(mapping);
606 DEFINE_DMA_UNMAP_LEN(maplen);
611 * struct ace_skb holding the rings of skb's. This is an awful lot of
612 * pointers, but I don't see any other smart mode to do this in an
613 * efficient manner ;-(
617 struct tx_ring_info tx_skbuff[MAX_TX_RING_ENTRIES];
618 struct ring_info rx_std_skbuff[RX_STD_RING_ENTRIES];
619 struct ring_info rx_mini_skbuff[RX_MINI_RING_ENTRIES];
620 struct ring_info rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
625 * Struct private for the AceNIC.
627 * Elements are grouped so variables used by the tx handling goes
628 * together, and will go into the same cache lines etc. in order to
629 * avoid cache line contention between the rx and tx handling on SMP.
631 * Frequently accessed variables are put at the beginning of the
632 * struct to help the compiler generate better/shorter code.
636 struct net_device *ndev; /* backpointer */
637 struct ace_info *info;
638 struct ace_regs __iomem *regs; /* register base */
640 dma_addr_t info_dma; /* 32/64 bit */
643 int promisc, mcast_all;
648 struct tx_desc *tx_ring;
650 volatile u32 tx_ret_csm;
656 unsigned long std_refill_busy
657 __attribute__ ((aligned (SMP_CACHE_BYTES)));
658 unsigned long mini_refill_busy, jumbo_refill_busy;
659 atomic_t cur_rx_bufs;
660 atomic_t cur_mini_bufs;
661 atomic_t cur_jumbo_bufs;
662 u32 rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
665 struct rx_desc *rx_std_ring;
666 struct rx_desc *rx_jumbo_ring;
667 struct rx_desc *rx_mini_ring;
668 struct rx_desc *rx_return_ring;
670 int tasklet_pending, jumbo;
671 struct tasklet_struct ace_tasklet;
673 struct event *evt_ring;
675 volatile u32 *evt_prd, *rx_ret_prd, *tx_csm;
677 dma_addr_t tx_ring_dma; /* 32/64 bit */
678 dma_addr_t rx_ring_base_dma;
679 dma_addr_t evt_ring_dma;
680 dma_addr_t evt_prd_dma, rx_ret_prd_dma, tx_csm_dma;
682 unsigned char *trace_buf;
683 struct pci_dev *pdev;
684 struct net_device *next;
685 volatile int fw_running;
691 spinlock_t debug_lock
692 __attribute__ ((aligned (SMP_CACHE_BYTES)));
693 u32 last_tx, last_std_rx, last_mini_rx;
703 #define TX_RESERVED MAX_SKB_FRAGS
705 static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd)
707 return (csm - prd - 1) & (ACE_TX_RING_ENTRIES(ap) - 1);
710 #define tx_free(ap) tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap)
711 #define tx_ring_full(ap, csm, prd) (tx_space(ap, csm, prd) <= TX_RESERVED)
713 static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr)
715 u64 baddr = (u64) addr;
716 aa->addrlo = baddr & 0xffffffff;
717 aa->addrhi = baddr >> 32;
722 static inline void ace_set_txprd(struct ace_regs __iomem *regs,
723 struct ace_private *ap, u32 value)
727 spin_lock_irqsave(&ap->debug_lock, flags);
728 writel(value, ®s->TxPrd);
729 if (value == ap->last_tx)
730 printk(KERN_ERR "AceNIC RACE ALERT! writing identical value "
731 "to tx producer (%i)\n", value);
733 spin_unlock_irqrestore(&ap->debug_lock, flags);
735 writel(value, ®s->TxPrd);
741 static inline void ace_mask_irq(struct net_device *dev)
743 struct ace_private *ap = netdev_priv(dev);
744 struct ace_regs __iomem *regs = ap->regs;
746 if (ACE_IS_TIGON_I(ap))
747 writel(1, ®s->MaskInt);
749 writel(readl(®s->HostCtrl) | MASK_INTS, ®s->HostCtrl);
751 ace_sync_irq(dev->irq);
755 static inline void ace_unmask_irq(struct net_device *dev)
757 struct ace_private *ap = netdev_priv(dev);
758 struct ace_regs __iomem *regs = ap->regs;
760 if (ACE_IS_TIGON_I(ap))
761 writel(0, ®s->MaskInt);
763 writel(readl(®s->HostCtrl) & ~MASK_INTS, ®s->HostCtrl);
770 static int ace_init(struct net_device *dev);
771 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs);
772 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs);
773 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs);
774 static irqreturn_t ace_interrupt(int irq, void *dev_id);
775 static int ace_load_firmware(struct net_device *dev);
776 static int ace_open(struct net_device *dev);
777 static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
778 struct net_device *dev);
779 static int ace_close(struct net_device *dev);
780 static void ace_tasklet(struct tasklet_struct *t);
781 static void ace_dump_trace(struct ace_private *ap);
782 static void ace_set_multicast_list(struct net_device *dev);
783 static int ace_change_mtu(struct net_device *dev, int new_mtu);
784 static int ace_set_mac_addr(struct net_device *dev, void *p);
785 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo);
786 static int ace_allocate_descriptors(struct net_device *dev);
787 static void ace_free_descriptors(struct net_device *dev);
788 static void ace_init_cleanup(struct net_device *dev);
789 static struct net_device_stats *ace_get_stats(struct net_device *dev);
790 static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
792 #endif /* _ACENIC_H_ */