2 * Allwinner EMAC Fast Ethernet driver for Linux.
4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
7 * Based on the Linux driver provided by Allwinner:
8 * Copyright (C) 1997 Sten Wang
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/clk.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/gpio.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/mii.h>
22 #include <linux/module.h>
23 #include <linux/netdevice.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
31 #include <linux/soc/sunxi/sunxi_sram.h>
33 #include "sun4i-emac.h"
35 #define DRV_NAME "sun4i-emac"
37 #define EMAC_MAX_FRAME_LEN 0x0600
39 #define EMAC_DEFAULT_MSG_ENABLE 0x0000
40 static int debug = -1; /* defaults above */;
41 module_param(debug, int, 0);
42 MODULE_PARM_DESC(debug, "debug message flags");
44 /* Transmit timeout, default 5 seconds. */
45 static int watchdog = 5000;
46 module_param(watchdog, int, 0400);
47 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
49 /* EMAC register address locking.
51 * The EMAC uses an address register to control where data written
52 * to the data register goes. This means that the address register
53 * must be preserved over interrupts or similar calls.
55 * During interrupt and other critical calls, a spinlock is used to
56 * protect the system, but the calls themselves save the address
57 * in the address register in case they are interrupting another
58 * access to the device.
60 * For general accesses a lock is provided so that calls which are
61 * allowed to sleep are serialised so that the address register does
62 * not need to be saved. This lock also serves to serialise access
63 * to the EEPROM and PHY access registers which are shared between
67 /* The driver supports the original EMACE, and now the two newer
68 * devices, EMACA and EMACB.
71 struct emac_board_info {
74 struct platform_device *pdev;
76 void __iomem *membase;
78 struct net_device *ndev;
79 struct sk_buff *skb_last;
82 int emacrx_completed_flag;
84 struct device_node *phy_node;
89 phy_interface_t phy_interface;
92 static void emac_update_speed(struct net_device *dev)
94 struct emac_board_info *db = netdev_priv(dev);
97 /* set EMAC SPEED, depend on PHY */
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
99 reg_val &= ~(0x1 << 8);
100 if (db->speed == SPEED_100)
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
105 static void emac_update_duplex(struct net_device *dev)
107 struct emac_board_info *db = netdev_priv(dev);
108 unsigned int reg_val;
110 /* set duplex depend on phy */
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
118 static void emac_handle_link_change(struct net_device *dev)
120 struct emac_board_info *db = netdev_priv(dev);
121 struct phy_device *phydev = dev->phydev;
123 int status_change = 0;
126 if (db->speed != phydev->speed) {
127 spin_lock_irqsave(&db->lock, flags);
128 db->speed = phydev->speed;
129 emac_update_speed(dev);
130 spin_unlock_irqrestore(&db->lock, flags);
134 if (db->duplex != phydev->duplex) {
135 spin_lock_irqsave(&db->lock, flags);
136 db->duplex = phydev->duplex;
137 emac_update_duplex(dev);
138 spin_unlock_irqrestore(&db->lock, flags);
143 if (phydev->link != db->link) {
148 db->link = phydev->link;
154 phy_print_status(phydev);
157 static int emac_mdio_probe(struct net_device *dev)
159 struct emac_board_info *db = netdev_priv(dev);
160 struct phy_device *phydev;
162 /* to-do: PHY interrupts are currently not supported */
164 /* attach the mac to the phy */
165 phydev = of_phy_connect(db->ndev, db->phy_node,
166 &emac_handle_link_change, 0,
169 netdev_err(db->ndev, "could not find the PHY\n");
173 /* mask with MAC supported features */
174 phy_set_max_speed(phydev, SPEED_100);
183 static void emac_mdio_remove(struct net_device *dev)
185 phy_disconnect(dev->phydev);
188 static void emac_reset(struct emac_board_info *db)
190 dev_dbg(db->dev, "resetting device\n");
193 writel(0, db->membase + EMAC_CTL_REG);
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
199 static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
201 writesl(reg, data, round_up(count, 4) / 4);
204 static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
206 readsl(reg, data, round_up(count, 4) / 4);
210 static void emac_get_drvinfo(struct net_device *dev,
211 struct ethtool_drvinfo *info)
213 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
214 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
217 static u32 emac_get_msglevel(struct net_device *dev)
219 struct emac_board_info *db = netdev_priv(dev);
221 return db->msg_enable;
224 static void emac_set_msglevel(struct net_device *dev, u32 value)
226 struct emac_board_info *db = netdev_priv(dev);
228 db->msg_enable = value;
231 static const struct ethtool_ops emac_ethtool_ops = {
232 .get_drvinfo = emac_get_drvinfo,
233 .get_link = ethtool_op_get_link,
234 .get_link_ksettings = phy_ethtool_get_link_ksettings,
235 .set_link_ksettings = phy_ethtool_set_link_ksettings,
236 .get_msglevel = emac_get_msglevel,
237 .set_msglevel = emac_set_msglevel,
240 static unsigned int emac_setup(struct net_device *ndev)
242 struct emac_board_info *db = netdev_priv(ndev);
243 unsigned int reg_val;
246 reg_val = readl(db->membase + EMAC_TX_MODE_REG);
248 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
249 db->membase + EMAC_TX_MODE_REG);
253 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
254 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
255 EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
256 db->membase + EMAC_MAC_CTL0_REG);
259 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
260 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
261 reg_val |= EMAC_MAC_CTL1_CRC_EN;
262 reg_val |= EMAC_MAC_CTL1_PAD_EN;
263 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
266 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
269 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
270 db->membase + EMAC_MAC_IPGR_REG);
272 /* set up Collison window */
273 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
274 db->membase + EMAC_MAC_CLRT_REG);
276 /* set up Max Frame Length */
277 writel(EMAC_MAX_FRAME_LEN,
278 db->membase + EMAC_MAC_MAXF_REG);
283 static void emac_set_rx_mode(struct net_device *ndev)
285 struct emac_board_info *db = netdev_priv(ndev);
286 unsigned int reg_val;
289 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
291 if (ndev->flags & IFF_PROMISC)
292 reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
294 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
296 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
297 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
298 EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
299 EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
300 db->membase + EMAC_RX_CTL_REG);
303 static unsigned int emac_powerup(struct net_device *ndev)
305 struct emac_board_info *db = netdev_priv(ndev);
306 unsigned int reg_val;
310 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
312 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
317 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
318 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
319 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
322 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
323 reg_val &= (~(0xf << 2));
324 reg_val |= (0xD << 2);
325 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
327 /* clear RX counter */
328 writel(0x0, db->membase + EMAC_RX_FBC_REG);
330 /* disable all interrupt and clear interrupt status */
331 writel(0, db->membase + EMAC_INT_CTL_REG);
332 reg_val = readl(db->membase + EMAC_INT_STA_REG);
333 writel(reg_val, db->membase + EMAC_INT_STA_REG);
340 /* set mac_address to chip */
341 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
342 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
343 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
344 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
351 static int emac_set_mac_address(struct net_device *dev, void *p)
353 struct sockaddr *addr = p;
354 struct emac_board_info *db = netdev_priv(dev);
356 if (netif_running(dev))
359 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
361 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
362 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
363 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
364 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
369 /* Initialize emac board */
370 static void emac_init_device(struct net_device *dev)
372 struct emac_board_info *db = netdev_priv(dev);
374 unsigned int reg_val;
376 spin_lock_irqsave(&db->lock, flags);
378 emac_update_speed(dev);
379 emac_update_duplex(dev);
382 reg_val = readl(db->membase + EMAC_CTL_REG);
383 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
384 db->membase + EMAC_CTL_REG);
386 /* enable RX/TX0/RX Hlevel interrup */
387 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
388 reg_val |= (0xf << 0) | (0x01 << 8);
389 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
391 spin_unlock_irqrestore(&db->lock, flags);
394 /* Our watchdog timed out. Called by the networking layer */
395 static void emac_timeout(struct net_device *dev, unsigned int txqueue)
397 struct emac_board_info *db = netdev_priv(dev);
400 if (netif_msg_timer(db))
401 dev_err(db->dev, "tx time out.\n");
403 /* Save previous register address */
404 spin_lock_irqsave(&db->lock, flags);
406 netif_stop_queue(dev);
408 emac_init_device(dev);
409 /* We can accept TX packets again */
410 netif_trans_update(dev);
411 netif_wake_queue(dev);
413 /* Restore previous register address */
414 spin_unlock_irqrestore(&db->lock, flags);
417 /* Hardware start transmission.
418 * Send a packet to media from the upper layer.
420 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
422 struct emac_board_info *db = netdev_priv(dev);
423 unsigned long channel;
426 channel = db->tx_fifo_stat & 3;
428 return NETDEV_TX_BUSY;
430 channel = (channel == 1 ? 1 : 0);
432 spin_lock_irqsave(&db->lock, flags);
434 writel(channel, db->membase + EMAC_TX_INS_REG);
436 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
437 skb->data, skb->len);
438 dev->stats.tx_bytes += skb->len;
440 db->tx_fifo_stat |= 1 << channel;
441 /* TX control: First packet immediately send, second packet queue */
444 writel(skb->len, db->membase + EMAC_TX_PL0_REG);
445 /* start translate from fifo to phy */
446 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
447 db->membase + EMAC_TX_CTL0_REG);
449 /* save the time stamp */
450 netif_trans_update(dev);
451 } else if (channel == 1) {
453 writel(skb->len, db->membase + EMAC_TX_PL1_REG);
454 /* start translate from fifo to phy */
455 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
456 db->membase + EMAC_TX_CTL1_REG);
458 /* save the time stamp */
459 netif_trans_update(dev);
462 if ((db->tx_fifo_stat & 3) == 3) {
464 netif_stop_queue(dev);
467 spin_unlock_irqrestore(&db->lock, flags);
470 dev_consume_skb_any(skb);
475 /* EMAC interrupt handler
476 * receive the packet to upper layer, free the transmitted packet
478 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
479 unsigned int tx_status)
481 /* One packet sent complete */
482 db->tx_fifo_stat &= ~(tx_status & 3);
483 if (3 == (tx_status & 3))
484 dev->stats.tx_packets += 2;
486 dev->stats.tx_packets++;
488 if (netif_msg_tx_done(db))
489 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
491 netif_wake_queue(dev);
494 /* Received a packet and pass to upper layer
496 static void emac_rx(struct net_device *dev)
498 struct emac_board_info *db = netdev_priv(dev);
502 static int rxlen_last;
503 unsigned int reg_val;
504 u32 rxhdr, rxstatus, rxcount, rxlen;
506 /* Check packet ready or not */
508 /* race warning: the first packet might arrive with
509 * the interrupts disabled, but the second will fix
512 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
514 if (netif_msg_rx_status(db))
515 dev_dbg(db->dev, "RXCount: %x\n", rxcount);
517 if ((db->skb_last != NULL) && (rxlen_last > 0)) {
518 dev->stats.rx_bytes += rxlen_last;
520 /* Pass to upper layer */
521 db->skb_last->protocol = eth_type_trans(db->skb_last,
523 netif_rx(db->skb_last);
524 dev->stats.rx_packets++;
528 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
529 reg_val &= ~EMAC_RX_CTL_DMA_EN;
530 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
534 db->emacrx_completed_flag = 1;
535 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
536 reg_val |= (0xf << 0) | (0x01 << 8);
537 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
540 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
545 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
546 if (netif_msg_rx_status(db))
547 dev_dbg(db->dev, "receive header: %x\n", reg_val);
548 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
550 reg_val = readl(db->membase + EMAC_CTL_REG);
551 writel(reg_val & ~EMAC_CTL_RX_EN,
552 db->membase + EMAC_CTL_REG);
555 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
556 writel(reg_val | (1 << 3),
557 db->membase + EMAC_RX_CTL_REG);
560 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
561 } while (reg_val & (1 << 3));
564 reg_val = readl(db->membase + EMAC_CTL_REG);
565 writel(reg_val | EMAC_CTL_RX_EN,
566 db->membase + EMAC_CTL_REG);
567 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
568 reg_val |= (0xf << 0) | (0x01 << 8);
569 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
571 db->emacrx_completed_flag = 1;
576 /* A packet ready now & Get status/length */
579 rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG);
581 if (netif_msg_rx_status(db))
582 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
584 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
585 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
587 if (netif_msg_rx_status(db))
588 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
591 /* Packet Status check */
594 if (netif_msg_rx_err(db))
595 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
598 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
601 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
602 if (netif_msg_rx_err(db))
603 dev_dbg(db->dev, "crc error\n");
604 dev->stats.rx_crc_errors++;
607 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
608 if (netif_msg_rx_err(db))
609 dev_dbg(db->dev, "length error\n");
610 dev->stats.rx_length_errors++;
614 /* Move data from EMAC */
616 skb = netdev_alloc_skb(dev, rxlen + 4);
620 rdptr = skb_put(skb, rxlen - 4);
622 /* Read received packet from RX SRAM */
623 if (netif_msg_rx_status(db))
624 dev_dbg(db->dev, "RxLen %x\n", rxlen);
626 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
628 dev->stats.rx_bytes += rxlen;
630 /* Pass to upper layer */
631 skb->protocol = eth_type_trans(skb, dev);
633 dev->stats.rx_packets++;
638 static irqreturn_t emac_interrupt(int irq, void *dev_id)
640 struct net_device *dev = dev_id;
641 struct emac_board_info *db = netdev_priv(dev);
643 unsigned int reg_val;
645 /* A real interrupt coming */
647 spin_lock(&db->lock);
649 /* Disable all interrupts */
650 writel(0, db->membase + EMAC_INT_CTL_REG);
652 /* Got EMAC interrupt status */
654 int_status = readl(db->membase + EMAC_INT_STA_REG);
655 /* Clear ISR status */
656 writel(int_status, db->membase + EMAC_INT_STA_REG);
658 if (netif_msg_intr(db))
659 dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
661 /* Received the coming packet */
662 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
664 db->emacrx_completed_flag = 0;
668 /* Transmit Interrupt check */
669 if (int_status & (0x01 | 0x02))
670 emac_tx_done(dev, db, int_status);
672 if (int_status & (0x04 | 0x08))
673 netdev_info(dev, " ab : %x\n", int_status);
675 /* Re-enable interrupt mask */
676 if (db->emacrx_completed_flag == 1) {
677 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
678 reg_val |= (0xf << 0) | (0x01 << 8);
679 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
681 spin_unlock(&db->lock);
686 #ifdef CONFIG_NET_POLL_CONTROLLER
690 static void emac_poll_controller(struct net_device *dev)
692 disable_irq(dev->irq);
693 emac_interrupt(dev->irq, dev);
694 enable_irq(dev->irq);
698 /* Open the interface.
699 * The interface is opened whenever "ifconfig" actives it.
701 static int emac_open(struct net_device *dev)
703 struct emac_board_info *db = netdev_priv(dev);
706 if (netif_msg_ifup(db))
707 dev_dbg(db->dev, "enabling %s\n", dev->name);
709 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
712 /* Initialize EMAC board */
714 emac_init_device(dev);
716 ret = emac_mdio_probe(dev);
718 free_irq(dev->irq, dev);
719 netdev_err(dev, "cannot probe MDIO bus\n");
723 phy_start(dev->phydev);
724 netif_start_queue(dev);
729 static void emac_shutdown(struct net_device *dev)
731 unsigned int reg_val;
732 struct emac_board_info *db = netdev_priv(dev);
734 /* Disable all interrupt */
735 writel(0, db->membase + EMAC_INT_CTL_REG);
737 /* clear interrupt status */
738 reg_val = readl(db->membase + EMAC_INT_STA_REG);
739 writel(reg_val, db->membase + EMAC_INT_STA_REG);
742 reg_val = readl(db->membase + EMAC_CTL_REG);
743 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
744 writel(reg_val, db->membase + EMAC_CTL_REG);
747 /* Stop the interface.
748 * The interface is stopped when it is brought.
750 static int emac_stop(struct net_device *ndev)
752 struct emac_board_info *db = netdev_priv(ndev);
754 if (netif_msg_ifdown(db))
755 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
757 netif_stop_queue(ndev);
758 netif_carrier_off(ndev);
760 phy_stop(ndev->phydev);
762 emac_mdio_remove(ndev);
766 free_irq(ndev->irq, ndev);
771 static const struct net_device_ops emac_netdev_ops = {
772 .ndo_open = emac_open,
773 .ndo_stop = emac_stop,
774 .ndo_start_xmit = emac_start_xmit,
775 .ndo_tx_timeout = emac_timeout,
776 .ndo_set_rx_mode = emac_set_rx_mode,
777 .ndo_do_ioctl = phy_do_ioctl_running,
778 .ndo_validate_addr = eth_validate_addr,
779 .ndo_set_mac_address = emac_set_mac_address,
780 #ifdef CONFIG_NET_POLL_CONTROLLER
781 .ndo_poll_controller = emac_poll_controller,
785 /* Search EMAC board, allocate space and register it
787 static int emac_probe(struct platform_device *pdev)
789 struct device_node *np = pdev->dev.of_node;
790 struct emac_board_info *db;
791 struct net_device *ndev;
793 const char *mac_addr;
795 ndev = alloc_etherdev(sizeof(struct emac_board_info));
797 dev_err(&pdev->dev, "could not allocate device.\n");
801 SET_NETDEV_DEV(ndev, &pdev->dev);
803 db = netdev_priv(ndev);
805 db->dev = &pdev->dev;
808 db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE);
810 spin_lock_init(&db->lock);
812 db->membase = of_iomap(np, 0);
814 dev_err(&pdev->dev, "failed to remap registers\n");
819 /* fill in parameters for net-dev structure */
820 ndev->base_addr = (unsigned long)db->membase;
821 ndev->irq = irq_of_parse_and_map(np, 0);
822 if (ndev->irq == -ENXIO) {
823 netdev_err(ndev, "No irq resource\n");
828 db->clk = devm_clk_get(&pdev->dev, NULL);
829 if (IS_ERR(db->clk)) {
830 ret = PTR_ERR(db->clk);
831 goto out_dispose_mapping;
834 ret = clk_prepare_enable(db->clk);
836 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret);
837 goto out_dispose_mapping;
840 ret = sunxi_sram_claim(&pdev->dev);
842 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
843 goto out_clk_disable_unprepare;
846 db->phy_node = of_parse_phandle(np, "phy-handle", 0);
848 db->phy_node = of_parse_phandle(np, "phy", 0);
850 dev_err(&pdev->dev, "no associated PHY\n");
852 goto out_release_sram;
855 /* Read MAC-address from DT */
856 mac_addr = of_get_mac_address(np);
857 if (!IS_ERR(mac_addr))
858 ether_addr_copy(ndev->dev_addr, mac_addr);
860 /* Check if the MAC address is valid, if not get a random one */
861 if (!is_valid_ether_addr(ndev->dev_addr)) {
862 eth_hw_addr_random(ndev);
863 dev_warn(&pdev->dev, "using random MAC address %pM\n",
867 db->emacrx_completed_flag = 1;
871 ndev->netdev_ops = &emac_netdev_ops;
872 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
873 ndev->ethtool_ops = &emac_ethtool_ops;
875 platform_set_drvdata(pdev, ndev);
877 /* Carrier starts down, phylib will bring it up */
878 netif_carrier_off(ndev);
880 ret = register_netdev(ndev);
882 dev_err(&pdev->dev, "Registering netdev failed!\n");
884 goto out_release_sram;
887 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
888 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
893 sunxi_sram_release(&pdev->dev);
894 out_clk_disable_unprepare:
895 clk_disable_unprepare(db->clk);
897 irq_dispose_mapping(ndev->irq);
899 iounmap(db->membase);
901 dev_err(db->dev, "not found (%d).\n", ret);
908 static int emac_remove(struct platform_device *pdev)
910 struct net_device *ndev = platform_get_drvdata(pdev);
911 struct emac_board_info *db = netdev_priv(ndev);
913 unregister_netdev(ndev);
914 sunxi_sram_release(&pdev->dev);
915 clk_disable_unprepare(db->clk);
916 irq_dispose_mapping(ndev->irq);
917 iounmap(db->membase);
920 dev_dbg(&pdev->dev, "released and freed device\n");
924 static int emac_suspend(struct platform_device *dev, pm_message_t state)
926 struct net_device *ndev = platform_get_drvdata(dev);
928 netif_carrier_off(ndev);
929 netif_device_detach(ndev);
935 static int emac_resume(struct platform_device *dev)
937 struct net_device *ndev = platform_get_drvdata(dev);
938 struct emac_board_info *db = netdev_priv(ndev);
941 emac_init_device(ndev);
942 netif_device_attach(ndev);
947 static const struct of_device_id emac_of_match[] = {
948 {.compatible = "allwinner,sun4i-a10-emac",},
951 {.compatible = "allwinner,sun4i-emac",},
955 MODULE_DEVICE_TABLE(of, emac_of_match);
957 static struct platform_driver emac_driver = {
959 .name = "sun4i-emac",
960 .of_match_table = emac_of_match,
963 .remove = emac_remove,
964 .suspend = emac_suspend,
965 .resume = emac_resume,
968 module_platform_driver(emac_driver);
970 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
971 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
972 MODULE_DESCRIPTION("Allwinner A10 emac network driver");
973 MODULE_LICENSE("GPL");