1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/crc32.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/if_vlan.h>
46 #include <linux/firmware.h>
47 #include <asm/processor.h> /* Processor type for cache alignment. */
48 #include <linux/uaccess.h>
52 * The current frame processor firmware fails to checksum a fragment
53 * of length 1. If and when this is fixed, the #define below can be removed.
55 #define HAS_BROKEN_FIRMWARE
58 * If using the broken firmware, data must be padded to the next 32-bit boundary.
60 #ifdef HAS_BROKEN_FIRMWARE
61 #define PADDING_MASK 3
65 * Define this if using the driver with the zero-copy patch
69 #if IS_ENABLED(CONFIG_VLAN_8021Q)
73 /* The user-configurable values.
74 These may be modified when a driver module is loaded.*/
76 /* Used for tuning interrupt latency vs. overhead. */
77 static int intr_latency;
78 static int small_frames;
80 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
81 static int max_interrupt_work = 20;
83 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
84 The Starfire has a 512 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 512;
86 /* Whether to do TCP/UDP checksums in hardware */
87 static int enable_hw_cksum = 1;
89 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
91 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
92 * Setting to > 1518 effectively disables this feature.
95 * The ia64 doesn't allow for unaligned loads even of integers being
96 * misaligned on a 2 byte boundary. Thus always force copying of
97 * packets as the starfire doesn't allow for misaligned DMAs ;-(
100 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
101 * at least, having unaligned frames leads to a rather serious performance
104 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
105 static int rx_copybreak = PKT_BUF_SZ;
107 static int rx_copybreak /* = 0 */;
110 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
112 #define DMA_BURST_SIZE 64
114 #define DMA_BURST_SIZE 128
117 /* Operational parameters that are set at compile time. */
119 /* The "native" ring sizes are either 256 or 2048.
120 However in some modes a descriptor may be marked to wrap the ring earlier.
122 #define RX_RING_SIZE 256
123 #define TX_RING_SIZE 32
124 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
125 #define DONE_Q_SIZE 1024
126 /* All queues must be aligned on a 256-byte boundary */
127 #define QUEUE_ALIGN 256
129 #if RX_RING_SIZE > 256
130 #define RX_Q_ENTRIES Rx2048QEntries
132 #define RX_Q_ENTRIES Rx256QEntries
135 /* Operational parameters that usually are not changed. */
136 /* Time in jiffies before concluding the transmitter is hung. */
137 #define TX_TIMEOUT (2 * HZ)
139 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
140 /* 64-bit dma_addr_t */
141 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
142 #define netdrv_addr_t __le64
143 #define cpu_to_dma(x) cpu_to_le64(x)
144 #define dma_to_cpu(x) le64_to_cpu(x)
145 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
146 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
147 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
148 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
149 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
150 #else /* 32-bit dma_addr_t */
151 #define netdrv_addr_t __le32
152 #define cpu_to_dma(x) cpu_to_le32(x)
153 #define dma_to_cpu(x) le32_to_cpu(x)
154 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
155 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
156 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
157 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
158 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
161 #define skb_first_frag_len(skb) skb_headlen(skb)
162 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
165 #define FIRMWARE_RX "/*(DEBLOBBED)*/"
166 #define FIRMWARE_TX "/*(DEBLOBBED)*/"
168 /* These identify the driver base version and may not be removed. */
169 static const char version[] =
170 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
171 " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
173 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
174 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
175 MODULE_LICENSE("GPL");
176 MODULE_VERSION(DRV_VERSION);
179 module_param(max_interrupt_work, int, 0);
180 module_param(mtu, int, 0);
181 module_param(debug, int, 0);
182 module_param(rx_copybreak, int, 0);
183 module_param(intr_latency, int, 0);
184 module_param(small_frames, int, 0);
185 module_param(enable_hw_cksum, int, 0);
186 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
187 MODULE_PARM_DESC(mtu, "MTU (all boards)");
188 MODULE_PARM_DESC(debug, "Debug level (0-6)");
189 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
190 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
191 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
192 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
197 I. Board Compatibility
199 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
201 II. Board-specific settings
203 III. Driver operation
207 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
208 ring sizes are set fixed by the hardware, but may optionally be wrapped
209 earlier by the END bit in the descriptor.
210 This driver uses that hardware queue size for the Rx ring, where a large
211 number of entries has no ill effect beyond increases the potential backlog.
212 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
213 disables the queue layer priority ordering and we have no mechanism to
214 utilize the hardware two-level priority queue. When modifying the
215 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
218 IIIb/c. Transmit/Receive Structure
220 See the Adaptec manual for the many possible structures, and options for
221 each structure. There are far too many to document all of them here.
223 For transmit this driver uses type 0/1 transmit descriptors (depending
224 on the 32/64 bitness of the architecture), and relies on automatic
225 minimum-length padding. It does not use the completion queue
226 consumer index, but instead checks for non-zero status entries.
228 For receive this driver uses type 2/3 receive descriptors. The driver
229 allocates full frame size skbuffs for the Rx ring buffers, so all frames
230 should fit in a single descriptor. The driver does not use the completion
231 queue consumer index, but instead checks for non-zero status entries.
233 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
234 is allocated and the frame is copied to the new skbuff. When the incoming
235 frame is larger, the skbuff is passed directly up the protocol stack.
236 Buffers consumed this way are replaced by newly allocated skbuffs in a later
239 A notable aspect of operation is that unaligned buffers are not permitted by
240 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
241 isn't longword aligned, which may cause problems on some machine
242 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
243 the frame into a new skbuff unconditionally. Copied frames are put into the
244 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
246 IIId. Synchronization
248 The driver runs as two independent, single-threaded flows of control. One
249 is the send-packet routine, which enforces single-threaded use by the
250 dev->tbusy flag. The other thread is the interrupt handler, which is single
251 threaded by the hardware and interrupt handling software.
253 The send packet thread has partial control over the Tx ring and the netif_queue
254 status. If the number of free Tx slots in the ring falls below a certain number
255 (currently hardcoded to 4), it signals the upper layer to stop the queue.
257 The interrupt handler has exclusive control over the Rx ring and records stats
258 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
259 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
260 number of free Tx slow is above the threshold, it signals the upper layer to
267 The Adaptec Starfire manuals, available only from Adaptec.
268 http://www.scyld.com/expert/100mbps.html
269 http://www.scyld.com/expert/NWay.html
273 - StopOnPerr is broken, don't enable
274 - Hardware ethernet padding exposes random data, perform software padding
275 instead (unverified -- works correctly for all the hardware I have)
281 enum chip_capability_flags {CanHaveMII=1, };
287 static const struct pci_device_id starfire_pci_tbl[] = {
288 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
291 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
293 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
294 static const struct chip_info {
298 { "Adaptec Starfire 6915", CanHaveMII },
302 /* Offsets to the device registers.
303 Unlike software-only systems, device drivers interact with complex hardware.
304 It's not useful to define symbolic names for every register bit in the
305 device. The name can only partially document the semantics and make
306 the driver longer and more difficult to read.
307 In general, only the important configuration values or bits changed
308 multiple times should be defined symbolically.
310 enum register_offsets {
311 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
312 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
313 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
314 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
315 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
316 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
317 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
319 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
320 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
321 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
322 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
323 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
324 TxMode=0x55000, VlanType=0x55064,
325 PerfFilterTable=0x56000, HashTable=0x56100,
326 TxGfpMem=0x58000, RxGfpMem=0x5a000,
330 * Bits in the interrupt status/mask registers.
331 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
332 * enables all the interrupt sources that are or'ed into those status bits.
334 enum intr_status_bits {
335 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
336 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
337 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
338 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
339 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
340 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
341 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
342 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
343 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
344 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
345 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
346 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
347 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
348 IntrTxGfp=0x02, IntrPCIPad=0x01,
350 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
351 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
352 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
355 /* Bits in the RxFilterMode register. */
357 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
358 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
359 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
363 /* Bits in the TxMode register */
365 MiiSoftReset=0x8000, MIILoopback=0x4000,
366 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
367 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
370 /* Bits in the TxDescCtrl register. */
372 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
373 TxDescSpace128=0x30, TxDescSpace256=0x40,
374 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
375 TxDescType3=0x03, TxDescType4=0x04,
376 TxNoDMACompletion=0x08,
377 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
378 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
379 TxDMABurstSizeShift=8,
382 /* Bits in the RxDescQCtrl register. */
384 RxBufferLenShift=16, RxMinDescrThreshShift=0,
385 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
386 Rx2048QEntries=0x4000, Rx256QEntries=0,
387 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
388 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
389 RxDescSpace4=0x000, RxDescSpace8=0x100,
390 RxDescSpace16=0x200, RxDescSpace32=0x300,
391 RxDescSpace64=0x400, RxDescSpace128=0x500,
395 /* Bits in the RxDMACtrl register. */
396 enum rx_dmactrl_bits {
397 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
398 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
399 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
400 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
401 RxChecksumRejectTCPOnly=0x01000000,
402 RxCompletionQ2Enable=0x800000,
403 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
404 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
405 RxDMAQ2NonIP=0x400000,
406 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
407 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
411 /* Bits in the RxCompletionAddr register */
413 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
414 RxComplProducerWrEn=0x40,
415 RxComplType0=0x00, RxComplType1=0x10,
416 RxComplType2=0x20, RxComplType3=0x30,
417 RxComplThreshShift=0,
420 /* Bits in the TxCompletionAddr register */
422 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
423 TxComplProducerWrEn=0x40,
424 TxComplIntrStatus=0x20,
425 CommonQueueMode=0x10,
426 TxComplThreshShift=0,
429 /* Bits in the GenCtrl register */
431 RxEnable=0x05, TxEnable=0x0a,
432 RxGFPEnable=0x10, TxGFPEnable=0x20,
435 /* Bits in the IntrTimerCtrl register */
436 enum intr_ctrl_bits {
437 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
438 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
439 IntrLatencyMask=0x1f,
442 /* The Rx and Tx buffer descriptors. */
443 struct starfire_rx_desc {
444 netdrv_addr_t rxaddr;
447 RxDescValid=1, RxDescEndRing=2,
450 /* Completion queue entry. */
451 struct short_rx_done_desc {
452 __le32 status; /* Low 16 bits is length. */
454 struct basic_rx_done_desc {
455 __le32 status; /* Low 16 bits is length. */
459 struct csum_rx_done_desc {
460 __le32 status; /* Low 16 bits is length. */
461 __le16 csum; /* Partial checksum */
464 struct full_rx_done_desc {
465 __le32 status; /* Low 16 bits is length. */
469 __le16 csum; /* partial checksum */
472 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
474 typedef struct full_rx_done_desc rx_done_desc;
475 #define RxComplType RxComplType3
476 #else /* not VLAN_SUPPORT */
477 typedef struct csum_rx_done_desc rx_done_desc;
478 #define RxComplType RxComplType2
479 #endif /* not VLAN_SUPPORT */
482 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
485 /* Type 1 Tx descriptor. */
486 struct starfire_tx_desc_1 {
487 __le32 status; /* Upper bits are status, lower 16 length. */
491 /* Type 2 Tx descriptor. */
492 struct starfire_tx_desc_2 {
493 __le32 status; /* Upper bits are status, lower 16 length. */
499 typedef struct starfire_tx_desc_2 starfire_tx_desc;
500 #define TX_DESC_TYPE TxDescType2
501 #else /* not ADDR_64BITS */
502 typedef struct starfire_tx_desc_1 starfire_tx_desc;
503 #define TX_DESC_TYPE TxDescType1
504 #endif /* not ADDR_64BITS */
505 #define TX_DESC_SPACING TxDescSpaceUnlim
509 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
510 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
512 struct tx_done_desc {
513 __le32 status; /* timestamp, index. */
515 __le32 intrstatus; /* interrupt status */
519 struct rx_ring_info {
523 struct tx_ring_info {
526 unsigned int used_slots;
530 struct netdev_private {
531 /* Descriptor rings first for alignment. */
532 struct starfire_rx_desc *rx_ring;
533 starfire_tx_desc *tx_ring;
534 dma_addr_t rx_ring_dma;
535 dma_addr_t tx_ring_dma;
536 /* The addresses of rx/tx-in-place skbuffs. */
537 struct rx_ring_info rx_info[RX_RING_SIZE];
538 struct tx_ring_info tx_info[TX_RING_SIZE];
539 /* Pointers to completion queues (full pages). */
540 rx_done_desc *rx_done_q;
541 dma_addr_t rx_done_q_dma;
542 unsigned int rx_done;
543 struct tx_done_desc *tx_done_q;
544 dma_addr_t tx_done_q_dma;
545 unsigned int tx_done;
546 struct napi_struct napi;
547 struct net_device *dev;
548 struct pci_dev *pci_dev;
550 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
553 dma_addr_t queue_mem_dma;
554 size_t queue_mem_size;
556 /* Frequently used values: keep some adjacent for cache effect. */
558 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
559 unsigned int cur_tx, dirty_tx, reap_tx;
560 unsigned int rx_buf_sz; /* Based on MTU+slack. */
561 /* These values keep track of the transceiver/media in use. */
562 int speed100; /* Set if speed == 100MBit. */
566 /* MII transceiver section. */
567 struct mii_if_info mii_if; /* MII lib hooks/info */
568 int phy_cnt; /* MII device addresses. */
569 unsigned char phys[PHY_CNT]; /* MII device addresses. */
574 static int mdio_read(struct net_device *dev, int phy_id, int location);
575 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
576 static int netdev_open(struct net_device *dev);
577 static void check_duplex(struct net_device *dev);
578 static void tx_timeout(struct net_device *dev);
579 static void init_ring(struct net_device *dev);
580 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
581 static irqreturn_t intr_handler(int irq, void *dev_instance);
582 static void netdev_error(struct net_device *dev, int intr_status);
583 static int __netdev_rx(struct net_device *dev, int *quota);
584 static int netdev_poll(struct napi_struct *napi, int budget);
585 static void refill_rx_ring(struct net_device *dev);
586 static void netdev_error(struct net_device *dev, int intr_status);
587 static void set_rx_mode(struct net_device *dev);
588 static struct net_device_stats *get_stats(struct net_device *dev);
589 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
590 static int netdev_close(struct net_device *dev);
591 static void netdev_media_change(struct net_device *dev);
592 static const struct ethtool_ops ethtool_ops;
596 static int netdev_vlan_rx_add_vid(struct net_device *dev,
597 __be16 proto, u16 vid)
599 struct netdev_private *np = netdev_priv(dev);
601 spin_lock(&np->lock);
603 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
604 set_bit(vid, np->active_vlans);
606 spin_unlock(&np->lock);
611 static int netdev_vlan_rx_kill_vid(struct net_device *dev,
612 __be16 proto, u16 vid)
614 struct netdev_private *np = netdev_priv(dev);
616 spin_lock(&np->lock);
618 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
619 clear_bit(vid, np->active_vlans);
621 spin_unlock(&np->lock);
625 #endif /* VLAN_SUPPORT */
628 static const struct net_device_ops netdev_ops = {
629 .ndo_open = netdev_open,
630 .ndo_stop = netdev_close,
631 .ndo_start_xmit = start_tx,
632 .ndo_tx_timeout = tx_timeout,
633 .ndo_get_stats = get_stats,
634 .ndo_set_rx_mode = set_rx_mode,
635 .ndo_do_ioctl = netdev_ioctl,
636 .ndo_set_mac_address = eth_mac_addr,
637 .ndo_validate_addr = eth_validate_addr,
639 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
640 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
644 static int starfire_init_one(struct pci_dev *pdev,
645 const struct pci_device_id *ent)
647 struct device *d = &pdev->dev;
648 struct netdev_private *np;
649 int i, irq, chip_idx = ent->driver_data;
650 struct net_device *dev;
653 int drv_flags, io_size;
656 /* when built into the kernel, we only print version if device is found */
658 static int printed_version;
659 if (!printed_version++)
663 if (pci_enable_device (pdev))
666 ioaddr = pci_resource_start(pdev, 0);
667 io_size = pci_resource_len(pdev, 0);
668 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
669 dev_err(d, "no PCI MEM resources, aborting\n");
673 dev = alloc_etherdev(sizeof(*np));
677 SET_NETDEV_DEV(dev, &pdev->dev);
681 if (pci_request_regions (pdev, DRV_NAME)) {
682 dev_err(d, "cannot reserve PCI resources, aborting\n");
683 goto err_out_free_netdev;
686 base = ioremap(ioaddr, io_size);
688 dev_err(d, "cannot remap %#x @ %#lx, aborting\n",
690 goto err_out_free_res;
693 pci_set_master(pdev);
695 /* enable MWI -- it vastly improves Rx performance on sparc64 */
696 pci_try_set_mwi(pdev);
699 /* Starfire can do TCP/UDP checksumming */
701 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
702 #endif /* ZEROCOPY */
705 dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER;
706 #endif /* VLAN_RX_KILL_VID */
708 dev->features |= NETIF_F_HIGHDMA;
709 #endif /* ADDR_64BITS */
711 /* Serial EEPROM reads are hidden by the hardware. */
712 for (i = 0; i < 6; i++)
713 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
715 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
717 for (i = 0; i < 0x20; i++)
719 (unsigned int)readb(base + EEPROMCtrl + i),
720 i % 16 != 15 ? " " : "\n");
723 /* Issue soft reset */
724 writel(MiiSoftReset, base + TxMode);
726 writel(0, base + TxMode);
728 /* Reset the chip to erase previous misconfiguration. */
729 writel(1, base + PCIDeviceConfig);
731 while (--boguscnt > 0) {
733 if ((readl(base + PCIDeviceConfig) & 1) == 0)
737 printk("%s: chipset reset never completed!\n", dev->name);
738 /* wait a little longer */
741 np = netdev_priv(dev);
744 spin_lock_init(&np->lock);
745 pci_set_drvdata(pdev, dev);
749 np->mii_if.dev = dev;
750 np->mii_if.mdio_read = mdio_read;
751 np->mii_if.mdio_write = mdio_write;
752 np->mii_if.phy_id_mask = 0x1f;
753 np->mii_if.reg_num_mask = 0x1f;
755 drv_flags = netdrv_tbl[chip_idx].drv_flags;
759 /* timer resolution is 128 * 0.8us */
760 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
761 Timer10X | EnableIntrMasking;
763 if (small_frames > 0) {
764 np->intr_timer_ctrl |= SmallFrameBypass;
765 switch (small_frames) {
767 np->intr_timer_ctrl |= SmallFrame64;
770 np->intr_timer_ctrl |= SmallFrame128;
773 np->intr_timer_ctrl |= SmallFrame256;
776 np->intr_timer_ctrl |= SmallFrame512;
777 if (small_frames > 512)
778 printk("Adjusting small_frames down to 512\n");
783 dev->netdev_ops = &netdev_ops;
784 dev->watchdog_timeo = TX_TIMEOUT;
785 dev->ethtool_ops = ðtool_ops;
787 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
792 if (register_netdev(dev))
793 goto err_out_cleardev;
795 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
796 dev->name, netdrv_tbl[chip_idx].name, base,
799 if (drv_flags & CanHaveMII) {
800 int phy, phy_idx = 0;
802 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
803 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
806 while (--boguscnt > 0)
807 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
810 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
813 mii_status = mdio_read(dev, phy, MII_BMSR);
814 if (mii_status != 0) {
815 np->phys[phy_idx++] = phy;
816 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
817 printk(KERN_INFO "%s: MII PHY found at address %d, status "
818 "%#4.4x advertising %#4.4x.\n",
819 dev->name, phy, mii_status, np->mii_if.advertising);
820 /* there can be only one PHY on-board */
824 np->phy_cnt = phy_idx;
826 np->mii_if.phy_id = np->phys[0];
828 memset(&np->mii_if, 0, sizeof(np->mii_if));
831 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
832 dev->name, enable_hw_cksum ? "enabled" : "disabled");
838 pci_release_regions (pdev);
845 /* Read the MII Management Data I/O (MDIO) interfaces. */
846 static int mdio_read(struct net_device *dev, int phy_id, int location)
848 struct netdev_private *np = netdev_priv(dev);
849 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
850 int result, boguscnt=1000;
851 /* ??? Should we add a busy-wait here? */
853 result = readl(mdio_addr);
854 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
857 if ((result & 0xffff) == 0xffff)
859 return result & 0xffff;
863 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
865 struct netdev_private *np = netdev_priv(dev);
866 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
867 writel(value, mdio_addr);
868 /* The busy-wait will occur before a read. */
872 static int netdev_open(struct net_device *dev)
874 const struct firmware *fw_rx, *fw_tx;
875 const __be32 *fw_rx_data, *fw_tx_data;
876 struct netdev_private *np = netdev_priv(dev);
877 void __iomem *ioaddr = np->base;
878 const int irq = np->pci_dev->irq;
880 size_t tx_size, rx_size;
881 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
883 /* Do we ever need to reset the chip??? */
885 retval = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
889 /* Disable the Rx and Tx, and reset the chip. */
890 writel(0, ioaddr + GenCtrl);
891 writel(1, ioaddr + PCIDeviceConfig);
893 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
896 /* Allocate the various queues. */
897 if (!np->queue_mem) {
898 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
899 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
900 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
901 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
902 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
903 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
904 if (np->queue_mem == NULL) {
909 np->tx_done_q = np->queue_mem;
910 np->tx_done_q_dma = np->queue_mem_dma;
911 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
912 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
913 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
914 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
915 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
916 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
919 /* Start with no carrier, it gets adjusted later */
920 netif_carrier_off(dev);
922 /* Set the size of the Rx buffers. */
923 writel((np->rx_buf_sz << RxBufferLenShift) |
924 (0 << RxMinDescrThreshShift) |
925 RxPrefetchMode | RxVariableQ |
927 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
929 ioaddr + RxDescQCtrl);
931 /* Set up the Rx DMA controller. */
932 writel(RxChecksumIgnore |
933 (0 << RxEarlyIntThreshShift) |
934 (6 << RxHighPrioThreshShift) |
935 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
938 /* Set Tx descriptor */
939 writel((2 << TxHiPriFIFOThreshShift) |
940 (0 << TxPadLenShift) |
941 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
942 TX_DESC_Q_ADDR_SIZE |
943 TX_DESC_SPACING | TX_DESC_TYPE,
944 ioaddr + TxDescCtrl);
946 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
947 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
948 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
949 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
950 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
952 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
953 writel(np->rx_done_q_dma |
955 (0 << RxComplThreshShift),
956 ioaddr + RxCompletionAddr);
959 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
961 /* Fill both the Tx SA register and the Rx perfect filter. */
962 for (i = 0; i < 6; i++)
963 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
964 /* The first entry is special because it bypasses the VLAN filter.
966 writew(0, ioaddr + PerfFilterTable);
967 writew(0, ioaddr + PerfFilterTable + 4);
968 writew(0, ioaddr + PerfFilterTable + 8);
969 for (i = 1; i < 16; i++) {
970 __be16 *eaddrs = (__be16 *)dev->dev_addr;
971 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
972 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
973 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
974 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
977 /* Initialize other registers. */
978 /* Configure the PCI bus bursts and FIFO thresholds. */
979 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
980 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
982 writel(np->tx_mode, ioaddr + TxMode);
983 np->tx_threshold = 4;
984 writel(np->tx_threshold, ioaddr + TxThreshold);
986 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
988 napi_enable(&np->napi);
990 netif_start_queue(dev);
993 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
996 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
999 /* Enable GPIO interrupts on link change */
1000 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1002 /* Set the interrupt mask */
1003 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1004 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1005 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1006 ioaddr + IntrEnable);
1007 /* Enable PCI interrupts. */
1008 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1009 ioaddr + PCIDeviceConfig);
1012 /* Set VLAN type to 802.1q */
1013 writel(ETH_P_8021Q, ioaddr + VlanType);
1014 #endif /* VLAN_SUPPORT */
1016 retval = reject_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1018 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1022 if (fw_rx->size % 4) {
1023 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1024 fw_rx->size, FIRMWARE_RX);
1028 retval = reject_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1030 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1034 if (fw_tx->size % 4) {
1035 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1036 fw_tx->size, FIRMWARE_TX);
1040 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1041 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1042 rx_size = fw_rx->size / 4;
1043 tx_size = fw_tx->size / 4;
1045 /* Load Rx/Tx firmware into the frame processors */
1046 for (i = 0; i < rx_size; i++)
1047 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1048 for (i = 0; i < tx_size; i++)
1049 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1050 if (enable_hw_cksum)
1051 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1052 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1054 /* Enable the Rx and Tx units only. */
1055 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1058 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1062 release_firmware(fw_tx);
1064 release_firmware(fw_rx);
1072 static void check_duplex(struct net_device *dev)
1074 struct netdev_private *np = netdev_priv(dev);
1076 int silly_count = 1000;
1078 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1079 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1081 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1084 printk("%s: MII reset failed!\n", dev->name);
1088 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1090 if (!np->mii_if.force_media) {
1091 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1093 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1095 reg0 |= BMCR_SPEED100;
1096 if (np->mii_if.full_duplex)
1097 reg0 |= BMCR_FULLDPLX;
1098 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1100 np->speed100 ? "100" : "10",
1101 np->mii_if.full_duplex ? "full" : "half");
1103 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1107 static void tx_timeout(struct net_device *dev)
1109 struct netdev_private *np = netdev_priv(dev);
1110 void __iomem *ioaddr = np->base;
1113 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1114 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1116 /* Perhaps we should reinitialize the hardware here. */
1119 * Stop and restart the interface.
1120 * Cheat and increase the debug level temporarily.
1128 /* Trigger an immediate transmit demand. */
1130 netif_trans_update(dev); /* prevent tx timeout */
1131 dev->stats.tx_errors++;
1132 netif_wake_queue(dev);
1136 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1137 static void init_ring(struct net_device *dev)
1139 struct netdev_private *np = netdev_priv(dev);
1142 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1143 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1145 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1147 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1148 for (i = 0; i < RX_RING_SIZE; i++) {
1149 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1150 np->rx_info[i].skb = skb;
1153 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1154 if (pci_dma_mapping_error(np->pci_dev,
1155 np->rx_info[i].mapping)) {
1157 np->rx_info[i].skb = NULL;
1160 /* Grrr, we cannot offset to correctly align the IP header. */
1161 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1163 writew(i - 1, np->base + RxDescQIdx);
1164 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1166 /* Clear the remainder of the Rx buffer ring. */
1167 for ( ; i < RX_RING_SIZE; i++) {
1168 np->rx_ring[i].rxaddr = 0;
1169 np->rx_info[i].skb = NULL;
1170 np->rx_info[i].mapping = 0;
1172 /* Mark the last entry as wrapping the ring. */
1173 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1175 /* Clear the completion rings. */
1176 for (i = 0; i < DONE_Q_SIZE; i++) {
1177 np->rx_done_q[i].status = 0;
1178 np->tx_done_q[i].status = 0;
1181 for (i = 0; i < TX_RING_SIZE; i++)
1182 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1186 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1188 struct netdev_private *np = netdev_priv(dev);
1190 unsigned int prev_tx;
1195 * be cautious here, wrapping the queue has weird semantics
1196 * and we may not have enough slots even when it seems we do.
1198 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1199 netif_stop_queue(dev);
1200 return NETDEV_TX_BUSY;
1203 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1204 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1205 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1206 return NETDEV_TX_OK;
1208 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1210 prev_tx = np->cur_tx;
1211 entry = np->cur_tx % TX_RING_SIZE;
1212 for (i = 0; i < skb_num_frags(skb); i++) {
1217 np->tx_info[entry].skb = skb;
1219 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1220 status |= TxRingWrap;
1224 status |= TxDescIntr;
1227 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1229 dev->stats.tx_compressed++;
1231 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1233 np->tx_info[entry].mapping =
1234 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1236 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1237 status |= skb_frag_size(this_frag);
1238 np->tx_info[entry].mapping =
1239 pci_map_single(np->pci_dev,
1240 skb_frag_address(this_frag),
1241 skb_frag_size(this_frag),
1244 if (pci_dma_mapping_error(np->pci_dev,
1245 np->tx_info[entry].mapping)) {
1246 dev->stats.tx_dropped++;
1250 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1251 np->tx_ring[entry].status = cpu_to_le32(status);
1253 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1254 dev->name, np->cur_tx, np->dirty_tx,
1257 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1258 np->cur_tx += np->tx_info[entry].used_slots;
1261 np->tx_info[entry].used_slots = 1;
1262 np->cur_tx += np->tx_info[entry].used_slots;
1265 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1266 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1270 /* Non-x86: explicitly flush descriptor cache lines here. */
1271 /* Ensure all descriptors are written back before the transmit is
1275 /* Update the producer index. */
1276 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1278 /* 4 is arbitrary, but should be ok */
1279 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1280 netif_stop_queue(dev);
1282 return NETDEV_TX_OK;
1285 entry = prev_tx % TX_RING_SIZE;
1286 np->tx_info[entry].skb = NULL;
1288 pci_unmap_single(np->pci_dev,
1289 np->tx_info[entry].mapping,
1290 skb_first_frag_len(skb),
1292 np->tx_info[entry].mapping = 0;
1293 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1294 for (j = 1; j < i; j++) {
1295 pci_unmap_single(np->pci_dev,
1296 np->tx_info[entry].mapping,
1298 &skb_shinfo(skb)->frags[j-1]),
1303 dev_kfree_skb_any(skb);
1304 np->cur_tx = prev_tx;
1305 return NETDEV_TX_OK;
1308 /* The interrupt handler does all of the Rx thread work and cleans up
1309 after the Tx thread. */
1310 static irqreturn_t intr_handler(int irq, void *dev_instance)
1312 struct net_device *dev = dev_instance;
1313 struct netdev_private *np = netdev_priv(dev);
1314 void __iomem *ioaddr = np->base;
1315 int boguscnt = max_interrupt_work;
1321 u32 intr_status = readl(ioaddr + IntrClear);
1324 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1325 dev->name, intr_status);
1327 if (intr_status == 0 || intr_status == (u32) -1)
1332 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1335 if (likely(napi_schedule_prep(&np->napi))) {
1336 __napi_schedule(&np->napi);
1337 enable = readl(ioaddr + IntrEnable);
1338 enable &= ~(IntrRxDone | IntrRxEmpty);
1339 writel(enable, ioaddr + IntrEnable);
1340 /* flush PCI posting buffers */
1341 readl(ioaddr + IntrEnable);
1343 /* Paranoia check */
1344 enable = readl(ioaddr + IntrEnable);
1345 if (enable & (IntrRxDone | IntrRxEmpty)) {
1347 "%s: interrupt while in poll!\n",
1349 enable &= ~(IntrRxDone | IntrRxEmpty);
1350 writel(enable, ioaddr + IntrEnable);
1355 /* Scavenge the skbuff list based on the Tx-done queue.
1356 There are redundant checks here that may be cleaned up
1357 after the driver has proven to be reliable. */
1358 consumer = readl(ioaddr + TxConsumerIdx);
1360 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1361 dev->name, consumer);
1363 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1365 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1366 dev->name, np->dirty_tx, np->tx_done, tx_status);
1367 if ((tx_status & 0xe0000000) == 0xa0000000) {
1368 dev->stats.tx_packets++;
1369 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1370 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1371 struct sk_buff *skb = np->tx_info[entry].skb;
1372 np->tx_info[entry].skb = NULL;
1373 pci_unmap_single(np->pci_dev,
1374 np->tx_info[entry].mapping,
1375 skb_first_frag_len(skb),
1377 np->tx_info[entry].mapping = 0;
1378 np->dirty_tx += np->tx_info[entry].used_slots;
1379 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1382 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1383 pci_unmap_single(np->pci_dev,
1384 np->tx_info[entry].mapping,
1385 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1392 dev_kfree_skb_irq(skb);
1394 np->tx_done_q[np->tx_done].status = 0;
1395 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1397 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1399 if (netif_queue_stopped(dev) &&
1400 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1401 /* The ring is no longer full, wake the queue. */
1402 netif_wake_queue(dev);
1405 /* Stats overflow */
1406 if (intr_status & IntrStatsMax)
1409 /* Media change interrupt. */
1410 if (intr_status & IntrLinkChange)
1411 netdev_media_change(dev);
1413 /* Abnormal error summary/uncommon events handlers. */
1414 if (intr_status & IntrAbnormalSummary)
1415 netdev_error(dev, intr_status);
1417 if (--boguscnt < 0) {
1419 printk(KERN_WARNING "%s: Too much work at interrupt, "
1421 dev->name, intr_status);
1427 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1428 dev->name, (int) readl(ioaddr + IntrStatus));
1429 return IRQ_RETVAL(handled);
1434 * This routine is logically part of the interrupt/poll handler, but separated
1435 * for clarity and better register allocation.
1437 static int __netdev_rx(struct net_device *dev, int *quota)
1439 struct netdev_private *np = netdev_priv(dev);
1443 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1444 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1445 struct sk_buff *skb;
1448 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1451 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1452 if (!(desc_status & RxOK)) {
1453 /* There was an error. */
1455 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1456 dev->stats.rx_errors++;
1457 if (desc_status & RxFIFOErr)
1458 dev->stats.rx_fifo_errors++;
1462 if (*quota <= 0) { /* out of rx quota */
1468 pkt_len = desc_status; /* Implicitly Truncate */
1469 entry = (desc_status >> 16) & 0x7ff;
1472 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1473 /* Check if the packet is long enough to accept without copying
1474 to a minimally-sized skbuff. */
1475 if (pkt_len < rx_copybreak &&
1476 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1477 skb_reserve(skb, 2); /* 16 byte align the IP header */
1478 pci_dma_sync_single_for_cpu(np->pci_dev,
1479 np->rx_info[entry].mapping,
1480 pkt_len, PCI_DMA_FROMDEVICE);
1481 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1482 pci_dma_sync_single_for_device(np->pci_dev,
1483 np->rx_info[entry].mapping,
1484 pkt_len, PCI_DMA_FROMDEVICE);
1485 skb_put(skb, pkt_len);
1487 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1488 skb = np->rx_info[entry].skb;
1489 skb_put(skb, pkt_len);
1490 np->rx_info[entry].skb = NULL;
1491 np->rx_info[entry].mapping = 0;
1493 #ifndef final_version /* Remove after testing. */
1494 /* You will want this info for the initial debug. */
1496 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1497 skb->data, skb->data + 6,
1498 skb->data[12], skb->data[13]);
1502 skb->protocol = eth_type_trans(skb, dev);
1505 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1507 if (le16_to_cpu(desc->status2) & 0x0100) {
1508 skb->ip_summed = CHECKSUM_UNNECESSARY;
1509 dev->stats.rx_compressed++;
1512 * This feature doesn't seem to be working, at least
1513 * with the two firmware versions I have. If the GFP sees
1514 * an IP fragment, it either ignores it completely, or reports
1515 * "bad checksum" on it.
1517 * Maybe I missed something -- corrections are welcome.
1518 * Until then, the printk stays. :-) -Ion
1520 else if (le16_to_cpu(desc->status2) & 0x0040) {
1521 skb->ip_summed = CHECKSUM_COMPLETE;
1522 skb->csum = le16_to_cpu(desc->csum);
1523 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1526 if (le16_to_cpu(desc->status2) & 0x0200) {
1527 u16 vlid = le16_to_cpu(desc->vlanid);
1530 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1533 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlid);
1535 #endif /* VLAN_SUPPORT */
1536 netif_receive_skb(skb);
1537 dev->stats.rx_packets++;
1542 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1545 if (*quota == 0) { /* out of rx quota */
1549 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1552 refill_rx_ring(dev);
1554 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1555 retcode, np->rx_done, desc_status);
1559 static int netdev_poll(struct napi_struct *napi, int budget)
1561 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1562 struct net_device *dev = np->dev;
1564 void __iomem *ioaddr = np->base;
1568 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1570 if (__netdev_rx(dev, "a))
1573 intr_status = readl(ioaddr + IntrStatus);
1574 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1576 napi_complete(napi);
1577 intr_status = readl(ioaddr + IntrEnable);
1578 intr_status |= IntrRxDone | IntrRxEmpty;
1579 writel(intr_status, ioaddr + IntrEnable);
1583 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1586 /* Restart Rx engine if stopped. */
1587 return budget - quota;
1590 static void refill_rx_ring(struct net_device *dev)
1592 struct netdev_private *np = netdev_priv(dev);
1593 struct sk_buff *skb;
1596 /* Refill the Rx ring buffers. */
1597 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1598 entry = np->dirty_rx % RX_RING_SIZE;
1599 if (np->rx_info[entry].skb == NULL) {
1600 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1601 np->rx_info[entry].skb = skb;
1603 break; /* Better luck next round. */
1604 np->rx_info[entry].mapping =
1605 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1606 if (pci_dma_mapping_error(np->pci_dev,
1607 np->rx_info[entry].mapping)) {
1609 np->rx_info[entry].skb = NULL;
1612 np->rx_ring[entry].rxaddr =
1613 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1615 if (entry == RX_RING_SIZE - 1)
1616 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1619 writew(entry, np->base + RxDescQIdx);
1623 static void netdev_media_change(struct net_device *dev)
1625 struct netdev_private *np = netdev_priv(dev);
1626 void __iomem *ioaddr = np->base;
1627 u16 reg0, reg1, reg4, reg5;
1629 u32 new_intr_timer_ctrl;
1631 /* reset status first */
1632 mdio_read(dev, np->phys[0], MII_BMCR);
1633 mdio_read(dev, np->phys[0], MII_BMSR);
1635 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1636 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1638 if (reg1 & BMSR_LSTATUS) {
1640 if (reg0 & BMCR_ANENABLE) {
1641 /* autonegotiation is enabled */
1642 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1643 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1644 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1646 np->mii_if.full_duplex = 1;
1647 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1649 np->mii_if.full_duplex = 0;
1650 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1652 np->mii_if.full_duplex = 1;
1655 np->mii_if.full_duplex = 0;
1658 /* autonegotiation is disabled */
1659 if (reg0 & BMCR_SPEED100)
1663 if (reg0 & BMCR_FULLDPLX)
1664 np->mii_if.full_duplex = 1;
1666 np->mii_if.full_duplex = 0;
1668 netif_carrier_on(dev);
1669 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1671 np->speed100 ? "100" : "10",
1672 np->mii_if.full_duplex ? "full" : "half");
1674 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1675 if (np->mii_if.full_duplex)
1676 new_tx_mode |= FullDuplex;
1677 if (np->tx_mode != new_tx_mode) {
1678 np->tx_mode = new_tx_mode;
1679 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1681 writel(np->tx_mode, ioaddr + TxMode);
1684 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1686 new_intr_timer_ctrl |= Timer10X;
1687 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1688 np->intr_timer_ctrl = new_intr_timer_ctrl;
1689 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1692 netif_carrier_off(dev);
1693 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1698 static void netdev_error(struct net_device *dev, int intr_status)
1700 struct netdev_private *np = netdev_priv(dev);
1702 /* Came close to underrunning the Tx FIFO, increase threshold. */
1703 if (intr_status & IntrTxDataLow) {
1704 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1705 writel(++np->tx_threshold, np->base + TxThreshold);
1706 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1707 dev->name, np->tx_threshold * 16);
1709 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1711 if (intr_status & IntrRxGFPDead) {
1712 dev->stats.rx_fifo_errors++;
1713 dev->stats.rx_errors++;
1715 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1716 dev->stats.tx_fifo_errors++;
1717 dev->stats.tx_errors++;
1719 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1720 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1721 dev->name, intr_status);
1725 static struct net_device_stats *get_stats(struct net_device *dev)
1727 struct netdev_private *np = netdev_priv(dev);
1728 void __iomem *ioaddr = np->base;
1730 /* This adapter architecture needs no SMP locks. */
1731 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1732 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1733 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1734 dev->stats.tx_aborted_errors =
1735 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1736 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1737 dev->stats.collisions =
1738 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1740 /* The chip only need report frame silently dropped. */
1741 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1742 writew(0, ioaddr + RxDMAStatus);
1743 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1744 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1745 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1746 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1752 static u32 set_vlan_mode(struct netdev_private *np)
1756 void __iomem *filter_addr = np->base + HashTable + 8;
1759 for_each_set_bit(vid, np->active_vlans, VLAN_N_VID) {
1760 if (vlan_count == 32)
1762 writew(vid, filter_addr);
1766 if (vlan_count == 32) {
1767 ret |= PerfectFilterVlan;
1768 while (vlan_count < 32) {
1769 writew(0, filter_addr);
1776 #endif /* VLAN_SUPPORT */
1778 static void set_rx_mode(struct net_device *dev)
1780 struct netdev_private *np = netdev_priv(dev);
1781 void __iomem *ioaddr = np->base;
1782 u32 rx_mode = MinVLANPrio;
1783 struct netdev_hw_addr *ha;
1787 rx_mode |= set_vlan_mode(np);
1788 #endif /* VLAN_SUPPORT */
1790 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1791 rx_mode |= AcceptAll;
1792 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1793 (dev->flags & IFF_ALLMULTI)) {
1794 /* Too many to match, or accept all multicasts. */
1795 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1796 } else if (netdev_mc_count(dev) <= 14) {
1797 /* Use the 16 element perfect filter, skip first two entries. */
1798 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1800 netdev_for_each_mc_addr(ha, dev) {
1801 eaddrs = (__be16 *) ha->addr;
1802 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1803 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1804 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1806 eaddrs = (__be16 *)dev->dev_addr;
1807 i = netdev_mc_count(dev) + 2;
1809 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1810 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1811 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1813 rx_mode |= AcceptBroadcast|PerfectFilter;
1815 /* Must use a multicast hash table. */
1816 void __iomem *filter_addr;
1818 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1820 memset(mc_filter, 0, sizeof(mc_filter));
1821 netdev_for_each_mc_addr(ha, dev) {
1822 /* The chip uses the upper 9 CRC bits
1823 as index into the hash table */
1824 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1825 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1827 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1829 /* Clear the perfect filter list, skip first two entries. */
1830 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1831 eaddrs = (__be16 *)dev->dev_addr;
1832 for (i = 2; i < 16; i++) {
1833 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1834 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1835 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1837 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1838 writew(mc_filter[i], filter_addr);
1839 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1841 writel(rx_mode, ioaddr + RxFilterMode);
1844 static int check_if_running(struct net_device *dev)
1846 if (!netif_running(dev))
1851 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1853 struct netdev_private *np = netdev_priv(dev);
1854 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1855 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1856 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1859 static int get_link_ksettings(struct net_device *dev,
1860 struct ethtool_link_ksettings *cmd)
1862 struct netdev_private *np = netdev_priv(dev);
1863 spin_lock_irq(&np->lock);
1864 mii_ethtool_get_link_ksettings(&np->mii_if, cmd);
1865 spin_unlock_irq(&np->lock);
1869 static int set_link_ksettings(struct net_device *dev,
1870 const struct ethtool_link_ksettings *cmd)
1872 struct netdev_private *np = netdev_priv(dev);
1874 spin_lock_irq(&np->lock);
1875 res = mii_ethtool_set_link_ksettings(&np->mii_if, cmd);
1876 spin_unlock_irq(&np->lock);
1881 static int nway_reset(struct net_device *dev)
1883 struct netdev_private *np = netdev_priv(dev);
1884 return mii_nway_restart(&np->mii_if);
1887 static u32 get_link(struct net_device *dev)
1889 struct netdev_private *np = netdev_priv(dev);
1890 return mii_link_ok(&np->mii_if);
1893 static u32 get_msglevel(struct net_device *dev)
1898 static void set_msglevel(struct net_device *dev, u32 val)
1903 static const struct ethtool_ops ethtool_ops = {
1904 .begin = check_if_running,
1905 .get_drvinfo = get_drvinfo,
1906 .nway_reset = nway_reset,
1907 .get_link = get_link,
1908 .get_msglevel = get_msglevel,
1909 .set_msglevel = set_msglevel,
1910 .get_link_ksettings = get_link_ksettings,
1911 .set_link_ksettings = set_link_ksettings,
1914 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1916 struct netdev_private *np = netdev_priv(dev);
1917 struct mii_ioctl_data *data = if_mii(rq);
1920 if (!netif_running(dev))
1923 spin_lock_irq(&np->lock);
1924 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1925 spin_unlock_irq(&np->lock);
1927 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1933 static int netdev_close(struct net_device *dev)
1935 struct netdev_private *np = netdev_priv(dev);
1936 void __iomem *ioaddr = np->base;
1939 netif_stop_queue(dev);
1941 napi_disable(&np->napi);
1944 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1945 dev->name, (int) readl(ioaddr + IntrStatus));
1946 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1947 dev->name, np->cur_tx, np->dirty_tx,
1948 np->cur_rx, np->dirty_rx);
1951 /* Disable interrupts by clearing the interrupt mask. */
1952 writel(0, ioaddr + IntrEnable);
1954 /* Stop the chip's Tx and Rx processes. */
1955 writel(0, ioaddr + GenCtrl);
1956 readl(ioaddr + GenCtrl);
1959 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1960 (long long) np->tx_ring_dma);
1961 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1962 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1963 i, le32_to_cpu(np->tx_ring[i].status),
1964 (long long) dma_to_cpu(np->tx_ring[i].addr),
1965 le32_to_cpu(np->tx_done_q[i].status));
1966 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1967 (long long) np->rx_ring_dma, np->rx_done_q);
1969 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1970 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1971 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1975 free_irq(np->pci_dev->irq, dev);
1977 /* Free all the skbuffs in the Rx queue. */
1978 for (i = 0; i < RX_RING_SIZE; i++) {
1979 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1980 if (np->rx_info[i].skb != NULL) {
1981 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1982 dev_kfree_skb(np->rx_info[i].skb);
1984 np->rx_info[i].skb = NULL;
1985 np->rx_info[i].mapping = 0;
1987 for (i = 0; i < TX_RING_SIZE; i++) {
1988 struct sk_buff *skb = np->tx_info[i].skb;
1991 pci_unmap_single(np->pci_dev,
1992 np->tx_info[i].mapping,
1993 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1994 np->tx_info[i].mapping = 0;
1996 np->tx_info[i].skb = NULL;
2003 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
2005 struct net_device *dev = pci_get_drvdata(pdev);
2007 if (netif_running(dev)) {
2008 netif_device_detach(dev);
2012 pci_save_state(pdev);
2013 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2018 static int starfire_resume(struct pci_dev *pdev)
2020 struct net_device *dev = pci_get_drvdata(pdev);
2022 pci_set_power_state(pdev, PCI_D0);
2023 pci_restore_state(pdev);
2025 if (netif_running(dev)) {
2027 netif_device_attach(dev);
2032 #endif /* CONFIG_PM */
2035 static void starfire_remove_one(struct pci_dev *pdev)
2037 struct net_device *dev = pci_get_drvdata(pdev);
2038 struct netdev_private *np = netdev_priv(dev);
2042 unregister_netdev(dev);
2045 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2048 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2049 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2050 pci_disable_device(pdev);
2053 pci_release_regions(pdev);
2055 free_netdev(dev); /* Will also free np!! */
2059 static struct pci_driver starfire_driver = {
2061 .probe = starfire_init_one,
2062 .remove = starfire_remove_one,
2064 .suspend = starfire_suspend,
2065 .resume = starfire_resume,
2066 #endif /* CONFIG_PM */
2067 .id_table = starfire_pci_tbl,
2071 static int __init starfire_init (void)
2073 /* when a module, this is printed whether or not devices are found in probe */
2077 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2080 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2082 return pci_register_driver(&starfire_driver);
2086 static void __exit starfire_cleanup (void)
2088 pci_unregister_driver (&starfire_driver);
2092 module_init(starfire_init);
2093 module_exit(starfire_cleanup);