1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
275 static struct vortex_chip_info {
280 } vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
374 {NULL,}, /* NULL terminated list. */
378 static const struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
426 {0,} /* 0 terminated list. */
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
439 #define EL3_STATUS 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459 /* The SetRxFilter command accepts the following classes: */
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463 /* Bits in the general status register. */
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490 /* EEPROM locations. */
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
497 enum Window2 { /* Window 2. */
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
532 /* Boomerang bus master control registers. */
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
558 #define DO_ZEROCOPY 1
560 #define DO_ZEROCOPY 0
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
570 } frag[1+MAX_SKB_FRAGS];
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
651 /* Serialises access to hardware other than MII and variables below.
652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
661 static void window_set(struct vortex_private *vp, int window)
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
669 #define DEFINE_WINDOW_IO(size) \
671 window_read ## size(struct vortex_private *vp, int window, int addr) \
673 unsigned long flags; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
676 window_set(vp, window); \
677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
682 window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
689 spin_unlock_irqrestore(&vp->window_lock, flags); \
696 #define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
698 #define DEVICE_PCI(dev) NULL
701 #define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
705 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
707 #define DEVICE_EISA(dev) NULL
710 #define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
713 /* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
721 static const struct media_table {
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
742 const char str[ETH_GSTRING_LEN];
743 } ethtool_stats_keys[] = {
745 { "tx_max_collisions" },
746 { "tx_multiple_collisions" },
747 { "tx_single_collisions" },
751 /* number of ETHTOOL_GSTATS u64's */
752 #define VORTEX_NUM_STATS 5
754 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
755 int chip_idx, int card_idx);
756 static int vortex_up(struct net_device *dev);
757 static void vortex_down(struct net_device *dev, int final);
758 static int vortex_open(struct net_device *dev);
759 static void mdio_sync(struct vortex_private *vp, int bits);
760 static int mdio_read(struct net_device *dev, int phy_id, int location);
761 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762 static void vortex_timer(unsigned long arg);
763 static void rx_oom_timer(unsigned long arg);
764 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
768 static int vortex_rx(struct net_device *dev);
769 static int boomerang_rx(struct net_device *dev);
770 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
772 static int vortex_close(struct net_device *dev);
773 static void dump_tx_ring(struct net_device *dev);
774 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
775 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776 static void set_rx_mode(struct net_device *dev);
778 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
780 static void vortex_tx_timeout(struct net_device *dev);
781 static void acpi_set_WOL(struct net_device *dev);
782 static const struct ethtool_ops vortex_ethtool_ops;
783 static void set_8021q_mode(struct net_device *dev, int enable);
785 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786 /* Option count limit only -- unlimited interfaces are supported. */
788 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794 static int global_options = -1;
795 static int global_full_duplex = -1;
796 static int global_enable_wol = -1;
797 static int global_use_mmio = -1;
799 /* Variables to work-around the Compaq PCI BIOS32 problem. */
800 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801 static struct net_device *compaq_net_device;
803 static int vortex_cards_found;
805 module_param(debug, int, 0);
806 module_param(global_options, int, 0);
807 module_param_array(options, int, NULL, 0);
808 module_param(global_full_duplex, int, 0);
809 module_param_array(full_duplex, int, NULL, 0);
810 module_param_array(hw_checksums, int, NULL, 0);
811 module_param_array(flow_ctrl, int, NULL, 0);
812 module_param(global_enable_wol, int, 0);
813 module_param_array(enable_wol, int, NULL, 0);
814 module_param(rx_copybreak, int, 0);
815 module_param(max_interrupt_work, int, 0);
816 module_param(compaq_ioaddr, int, 0);
817 module_param(compaq_irq, int, 0);
818 module_param(compaq_device_id, int, 0);
819 module_param(watchdog, int, 0);
820 module_param(global_use_mmio, int, 0);
821 module_param_array(use_mmio, int, NULL, 0);
822 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
826 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
827 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
830 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
831 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
837 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
840 #ifdef CONFIG_NET_POLL_CONTROLLER
841 static void poll_vortex(struct net_device *dev)
843 struct vortex_private *vp = netdev_priv(dev);
845 local_irq_save(flags);
846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
847 local_irq_restore(flags);
853 static int vortex_suspend(struct device *dev)
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
858 if (!ndev || !netif_running(ndev))
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
867 static int vortex_resume(struct device *dev)
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
873 if (!ndev || !netif_running(ndev))
876 err = vortex_up(ndev);
880 netif_device_attach(ndev);
885 static const struct dev_pm_ops vortex_pm_ops = {
886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
894 #define VORTEX_PM_OPS (&vortex_pm_ops)
896 #else /* !CONFIG_PM */
898 #define VORTEX_PM_OPS NULL
900 #endif /* !CONFIG_PM */
903 static struct eisa_device_id vortex_eisa_ids[] = {
904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
908 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
910 static int vortex_eisa_probe(struct device *device)
912 void __iomem *ioaddr;
913 struct eisa_device *edev;
915 edev = to_eisa_device(device);
917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
923 edev->id.driver_data, vortex_cards_found)) {
924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
928 vortex_cards_found++;
933 static int vortex_eisa_remove(struct device *device)
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
938 void __iomem *ioaddr;
940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
944 pr_err("vortex_eisa_remove called for Compaq device!\n");
948 vp = netdev_priv(dev);
951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
959 static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
963 .probe = vortex_eisa_probe,
964 .remove = vortex_eisa_remove
968 #endif /* CONFIG_EISA */
970 /* returns count found (>= 0), or negative on error */
971 static int __init vortex_eisa_init(void)
974 int orig_cards_found = vortex_cards_found;
979 err = eisa_driver_register (&vortex_eisa_driver);
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
986 * found, and let the sysfs magic happened...
992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
998 return vortex_cards_found - orig_cards_found + eisa_found;
1001 /* returns count (>= 0), or negative on error */
1002 static int vortex_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1009 /* wake up and enable device */
1010 rc = pci_enable_device(pdev);
1014 rc = pci_request_regions(pdev, DRV_NAME);
1018 unit = vortex_cards_found;
1020 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1021 /* Determine the default if the user didn't override us */
1022 vci = &vortex_info_tbl[ent->driver_data];
1023 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1024 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1025 pci_bar = use_mmio[unit] ? 1 : 0;
1027 pci_bar = global_use_mmio ? 1 : 0;
1029 ioaddr = pci_iomap(pdev, pci_bar, 0);
1030 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1031 ioaddr = pci_iomap(pdev, 0, 0);
1037 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1038 ent->driver_data, unit);
1042 vortex_cards_found++;
1046 pci_iounmap(pdev, ioaddr);
1048 pci_release_regions(pdev);
1050 pci_disable_device(pdev);
1055 static const struct net_device_ops boomrang_netdev_ops = {
1056 .ndo_open = vortex_open,
1057 .ndo_stop = vortex_close,
1058 .ndo_start_xmit = boomerang_start_xmit,
1059 .ndo_tx_timeout = vortex_tx_timeout,
1060 .ndo_get_stats = vortex_get_stats,
1062 .ndo_do_ioctl = vortex_ioctl,
1064 .ndo_set_rx_mode = set_rx_mode,
1065 .ndo_change_mtu = eth_change_mtu,
1066 .ndo_set_mac_address = eth_mac_addr,
1067 .ndo_validate_addr = eth_validate_addr,
1068 #ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = poll_vortex,
1073 static const struct net_device_ops vortex_netdev_ops = {
1074 .ndo_open = vortex_open,
1075 .ndo_stop = vortex_close,
1076 .ndo_start_xmit = vortex_start_xmit,
1077 .ndo_tx_timeout = vortex_tx_timeout,
1078 .ndo_get_stats = vortex_get_stats,
1080 .ndo_do_ioctl = vortex_ioctl,
1082 .ndo_set_rx_mode = set_rx_mode,
1083 .ndo_change_mtu = eth_change_mtu,
1084 .ndo_set_mac_address = eth_mac_addr,
1085 .ndo_validate_addr = eth_validate_addr,
1086 #ifdef CONFIG_NET_POLL_CONTROLLER
1087 .ndo_poll_controller = poll_vortex,
1092 * Start up the PCI/EISA device which is described by *gendev.
1093 * Return 0 on success.
1095 * NOTE: pdev can be NULL, for the case of a Compaq device
1097 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1098 int chip_idx, int card_idx)
1100 struct vortex_private *vp;
1102 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1104 struct net_device *dev;
1105 static int printed_version;
1106 int retval, print_info;
1107 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1108 const char *print_name = "3c59x";
1109 struct pci_dev *pdev = NULL;
1110 struct eisa_device *edev = NULL;
1112 if (!printed_version) {
1113 pr_info("%s", version);
1114 printed_version = 1;
1118 if ((pdev = DEVICE_PCI(gendev))) {
1119 print_name = pci_name(pdev);
1122 if ((edev = DEVICE_EISA(gendev))) {
1123 print_name = dev_name(&edev->dev);
1127 dev = alloc_etherdev(sizeof(*vp));
1132 SET_NETDEV_DEV(dev, gendev);
1133 vp = netdev_priv(dev);
1135 option = global_options;
1137 /* The lower four bits are the media type. */
1138 if (dev->mem_start) {
1140 * The 'options' param is passed in as the third arg to the
1141 * LILO 'ether=' argument for non-modular use
1143 option = dev->mem_start;
1145 else if (card_idx < MAX_UNITS) {
1146 if (options[card_idx] >= 0)
1147 option = options[card_idx];
1151 if (option & 0x8000)
1153 if (option & 0x4000)
1155 if (option & 0x0400)
1159 print_info = (vortex_debug > 1);
1161 pr_info("See Documentation/networking/vortex.txt\n");
1163 pr_info("%s: 3Com %s %s at %p.\n",
1165 pdev ? "PCI" : "EISA",
1169 dev->base_addr = (unsigned long)ioaddr;
1172 vp->ioaddr = ioaddr;
1173 vp->large_frames = mtu > 1500;
1174 vp->drv_flags = vci->drv_flags;
1175 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1176 vp->io_size = vci->io_size;
1177 vp->card_idx = card_idx;
1180 /* module list only for Compaq device */
1181 if (gendev == NULL) {
1182 compaq_net_device = dev;
1185 /* PCI-only startup logic */
1187 /* enable bus-mastering if necessary */
1188 if (vci->flags & PCI_USES_MASTER)
1189 pci_set_master(pdev);
1191 if (vci->drv_flags & IS_VORTEX) {
1193 u8 new_latency = 248;
1195 /* Check the PCI latency value. On the 3c590 series the latency timer
1196 must be set to the maximum value to avoid data corruption that occurs
1197 when the timer expires during a transfer. This bug exists the Vortex
1199 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1200 if (pci_latency < new_latency) {
1201 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1202 print_name, pci_latency, new_latency);
1203 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1208 spin_lock_init(&vp->lock);
1209 spin_lock_init(&vp->mii_lock);
1210 spin_lock_init(&vp->window_lock);
1211 vp->gendev = gendev;
1213 vp->mii.mdio_read = mdio_read;
1214 vp->mii.mdio_write = mdio_write;
1215 vp->mii.phy_id_mask = 0x1f;
1216 vp->mii.reg_num_mask = 0x1f;
1218 /* Makes sure rings are at least 16 byte aligned. */
1219 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1220 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1226 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1227 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1229 /* if we are a PCI driver, we store info in pdev->driver_data
1230 * instead of a module list */
1232 pci_set_drvdata(pdev, dev);
1234 eisa_set_drvdata(edev, dev);
1236 vp->media_override = 7;
1238 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1239 if (vp->media_override != 7)
1241 vp->full_duplex = (option & 0x200) ? 1 : 0;
1242 vp->bus_master = (option & 16) ? 1 : 0;
1245 if (global_full_duplex > 0)
1246 vp->full_duplex = 1;
1247 if (global_enable_wol > 0)
1250 if (card_idx < MAX_UNITS) {
1251 if (full_duplex[card_idx] > 0)
1252 vp->full_duplex = 1;
1253 if (flow_ctrl[card_idx] > 0)
1255 if (enable_wol[card_idx] > 0)
1259 vp->mii.force_media = vp->full_duplex;
1260 vp->options = option;
1261 /* Read the station address from the EEPROM. */
1265 if (vci->drv_flags & EEPROM_8BIT)
1267 else if (vci->drv_flags & EEPROM_OFFSET)
1268 base = EEPROM_Read + 0x30;
1272 for (i = 0; i < 0x40; i++) {
1274 window_write16(vp, base + i, 0, Wn0EepromCmd);
1275 /* Pause for at least 162 us. for the read to take place. */
1276 for (timer = 10; timer >= 0; timer--) {
1278 if ((window_read16(vp, 0, Wn0EepromCmd) &
1282 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1285 for (i = 0; i < 0x18; i++)
1286 checksum ^= eeprom[i];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1288 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1290 checksum ^= eeprom[i++];
1291 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1293 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1294 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1295 for (i = 0; i < 3; i++)
1296 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1336 (unsigned long long)pci_resource_start(pdev, 2),
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1343 if (vp->drv_flags & INVERT_MII_PWR)
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1359 pr_info("Full duplex capable\n");
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1383 vp->autoselect = AUTOSELECT(config);
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1392 dev->if_port = vp->default_media;
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1426 mii_preamble_required--;
1428 pr_warn(" ***WARNING*** No MII transceivers found!\n");
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 vp->mii.phy_id = vp->phys[0];
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1461 dev->netdev_ops = &vortex_netdev_ops;
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1474 vp->pm_state_valid = 1;
1475 pci_save_state(pdev);
1478 retval = register_netdev(dev);
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1490 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1496 issue_and_wait(struct net_device *dev, int cmd)
1498 struct vortex_private *vp = netdev_priv(dev);
1499 void __iomem *ioaddr = vp->ioaddr;
1502 iowrite16(cmd, ioaddr + EL3_CMD);
1503 for (i = 0; i < 2000; i++) {
1504 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1508 /* OK, that didn't work. Do it the slow way. One second */
1509 for (i = 0; i < 100000; i++) {
1510 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1511 if (vortex_debug > 1)
1512 pr_info("%s: command 0x%04x took %d usecs\n",
1513 dev->name, cmd, i * 10);
1518 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1519 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1523 vortex_set_duplex(struct net_device *dev)
1525 struct vortex_private *vp = netdev_priv(dev);
1527 pr_info("%s: setting %s-duplex.\n",
1528 dev->name, (vp->full_duplex) ? "full" : "half");
1530 /* Set the full-duplex bit. */
1532 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1533 (vp->large_frames ? 0x40 : 0) |
1534 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1539 static void vortex_check_media(struct net_device *dev, unsigned int init)
1541 struct vortex_private *vp = netdev_priv(dev);
1542 unsigned int ok_to_print = 0;
1544 if (vortex_debug > 3)
1547 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1548 vp->full_duplex = vp->mii.full_duplex;
1549 vortex_set_duplex(dev);
1551 vortex_set_duplex(dev);
1556 vortex_up(struct net_device *dev)
1558 struct vortex_private *vp = netdev_priv(dev);
1559 void __iomem *ioaddr = vp->ioaddr;
1560 unsigned int config;
1561 int i, mii_reg1, mii_reg5, err = 0;
1563 if (VORTEX_PCI(vp)) {
1564 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1565 if (vp->pm_state_valid)
1566 pci_restore_state(VORTEX_PCI(vp));
1567 err = pci_enable_device(VORTEX_PCI(vp));
1569 pr_warn("%s: Could not enable device\n", dev->name);
1574 /* Before initializing select the active media port. */
1575 config = window_read32(vp, 3, Wn3_Config);
1577 if (vp->media_override != 7) {
1578 pr_info("%s: Media override to transceiver %d (%s).\n",
1579 dev->name, vp->media_override,
1580 media_tbl[vp->media_override].name);
1581 dev->if_port = vp->media_override;
1582 } else if (vp->autoselect) {
1584 if (vortex_debug > 1)
1585 pr_info("%s: using NWAY device table, not %d\n",
1586 dev->name, dev->if_port);
1587 dev->if_port = XCVR_NWAY;
1589 /* Find first available media type, starting with 100baseTx. */
1590 dev->if_port = XCVR_100baseTx;
1591 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1592 dev->if_port = media_tbl[dev->if_port].next;
1593 if (vortex_debug > 1)
1594 pr_info("%s: first available media type: %s\n",
1595 dev->name, media_tbl[dev->if_port].name);
1598 dev->if_port = vp->default_media;
1599 if (vortex_debug > 1)
1600 pr_info("%s: using default media %s\n",
1601 dev->name, media_tbl[dev->if_port].name);
1604 init_timer(&vp->timer);
1605 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1606 vp->timer.data = (unsigned long)dev;
1607 vp->timer.function = vortex_timer; /* timer handler */
1608 add_timer(&vp->timer);
1610 init_timer(&vp->rx_oom_timer);
1611 vp->rx_oom_timer.data = (unsigned long)dev;
1612 vp->rx_oom_timer.function = rx_oom_timer;
1614 if (vortex_debug > 1)
1615 pr_debug("%s: Initial media type %s.\n",
1616 dev->name, media_tbl[dev->if_port].name);
1618 vp->full_duplex = vp->mii.force_media;
1619 config = BFINS(config, dev->if_port, 20, 4);
1620 if (vortex_debug > 6)
1621 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1622 window_write32(vp, config, 3, Wn3_Config);
1624 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1625 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1626 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1627 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1628 vp->mii.full_duplex = vp->full_duplex;
1630 vortex_check_media(dev, 1);
1633 vortex_set_duplex(dev);
1635 issue_and_wait(dev, TxReset);
1637 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1639 issue_and_wait(dev, RxReset|0x04);
1642 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1644 if (vortex_debug > 1) {
1645 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1646 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1649 /* Set the station address and mask in window 2 each time opened. */
1650 for (i = 0; i < 6; i++)
1651 window_write8(vp, dev->dev_addr[i], 2, i);
1652 for (; i < 12; i+=2)
1653 window_write16(vp, 0, 2, i);
1655 if (vp->cb_fn_base) {
1656 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1657 if (vp->drv_flags & INVERT_LED_PWR)
1659 if (vp->drv_flags & INVERT_MII_PWR)
1661 window_write16(vp, n, 2, Wn2_ResetOptions);
1664 if (dev->if_port == XCVR_10base2)
1665 /* Start the thinnet transceiver. We should really wait 50ms...*/
1666 iowrite16(StartCoax, ioaddr + EL3_CMD);
1667 if (dev->if_port != XCVR_NWAY) {
1669 (window_read16(vp, 4, Wn4_Media) &
1670 ~(Media_10TP|Media_SQE)) |
1671 media_tbl[dev->if_port].media_bits,
1675 /* Switch to the stats window, and clear all stats by reading. */
1676 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1677 for (i = 0; i < 10; i++)
1678 window_read8(vp, 6, i);
1679 window_read16(vp, 6, 10);
1680 window_read16(vp, 6, 12);
1681 /* New: On the Vortex we must also clear the BadSSD counter. */
1682 window_read8(vp, 4, 12);
1683 /* ..and on the Boomerang we enable the extra statistics bits. */
1684 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1686 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1687 vp->cur_rx = vp->dirty_rx = 0;
1688 /* Initialize the RxEarly register as recommended. */
1689 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1690 iowrite32(0x0020, ioaddr + PktStatus);
1691 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1693 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1694 vp->cur_tx = vp->dirty_tx = 0;
1695 if (vp->drv_flags & IS_BOOMERANG)
1696 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1697 /* Clear the Rx, Tx rings. */
1698 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1699 vp->rx_ring[i].status = 0;
1700 for (i = 0; i < TX_RING_SIZE; i++)
1701 vp->tx_skbuff[i] = NULL;
1702 iowrite32(0, ioaddr + DownListPtr);
1704 /* Set receiver mode: presumably accept b-case and phys addr only. */
1706 /* enable 802.1q tagged frames */
1707 set_8021q_mode(dev, 1);
1708 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1710 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1711 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1712 /* Allow status bits to be seen. */
1713 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1714 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1715 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1716 (vp->bus_master ? DMADone : 0);
1717 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1718 (vp->full_bus_master_rx ? 0 : RxComplete) |
1719 StatsFull | HostError | TxComplete | IntReq
1720 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1721 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1722 /* Ack all pending events, and set active indicator mask. */
1723 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1725 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1726 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1727 iowrite32(0x8000, vp->cb_fn_base + 4);
1728 netif_start_queue (dev);
1729 netdev_reset_queue(dev);
1735 vortex_open(struct net_device *dev)
1737 struct vortex_private *vp = netdev_priv(dev);
1741 /* Use the now-standard shared IRQ implementation. */
1742 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1743 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1744 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1748 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1749 if (vortex_debug > 2)
1750 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1751 for (i = 0; i < RX_RING_SIZE; i++) {
1752 struct sk_buff *skb;
1753 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1754 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1755 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1757 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1759 vp->rx_skbuff[i] = skb;
1761 break; /* Bad news! */
1763 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1764 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1766 if (i != RX_RING_SIZE) {
1767 pr_emerg("%s: no memory for rx ring\n", dev->name);
1771 /* Wrap the ring. */
1772 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1775 retval = vortex_up(dev);
1780 for (i = 0; i < RX_RING_SIZE; i++) {
1781 if (vp->rx_skbuff[i]) {
1782 dev_kfree_skb(vp->rx_skbuff[i]);
1783 vp->rx_skbuff[i] = NULL;
1786 free_irq(dev->irq, dev);
1788 if (vortex_debug > 1)
1789 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1795 vortex_timer(unsigned long data)
1797 struct net_device *dev = (struct net_device *)data;
1798 struct vortex_private *vp = netdev_priv(dev);
1799 void __iomem *ioaddr = vp->ioaddr;
1800 int next_tick = 60*HZ;
1804 if (vortex_debug > 2) {
1805 pr_debug("%s: Media selection timer tick happened, %s.\n",
1806 dev->name, media_tbl[dev->if_port].name);
1807 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1810 media_status = window_read16(vp, 4, Wn4_Media);
1811 switch (dev->if_port) {
1812 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1813 if (media_status & Media_LnkBeat) {
1814 netif_carrier_on(dev);
1816 if (vortex_debug > 1)
1817 pr_debug("%s: Media %s has link beat, %x.\n",
1818 dev->name, media_tbl[dev->if_port].name, media_status);
1820 netif_carrier_off(dev);
1821 if (vortex_debug > 1) {
1822 pr_debug("%s: Media %s has no link beat, %x.\n",
1823 dev->name, media_tbl[dev->if_port].name, media_status);
1827 case XCVR_MII: case XCVR_NWAY:
1830 vortex_check_media(dev, 0);
1833 default: /* Other media types handled by Tx timeouts. */
1834 if (vortex_debug > 1)
1835 pr_debug("%s: Media %s has no indication, %x.\n",
1836 dev->name, media_tbl[dev->if_port].name, media_status);
1840 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1844 goto leave_media_alone;
1847 unsigned int config;
1849 spin_lock_irq(&vp->lock);
1852 dev->if_port = media_tbl[dev->if_port].next;
1853 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1854 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1855 dev->if_port = vp->default_media;
1856 if (vortex_debug > 1)
1857 pr_debug("%s: Media selection failing, using default %s port.\n",
1858 dev->name, media_tbl[dev->if_port].name);
1860 if (vortex_debug > 1)
1861 pr_debug("%s: Media selection failed, now trying %s port.\n",
1862 dev->name, media_tbl[dev->if_port].name);
1863 next_tick = media_tbl[dev->if_port].wait;
1866 (media_status & ~(Media_10TP|Media_SQE)) |
1867 media_tbl[dev->if_port].media_bits,
1870 config = window_read32(vp, 3, Wn3_Config);
1871 config = BFINS(config, dev->if_port, 20, 4);
1872 window_write32(vp, config, 3, Wn3_Config);
1874 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1876 if (vortex_debug > 1)
1877 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1878 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1880 spin_unlock_irq(&vp->lock);
1884 if (vortex_debug > 2)
1885 pr_debug("%s: Media selection timer finished, %s.\n",
1886 dev->name, media_tbl[dev->if_port].name);
1888 mod_timer(&vp->timer, RUN_AT(next_tick));
1890 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1893 static void vortex_tx_timeout(struct net_device *dev)
1895 struct vortex_private *vp = netdev_priv(dev);
1896 void __iomem *ioaddr = vp->ioaddr;
1898 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1899 dev->name, ioread8(ioaddr + TxStatus),
1900 ioread16(ioaddr + EL3_STATUS));
1901 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1902 window_read16(vp, 4, Wn4_NetDiag),
1903 window_read16(vp, 4, Wn4_Media),
1904 ioread32(ioaddr + PktStatus),
1905 window_read16(vp, 4, Wn4_FIFODiag));
1906 /* Slight code bloat to be user friendly. */
1907 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1908 pr_err("%s: Transmitter encountered 16 collisions --"
1909 " network cable problem?\n", dev->name);
1910 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1911 pr_err("%s: Interrupt posted but not delivered --"
1912 " IRQ blocked by another device?\n", dev->name);
1913 /* Bad idea here.. but we might as well handle a few events. */
1916 * Block interrupts because vortex_interrupt does a bare spin_lock()
1918 unsigned long flags;
1919 local_irq_save(flags);
1920 if (vp->full_bus_master_tx)
1921 boomerang_interrupt(dev->irq, dev);
1923 vortex_interrupt(dev->irq, dev);
1924 local_irq_restore(flags);
1928 if (vortex_debug > 0)
1931 issue_and_wait(dev, TxReset);
1933 dev->stats.tx_errors++;
1934 if (vp->full_bus_master_tx) {
1935 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1936 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1937 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1938 ioaddr + DownListPtr);
1939 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
1940 netif_wake_queue (dev);
1941 netdev_reset_queue (dev);
1943 if (vp->drv_flags & IS_BOOMERANG)
1944 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1945 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1947 dev->stats.tx_dropped++;
1948 netif_wake_queue(dev);
1949 netdev_reset_queue(dev);
1951 /* Issue Tx Enable */
1952 iowrite16(TxEnable, ioaddr + EL3_CMD);
1953 dev->trans_start = jiffies; /* prevent tx timeout */
1957 * Handle uncommon interrupt sources. This is a separate routine to minimize
1961 vortex_error(struct net_device *dev, int status)
1963 struct vortex_private *vp = netdev_priv(dev);
1964 void __iomem *ioaddr = vp->ioaddr;
1965 int do_tx_reset = 0, reset_mask = 0;
1966 unsigned char tx_status = 0;
1968 if (vortex_debug > 2) {
1969 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1972 if (status & TxComplete) { /* Really "TxError" for us. */
1973 tx_status = ioread8(ioaddr + TxStatus);
1974 /* Presumably a tx-timeout. We must merely re-enable. */
1975 if (vortex_debug > 2 ||
1976 (tx_status != 0x88 && vortex_debug > 0)) {
1977 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1978 dev->name, tx_status);
1979 if (tx_status == 0x82) {
1980 pr_err("Probably a duplex mismatch. See "
1981 "Documentation/networking/vortex.txt\n");
1985 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1986 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1987 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1988 iowrite8(0, ioaddr + TxStatus);
1989 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1991 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1993 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1994 } else { /* Merely re-enable the transmitter. */
1995 iowrite16(TxEnable, ioaddr + EL3_CMD);
1999 if (status & RxEarly) /* Rx early is unused. */
2000 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2002 if (status & StatsFull) { /* Empty statistics. */
2003 static int DoneDidThat;
2004 if (vortex_debug > 4)
2005 pr_debug("%s: Updating stats.\n", dev->name);
2006 update_stats(ioaddr, dev);
2007 /* HACK: Disable statistics as an interrupt source. */
2008 /* This occurs when we have the wrong media type! */
2009 if (DoneDidThat == 0 &&
2010 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2011 pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
2013 iowrite16(SetIntrEnb |
2014 (window_read16(vp, 5, 10) & ~StatsFull),
2016 vp->intr_enable &= ~StatsFull;
2020 if (status & IntReq) { /* Restore all interrupt sources. */
2021 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2022 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2024 if (status & HostError) {
2026 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2027 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2028 dev->name, fifo_diag);
2029 /* Adapter failure requires Tx/Rx reset and reinit. */
2030 if (vp->full_bus_master_tx) {
2031 int bus_status = ioread32(ioaddr + PktStatus);
2032 /* 0x80000000 PCI master abort. */
2033 /* 0x40000000 PCI target abort. */
2035 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2037 /* In this case, blow the card away */
2038 /* Must not enter D3 or we can't legally issue the reset! */
2039 vortex_down(dev, 0);
2040 issue_and_wait(dev, TotalReset | 0xff);
2041 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2042 } else if (fifo_diag & 0x0400)
2044 if (fifo_diag & 0x3000) {
2045 /* Reset Rx fifo and upload logic */
2046 issue_and_wait(dev, RxReset|0x07);
2047 /* Set the Rx filter to the current state. */
2049 /* enable 802.1q VLAN tagged frames */
2050 set_8021q_mode(dev, 1);
2051 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2052 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2057 issue_and_wait(dev, TxReset|reset_mask);
2058 iowrite16(TxEnable, ioaddr + EL3_CMD);
2059 if (!vp->full_bus_master_tx)
2060 netif_wake_queue(dev);
2065 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2067 struct vortex_private *vp = netdev_priv(dev);
2068 void __iomem *ioaddr = vp->ioaddr;
2069 int skblen = skb->len;
2071 /* Put out the doubleword header... */
2072 iowrite32(skb->len, ioaddr + TX_FIFO);
2073 if (vp->bus_master) {
2074 /* Set the bus-master controller to transfer the packet. */
2075 int len = (skb->len + 3) & ~3;
2076 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2078 spin_lock_irq(&vp->window_lock);
2080 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2081 iowrite16(len, ioaddr + Wn7_MasterLen);
2082 spin_unlock_irq(&vp->window_lock);
2084 skb_tx_timestamp(skb);
2085 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2086 /* netif_wake_queue() will be called at the DMADone interrupt. */
2088 /* ... and the packet rounded to a doubleword. */
2089 skb_tx_timestamp(skb);
2090 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2091 dev_consume_skb_any (skb);
2092 if (ioread16(ioaddr + TxFree) > 1536) {
2093 netif_start_queue (dev); /* AKPM: redundant? */
2095 /* Interrupt us when the FIFO has room for max-sized packet. */
2096 netif_stop_queue(dev);
2097 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2101 netdev_sent_queue(dev, skblen);
2103 /* Clear the Tx status stack. */
2108 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2109 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2110 if (vortex_debug > 2)
2111 pr_debug("%s: Tx error, status %2.2x.\n",
2112 dev->name, tx_status);
2113 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2114 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2115 if (tx_status & 0x30) {
2116 issue_and_wait(dev, TxReset);
2118 iowrite16(TxEnable, ioaddr + EL3_CMD);
2120 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2123 return NETDEV_TX_OK;
2127 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2129 struct vortex_private *vp = netdev_priv(dev);
2130 void __iomem *ioaddr = vp->ioaddr;
2131 /* Calculate the next Tx descriptor entry. */
2132 int entry = vp->cur_tx % TX_RING_SIZE;
2133 int skblen = skb->len;
2134 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2135 unsigned long flags;
2136 dma_addr_t dma_addr;
2138 if (vortex_debug > 6) {
2139 pr_debug("boomerang_start_xmit()\n");
2140 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2141 dev->name, vp->cur_tx);
2145 * We can't allow a recursion from our interrupt handler back into the
2146 * tx routine, as they take the same spin lock, and that causes
2147 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2150 if (vp->handling_irq)
2151 return NETDEV_TX_BUSY;
2153 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2154 if (vortex_debug > 0)
2155 pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2157 netif_stop_queue(dev);
2158 return NETDEV_TX_BUSY;
2161 vp->tx_skbuff[entry] = skb;
2163 vp->tx_ring[entry].next = 0;
2165 if (skb->ip_summed != CHECKSUM_PARTIAL)
2166 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2168 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2170 if (!skb_shinfo(skb)->nr_frags) {
2171 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len,
2173 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2176 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2177 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2181 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data,
2182 skb_headlen(skb), PCI_DMA_TODEVICE);
2183 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2186 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2187 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2189 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2190 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2192 dma_addr = skb_frag_dma_map(&VORTEX_PCI(vp)->dev, frag,
2196 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr)) {
2197 for(i = i-1; i >= 0; i--)
2198 dma_unmap_page(&VORTEX_PCI(vp)->dev,
2199 le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2200 le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2203 pci_unmap_single(VORTEX_PCI(vp),
2204 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2205 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2211 vp->tx_ring[entry].frag[i+1].addr =
2212 cpu_to_le32(dma_addr);
2214 if (i == skb_shinfo(skb)->nr_frags-1)
2215 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2217 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2221 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE);
2222 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2224 vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2225 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2226 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2229 spin_lock_irqsave(&vp->lock, flags);
2230 /* Wait for the stall to complete. */
2231 issue_and_wait(dev, DownStall);
2232 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2233 if (ioread32(ioaddr + DownListPtr) == 0) {
2234 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2235 vp->queued_packet++;
2239 netdev_sent_queue(dev, skblen);
2241 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2242 netif_stop_queue (dev);
2243 } else { /* Clear previous interrupt enable. */
2244 #if defined(tx_interrupt_mitigation)
2245 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2246 * were selected, this would corrupt DN_COMPLETE. No?
2248 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2251 skb_tx_timestamp(skb);
2252 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2253 spin_unlock_irqrestore(&vp->lock, flags);
2255 return NETDEV_TX_OK;
2257 dev_err(&VORTEX_PCI(vp)->dev, "Error mapping dma buffer\n");
2261 /* The interrupt handler does all of the Rx thread work and cleans up
2262 after the Tx thread. */
2265 * This is the ISR for the vortex series chips.
2266 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2270 vortex_interrupt(int irq, void *dev_id)
2272 struct net_device *dev = dev_id;
2273 struct vortex_private *vp = netdev_priv(dev);
2274 void __iomem *ioaddr;
2276 int work_done = max_interrupt_work;
2278 unsigned int bytes_compl = 0, pkts_compl = 0;
2280 ioaddr = vp->ioaddr;
2281 spin_lock(&vp->lock);
2283 status = ioread16(ioaddr + EL3_STATUS);
2285 if (vortex_debug > 6)
2286 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2288 if ((status & IntLatch) == 0)
2289 goto handler_exit; /* No interrupt: shared IRQs cause this */
2292 if (status & IntReq) {
2293 status |= vp->deferred;
2297 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2300 if (vortex_debug > 4)
2301 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2302 dev->name, status, ioread8(ioaddr + Timer));
2304 spin_lock(&vp->window_lock);
2308 if (vortex_debug > 5)
2309 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2311 if (status & RxComplete)
2314 if (status & TxAvailable) {
2315 if (vortex_debug > 5)
2316 pr_debug(" TX room bit was handled.\n");
2317 /* There's room in the FIFO for a full-sized packet. */
2318 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2319 netif_wake_queue (dev);
2322 if (status & DMADone) {
2323 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2324 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2325 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2327 bytes_compl += vp->tx_skb->len;
2328 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2329 if (ioread16(ioaddr + TxFree) > 1536) {
2331 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2332 * insufficient FIFO room, the TxAvailable test will succeed and call
2333 * netif_wake_queue()
2335 netif_wake_queue(dev);
2336 } else { /* Interrupt when FIFO has room for max-sized packet. */
2337 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2338 netif_stop_queue(dev);
2342 /* Check for all uncommon interrupts at once. */
2343 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2344 if (status == 0xffff)
2346 if (status & RxEarly)
2348 spin_unlock(&vp->window_lock);
2349 vortex_error(dev, status);
2350 spin_lock(&vp->window_lock);
2354 if (--work_done < 0) {
2355 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2357 /* Disable all pending interrupts. */
2359 vp->deferred |= status;
2360 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2362 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2363 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2364 /* The timer will reenable interrupts. */
2365 mod_timer(&vp->timer, jiffies + 1*HZ);
2368 /* Acknowledge the IRQ. */
2369 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2370 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2372 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2373 spin_unlock(&vp->window_lock);
2375 if (vortex_debug > 4)
2376 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2379 spin_unlock(&vp->lock);
2380 return IRQ_RETVAL(handled);
2384 * This is the ISR for the boomerang series chips.
2385 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2389 boomerang_interrupt(int irq, void *dev_id)
2391 struct net_device *dev = dev_id;
2392 struct vortex_private *vp = netdev_priv(dev);
2393 void __iomem *ioaddr;
2395 int work_done = max_interrupt_work;
2397 unsigned int bytes_compl = 0, pkts_compl = 0;
2399 ioaddr = vp->ioaddr;
2403 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2404 * and boomerang_start_xmit
2406 spin_lock(&vp->lock);
2407 vp->handling_irq = 1;
2409 status = ioread16(ioaddr + EL3_STATUS);
2411 if (vortex_debug > 6)
2412 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2414 if ((status & IntLatch) == 0)
2415 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2418 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2419 if (vortex_debug > 1)
2420 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2424 if (status & IntReq) {
2425 status |= vp->deferred;
2429 if (vortex_debug > 4)
2430 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2431 dev->name, status, ioread8(ioaddr + Timer));
2433 if (vortex_debug > 5)
2434 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2436 if (status & UpComplete) {
2437 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2438 if (vortex_debug > 5)
2439 pr_debug("boomerang_interrupt->boomerang_rx\n");
2443 if (status & DownComplete) {
2444 unsigned int dirty_tx = vp->dirty_tx;
2446 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2447 while (vp->cur_tx - dirty_tx > 0) {
2448 int entry = dirty_tx % TX_RING_SIZE;
2449 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2450 if (ioread32(ioaddr + DownListPtr) ==
2451 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2452 break; /* It still hasn't been processed. */
2454 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2455 break; /* It still hasn't been processed. */
2458 if (vp->tx_skbuff[entry]) {
2459 struct sk_buff *skb = vp->tx_skbuff[entry];
2462 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2463 pci_unmap_single(VORTEX_PCI(vp),
2464 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2465 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2468 pci_unmap_single(VORTEX_PCI(vp),
2469 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2472 bytes_compl += skb->len;
2473 dev_kfree_skb_irq(skb);
2474 vp->tx_skbuff[entry] = NULL;
2476 pr_debug("boomerang_interrupt: no skb!\n");
2478 /* dev->stats.tx_packets++; Counted below. */
2481 vp->dirty_tx = dirty_tx;
2482 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2483 if (vortex_debug > 6)
2484 pr_debug("boomerang_interrupt: wake queue\n");
2485 netif_wake_queue (dev);
2489 /* Check for all uncommon interrupts at once. */
2490 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2491 vortex_error(dev, status);
2493 if (--work_done < 0) {
2494 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2496 /* Disable all pending interrupts. */
2498 vp->deferred |= status;
2499 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2501 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2502 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2503 /* The timer will reenable interrupts. */
2504 mod_timer(&vp->timer, jiffies + 1*HZ);
2507 /* Acknowledge the IRQ. */
2508 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2509 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2510 iowrite32(0x8000, vp->cb_fn_base + 4);
2512 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2513 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2515 if (vortex_debug > 4)
2516 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2519 vp->handling_irq = 0;
2520 spin_unlock(&vp->lock);
2521 return IRQ_RETVAL(handled);
2524 static int vortex_rx(struct net_device *dev)
2526 struct vortex_private *vp = netdev_priv(dev);
2527 void __iomem *ioaddr = vp->ioaddr;
2531 if (vortex_debug > 5)
2532 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2533 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2534 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2535 if (rx_status & 0x4000) { /* Error, update stats. */
2536 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2537 if (vortex_debug > 2)
2538 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2539 dev->stats.rx_errors++;
2540 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2541 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2542 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2543 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2544 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2546 /* The packet length: up to 4.5K!. */
2547 int pkt_len = rx_status & 0x1fff;
2548 struct sk_buff *skb;
2550 skb = netdev_alloc_skb(dev, pkt_len + 5);
2551 if (vortex_debug > 4)
2552 pr_debug("Receiving packet size %d status %4.4x.\n",
2553 pkt_len, rx_status);
2555 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2556 /* 'skb_put()' points to the start of sk_buff data area. */
2557 if (vp->bus_master &&
2558 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2559 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2560 pkt_len, PCI_DMA_FROMDEVICE);
2561 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2562 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2563 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2564 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2566 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2568 ioread32_rep(ioaddr + RX_FIFO,
2569 skb_put(skb, pkt_len),
2570 (pkt_len + 3) >> 2);
2572 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2573 skb->protocol = eth_type_trans(skb, dev);
2575 dev->stats.rx_packets++;
2576 /* Wait a limited time to go to next packet. */
2577 for (i = 200; i >= 0; i--)
2578 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2581 } else if (vortex_debug > 0)
2582 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2583 dev->name, pkt_len);
2584 dev->stats.rx_dropped++;
2586 issue_and_wait(dev, RxDiscard);
2593 boomerang_rx(struct net_device *dev)
2595 struct vortex_private *vp = netdev_priv(dev);
2596 int entry = vp->cur_rx % RX_RING_SIZE;
2597 void __iomem *ioaddr = vp->ioaddr;
2599 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2601 if (vortex_debug > 5)
2602 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2604 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2605 if (--rx_work_limit < 0)
2607 if (rx_status & RxDError) { /* Error, update stats. */
2608 unsigned char rx_error = rx_status >> 16;
2609 if (vortex_debug > 2)
2610 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2611 dev->stats.rx_errors++;
2612 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2613 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2614 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2615 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2616 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2618 /* The packet length: up to 4.5K!. */
2619 int pkt_len = rx_status & 0x1fff;
2620 struct sk_buff *skb;
2621 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2623 if (vortex_debug > 4)
2624 pr_debug("Receiving packet size %d status %4.4x.\n",
2625 pkt_len, rx_status);
2627 /* Check if the packet is long enough to just accept without
2628 copying to a properly sized skbuff. */
2629 if (pkt_len < rx_copybreak &&
2630 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2631 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2632 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2633 /* 'skb_put()' points to the start of sk_buff data area. */
2634 memcpy(skb_put(skb, pkt_len),
2635 vp->rx_skbuff[entry]->data,
2637 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2640 /* Pass up the skbuff already on the Rx ring. */
2641 skb = vp->rx_skbuff[entry];
2642 vp->rx_skbuff[entry] = NULL;
2643 skb_put(skb, pkt_len);
2644 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2647 skb->protocol = eth_type_trans(skb, dev);
2648 { /* Use hardware checksum info. */
2649 int csum_bits = rx_status & 0xee000000;
2651 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2652 csum_bits == (IPChksumValid | UDPChksumValid))) {
2653 skb->ip_summed = CHECKSUM_UNNECESSARY;
2658 dev->stats.rx_packets++;
2660 entry = (++vp->cur_rx) % RX_RING_SIZE;
2662 /* Refill the Rx ring buffers. */
2663 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2664 struct sk_buff *skb;
2665 entry = vp->dirty_rx % RX_RING_SIZE;
2666 if (vp->rx_skbuff[entry] == NULL) {
2667 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2669 static unsigned long last_jif;
2670 if (time_after(jiffies, last_jif + 10 * HZ)) {
2671 pr_warn("%s: memory shortage\n",
2675 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2676 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2677 break; /* Bad news! */
2680 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2681 vp->rx_skbuff[entry] = skb;
2683 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2684 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2690 * If we've hit a total OOM refilling the Rx ring we poll once a second
2691 * for some memory. Otherwise there is no way to restart the rx process.
2694 rx_oom_timer(unsigned long arg)
2696 struct net_device *dev = (struct net_device *)arg;
2697 struct vortex_private *vp = netdev_priv(dev);
2699 spin_lock_irq(&vp->lock);
2700 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2702 if (vortex_debug > 1) {
2703 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2704 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2706 spin_unlock_irq(&vp->lock);
2710 vortex_down(struct net_device *dev, int final_down)
2712 struct vortex_private *vp = netdev_priv(dev);
2713 void __iomem *ioaddr = vp->ioaddr;
2715 netdev_reset_queue(dev);
2716 netif_stop_queue(dev);
2718 del_timer_sync(&vp->rx_oom_timer);
2719 del_timer_sync(&vp->timer);
2721 /* Turn off statistics ASAP. We update dev->stats below. */
2722 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2724 /* Disable the receiver and transmitter. */
2725 iowrite16(RxDisable, ioaddr + EL3_CMD);
2726 iowrite16(TxDisable, ioaddr + EL3_CMD);
2728 /* Disable receiving 802.1q tagged frames */
2729 set_8021q_mode(dev, 0);
2731 if (dev->if_port == XCVR_10base2)
2732 /* Turn off thinnet power. Green! */
2733 iowrite16(StopCoax, ioaddr + EL3_CMD);
2735 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2737 update_stats(ioaddr, dev);
2738 if (vp->full_bus_master_rx)
2739 iowrite32(0, ioaddr + UpListPtr);
2740 if (vp->full_bus_master_tx)
2741 iowrite32(0, ioaddr + DownListPtr);
2743 if (final_down && VORTEX_PCI(vp)) {
2744 vp->pm_state_valid = 1;
2745 pci_save_state(VORTEX_PCI(vp));
2751 vortex_close(struct net_device *dev)
2753 struct vortex_private *vp = netdev_priv(dev);
2754 void __iomem *ioaddr = vp->ioaddr;
2757 if (netif_device_present(dev))
2758 vortex_down(dev, 1);
2760 if (vortex_debug > 1) {
2761 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2762 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2763 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2764 " tx_queued %d Rx pre-checksummed %d.\n",
2765 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2769 if (vp->rx_csumhits &&
2770 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2771 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2772 pr_warn("%s supports hardware checksums, and we're not using them!\n",
2777 free_irq(dev->irq, dev);
2779 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2780 for (i = 0; i < RX_RING_SIZE; i++)
2781 if (vp->rx_skbuff[i]) {
2782 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2783 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2784 dev_kfree_skb(vp->rx_skbuff[i]);
2785 vp->rx_skbuff[i] = NULL;
2788 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2789 for (i = 0; i < TX_RING_SIZE; i++) {
2790 if (vp->tx_skbuff[i]) {
2791 struct sk_buff *skb = vp->tx_skbuff[i];
2795 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2796 pci_unmap_single(VORTEX_PCI(vp),
2797 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2798 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2801 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2804 vp->tx_skbuff[i] = NULL;
2813 dump_tx_ring(struct net_device *dev)
2815 if (vortex_debug > 0) {
2816 struct vortex_private *vp = netdev_priv(dev);
2817 void __iomem *ioaddr = vp->ioaddr;
2819 if (vp->full_bus_master_tx) {
2821 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2823 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2824 vp->full_bus_master_tx,
2825 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2826 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2827 pr_err(" Transmit list %8.8x vs. %p.\n",
2828 ioread32(ioaddr + DownListPtr),
2829 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2830 issue_and_wait(dev, DownStall);
2831 for (i = 0; i < TX_RING_SIZE; i++) {
2832 unsigned int length;
2835 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2837 length = le32_to_cpu(vp->tx_ring[i].length);
2839 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2840 i, &vp->tx_ring[i], length,
2841 le32_to_cpu(vp->tx_ring[i].status));
2844 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2849 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2851 struct vortex_private *vp = netdev_priv(dev);
2852 void __iomem *ioaddr = vp->ioaddr;
2853 unsigned long flags;
2855 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2856 spin_lock_irqsave (&vp->lock, flags);
2857 update_stats(ioaddr, dev);
2858 spin_unlock_irqrestore (&vp->lock, flags);
2863 /* Update statistics.
2864 Unlike with the EL3 we need not worry about interrupts changing
2865 the window setting from underneath us, but we must still guard
2866 against a race condition with a StatsUpdate interrupt updating the
2867 table. This is done by checking that the ASM (!) code generated uses
2868 atomic updates with '+='.
2870 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2872 struct vortex_private *vp = netdev_priv(dev);
2874 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2875 /* Switch to the stats window, and read everything. */
2876 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2877 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2878 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2879 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2880 dev->stats.tx_packets += window_read8(vp, 6, 6);
2881 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2883 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2884 /* Don't bother with register 9, an extension of registers 6&7.
2885 If we do use the 6&7 values the atomic update assumption above
2887 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2888 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2889 /* Extra stats for get_ethtool_stats() */
2890 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2891 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2892 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2893 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2895 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2896 + vp->xstats.tx_single_collisions
2897 + vp->xstats.tx_max_collisions;
2900 u8 up = window_read8(vp, 4, 13);
2901 dev->stats.rx_bytes += (up & 0x0f) << 16;
2902 dev->stats.tx_bytes += (up & 0xf0) << 12;
2906 static int vortex_nway_reset(struct net_device *dev)
2908 struct vortex_private *vp = netdev_priv(dev);
2910 return mii_nway_restart(&vp->mii);
2913 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2915 struct vortex_private *vp = netdev_priv(dev);
2917 return mii_ethtool_gset(&vp->mii, cmd);
2920 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2922 struct vortex_private *vp = netdev_priv(dev);
2924 return mii_ethtool_sset(&vp->mii, cmd);
2927 static u32 vortex_get_msglevel(struct net_device *dev)
2929 return vortex_debug;
2932 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2937 static int vortex_get_sset_count(struct net_device *dev, int sset)
2941 return VORTEX_NUM_STATS;
2947 static void vortex_get_ethtool_stats(struct net_device *dev,
2948 struct ethtool_stats *stats, u64 *data)
2950 struct vortex_private *vp = netdev_priv(dev);
2951 void __iomem *ioaddr = vp->ioaddr;
2952 unsigned long flags;
2954 spin_lock_irqsave(&vp->lock, flags);
2955 update_stats(ioaddr, dev);
2956 spin_unlock_irqrestore(&vp->lock, flags);
2958 data[0] = vp->xstats.tx_deferred;
2959 data[1] = vp->xstats.tx_max_collisions;
2960 data[2] = vp->xstats.tx_multiple_collisions;
2961 data[3] = vp->xstats.tx_single_collisions;
2962 data[4] = vp->xstats.rx_bad_ssd;
2966 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2968 switch (stringset) {
2970 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2978 static void vortex_get_drvinfo(struct net_device *dev,
2979 struct ethtool_drvinfo *info)
2981 struct vortex_private *vp = netdev_priv(dev);
2983 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2984 if (VORTEX_PCI(vp)) {
2985 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2986 sizeof(info->bus_info));
2988 if (VORTEX_EISA(vp))
2989 strlcpy(info->bus_info, dev_name(vp->gendev),
2990 sizeof(info->bus_info));
2992 snprintf(info->bus_info, sizeof(info->bus_info),
2993 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2997 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2999 struct vortex_private *vp = netdev_priv(dev);
3001 if (!VORTEX_PCI(vp))
3004 wol->supported = WAKE_MAGIC;
3008 wol->wolopts |= WAKE_MAGIC;
3011 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3013 struct vortex_private *vp = netdev_priv(dev);
3015 if (!VORTEX_PCI(vp))
3018 if (wol->wolopts & ~WAKE_MAGIC)
3021 if (wol->wolopts & WAKE_MAGIC)
3030 static const struct ethtool_ops vortex_ethtool_ops = {
3031 .get_drvinfo = vortex_get_drvinfo,
3032 .get_strings = vortex_get_strings,
3033 .get_msglevel = vortex_get_msglevel,
3034 .set_msglevel = vortex_set_msglevel,
3035 .get_ethtool_stats = vortex_get_ethtool_stats,
3036 .get_sset_count = vortex_get_sset_count,
3037 .get_settings = vortex_get_settings,
3038 .set_settings = vortex_set_settings,
3039 .get_link = ethtool_op_get_link,
3040 .nway_reset = vortex_nway_reset,
3041 .get_wol = vortex_get_wol,
3042 .set_wol = vortex_set_wol,
3043 .get_ts_info = ethtool_op_get_ts_info,
3048 * Must power the device up to do MDIO operations
3050 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3053 struct vortex_private *vp = netdev_priv(dev);
3054 pci_power_t state = 0;
3057 state = VORTEX_PCI(vp)->current_state;
3059 /* The kernel core really should have pci_get_power_state() */
3062 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3063 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3065 pci_set_power_state(VORTEX_PCI(vp), state);
3072 /* Pre-Cyclone chips have no documented multicast filter, so the only
3073 multicast setting is to receive all multicast frames. At least
3074 the chip has a very clean way to set the mode, unlike many others. */
3075 static void set_rx_mode(struct net_device *dev)
3077 struct vortex_private *vp = netdev_priv(dev);
3078 void __iomem *ioaddr = vp->ioaddr;
3081 if (dev->flags & IFF_PROMISC) {
3082 if (vortex_debug > 3)
3083 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3084 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3085 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3086 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3088 new_mode = SetRxFilter | RxStation | RxBroadcast;
3090 iowrite16(new_mode, ioaddr + EL3_CMD);
3093 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3094 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3095 Note that this must be done after each RxReset due to some backwards
3096 compatibility logic in the Cyclone and Tornado ASICs */
3098 /* The Ethernet Type used for 802.1q tagged frames */
3099 #define VLAN_ETHER_TYPE 0x8100
3101 static void set_8021q_mode(struct net_device *dev, int enable)
3103 struct vortex_private *vp = netdev_priv(dev);
3106 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3107 /* cyclone and tornado chipsets can recognize 802.1q
3108 * tagged frames and treat them correctly */
3110 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3112 max_pkt_size += 4; /* 802.1Q VLAN tag */
3114 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3116 /* set VlanEtherType to let the hardware checksumming
3117 treat tagged frames correctly */
3118 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3120 /* on older cards we have to enable large frames */
3122 vp->large_frames = dev->mtu > 1500 || enable;
3124 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3125 if (vp->large_frames)
3129 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3134 static void set_8021q_mode(struct net_device *dev, int enable)
3141 /* MII transceiver control section.
3142 Read and write the MII registers using software-generated serial
3143 MDIO protocol. See the MII specifications or DP83840A data sheet
3146 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3147 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3148 "overclocking" issues. */
3149 static void mdio_delay(struct vortex_private *vp)
3151 window_read32(vp, 4, Wn4_PhysicalMgmt);
3154 #define MDIO_SHIFT_CLK 0x01
3155 #define MDIO_DIR_WRITE 0x04
3156 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3157 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3158 #define MDIO_DATA_READ 0x02
3159 #define MDIO_ENB_IN 0x00
3161 /* Generate the preamble required for initial synchronization and
3162 a few older transceivers. */
3163 static void mdio_sync(struct vortex_private *vp, int bits)
3165 /* Establish sync by sending at least 32 logic ones. */
3166 while (-- bits >= 0) {
3167 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3169 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3170 4, Wn4_PhysicalMgmt);
3175 static int mdio_read(struct net_device *dev, int phy_id, int location)
3178 struct vortex_private *vp = netdev_priv(dev);
3179 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3180 unsigned int retval = 0;
3182 spin_lock_bh(&vp->mii_lock);
3184 if (mii_preamble_required)
3187 /* Shift the read command bits out. */
3188 for (i = 14; i >= 0; i--) {
3189 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3190 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3192 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3193 4, Wn4_PhysicalMgmt);
3196 /* Read the two transition, 16 data, and wire-idle bits. */
3197 for (i = 19; i > 0; i--) {
3198 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3200 retval = (retval << 1) |
3201 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3202 MDIO_DATA_READ) ? 1 : 0);
3203 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3204 4, Wn4_PhysicalMgmt);
3208 spin_unlock_bh(&vp->mii_lock);
3210 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3213 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3215 struct vortex_private *vp = netdev_priv(dev);
3216 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3219 spin_lock_bh(&vp->mii_lock);
3221 if (mii_preamble_required)
3224 /* Shift the command bits out. */
3225 for (i = 31; i >= 0; i--) {
3226 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3227 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3229 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3230 4, Wn4_PhysicalMgmt);
3233 /* Leave the interface idle. */
3234 for (i = 1; i >= 0; i--) {
3235 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3237 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3238 4, Wn4_PhysicalMgmt);
3242 spin_unlock_bh(&vp->mii_lock);
3245 /* ACPI: Advanced Configuration and Power Interface. */
3246 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3247 static void acpi_set_WOL(struct net_device *dev)
3249 struct vortex_private *vp = netdev_priv(dev);
3250 void __iomem *ioaddr = vp->ioaddr;
3252 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3254 if (vp->enable_wol) {
3255 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3256 window_write16(vp, 2, 7, 0x0c);
3257 /* The RxFilter must accept the WOL frames. */
3258 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3259 iowrite16(RxEnable, ioaddr + EL3_CMD);
3261 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3262 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3268 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3271 /* Change the power state to D3; RxEnable doesn't take effect. */
3272 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3277 static void vortex_remove_one(struct pci_dev *pdev)
3279 struct net_device *dev = pci_get_drvdata(pdev);
3280 struct vortex_private *vp;
3283 pr_err("vortex_remove_one called for Compaq device!\n");
3287 vp = netdev_priv(dev);
3290 pci_iounmap(pdev, vp->cb_fn_base);
3292 unregister_netdev(dev);
3294 pci_set_power_state(pdev, PCI_D0); /* Go active */
3295 if (vp->pm_state_valid)
3296 pci_restore_state(pdev);
3297 pci_disable_device(pdev);
3299 /* Should really use issue_and_wait() here */
3300 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3301 vp->ioaddr + EL3_CMD);
3303 pci_iounmap(pdev, vp->ioaddr);
3305 pci_free_consistent(pdev,
3306 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3307 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3311 pci_release_regions(pdev);
3317 static struct pci_driver vortex_driver = {
3319 .probe = vortex_init_one,
3320 .remove = vortex_remove_one,
3321 .id_table = vortex_pci_tbl,
3322 .driver.pm = VORTEX_PM_OPS,
3326 static int vortex_have_pci;
3327 static int vortex_have_eisa;
3330 static int __init vortex_init(void)
3332 int pci_rc, eisa_rc;
3334 pci_rc = pci_register_driver(&vortex_driver);
3335 eisa_rc = vortex_eisa_init();
3338 vortex_have_pci = 1;
3340 vortex_have_eisa = 1;
3342 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3346 static void __exit vortex_eisa_cleanup(void)
3348 void __iomem *ioaddr;
3351 /* Take care of the EISA devices */
3352 eisa_driver_unregister(&vortex_eisa_driver);
3355 if (compaq_net_device) {
3356 ioaddr = ioport_map(compaq_net_device->base_addr,
3359 unregister_netdev(compaq_net_device);
3360 iowrite16(TotalReset, ioaddr + EL3_CMD);
3361 release_region(compaq_net_device->base_addr,
3364 free_netdev(compaq_net_device);
3369 static void __exit vortex_cleanup(void)
3371 if (vortex_have_pci)
3372 pci_unregister_driver(&vortex_driver);
3373 if (vortex_have_eisa)
3374 vortex_eisa_cleanup();
3378 module_init(vortex_init);
3379 module_exit(vortex_cleanup);