drivers/net/dsa/realtek/rtl8366rb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
   3  *
   4  * This is a sparsely documented chip, the only viable documentation seems
   5  * to be a patched up code drop from the vendor that appear in various
   6  * GPL source trees.
   7  *
   8  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   9  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  10  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
  11  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
  12  * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/irqchip/chained_irq.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/regmap.h>
  24
  25 #include "realtek.h"
  26
  27 #define RTL8366RB_PORT_NUM_CPU          5
  28 #define RTL8366RB_NUM_PORTS             6
  29 #define RTL8366RB_PHY_NO_MAX            4
  30 #define RTL8366RB_PHY_ADDR_MAX          31
  31
  32 /* Switch Global Configuration register */
  33 #define RTL8366RB_SGCR                          0x0000
  34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  35 #define RTL8366RB_SGCR_MAX_LENGTH(a)            ((a) << 4)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  39 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  40 #define RTL8366RB_SGCR_MAX_LENGTH_16000         RTL8366RB_SGCR_MAX_LENGTH(0x3)
  41 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  42 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  43
  44 /* Port Enable Control register */
  45 #define RTL8366RB_PECR                          0x0001
  46
  47 /* Switch per-port learning disablement register */
  48 #define RTL8366RB_PORT_LEARNDIS_CTRL            0x0002
  49
  50 /* Security control, actually aging register */
  51 #define RTL8366RB_SECURITY_CTRL                 0x0003
  52
  53 #define RTL8366RB_SSCR2                         0x0004
  54 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  55
  56 /* Port Mode Control registers */
  57 #define RTL8366RB_PMC0                          0x0005
  58 #define RTL8366RB_PMC0_SPI                      BIT(0)
  59 #define RTL8366RB_PMC0_EN_AUTOLOAD              BIT(1)
  60 #define RTL8366RB_PMC0_PROBE                    BIT(2)
  61 #define RTL8366RB_PMC0_DIS_BISR                 BIT(3)
  62 #define RTL8366RB_PMC0_ADCTEST                  BIT(4)
  63 #define RTL8366RB_PMC0_SRAM_DIAG                BIT(5)
  64 #define RTL8366RB_PMC0_EN_SCAN                  BIT(6)
  65 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT          7
  66 #define RTL8366RB_PMC0_P4_IOMODE_MASK           GENMASK(9, 7)
  67 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT          10
  68 #define RTL8366RB_PMC0_P5_IOMODE_MASK           GENMASK(12, 10)
  69 #define RTL8366RB_PMC0_SDSMODE_SHIFT            13
  70 #define RTL8366RB_PMC0_SDSMODE_MASK             GENMASK(15, 13)
  71 #define RTL8366RB_PMC1                          0x0006
  72
  73 /* Port Mirror Control Register */
  74 #define RTL8366RB_PMCR                          0x0007
  75 #define RTL8366RB_PMCR_SOURCE_PORT(a)           (a)
  76 #define RTL8366RB_PMCR_SOURCE_PORT_MASK         0x000f
  77 #define RTL8366RB_PMCR_MONITOR_PORT(a)          ((a) << 4)
  78 #define RTL8366RB_PMCR_MONITOR_PORT_MASK        0x00f0
  79 #define RTL8366RB_PMCR_MIRROR_RX                BIT(8)
  80 #define RTL8366RB_PMCR_MIRROR_TX                BIT(9)
  81 #define RTL8366RB_PMCR_MIRROR_SPC               BIT(10)
  82 #define RTL8366RB_PMCR_MIRROR_ISO               BIT(11)
  83
  84 /* bits 0..7 = port 0, bits 8..15 = port 1 */
  85 #define RTL8366RB_PAACR0                0x0010
  86 /* bits 0..7 = port 2, bits 8..15 = port 3 */
  87 #define RTL8366RB_PAACR1                0x0011
  88 /* bits 0..7 = port 4, bits 8..15 = port 5 */
  89 #define RTL8366RB_PAACR2                0x0012
  90 #define RTL8366RB_PAACR_SPEED_10M       0
  91 #define RTL8366RB_PAACR_SPEED_100M      1
  92 #define RTL8366RB_PAACR_SPEED_1000M     2
  93 #define RTL8366RB_PAACR_FULL_DUPLEX     BIT(2)
  94 #define RTL8366RB_PAACR_LINK_UP         BIT(4)
  95 #define RTL8366RB_PAACR_TX_PAUSE        BIT(5)
  96 #define RTL8366RB_PAACR_RX_PAUSE        BIT(6)
  97 #define RTL8366RB_PAACR_AN              BIT(7)
  98
  99 /* bits 0..7 = port 0, bits 8..15 = port 1 */
 100 #define RTL8366RB_PSTAT0                0x0014
 101 /* bits 0..7 = port 2, bits 8..15 = port 3 */
 102 #define RTL8366RB_PSTAT1                0x0015
 103 /* bits 0..7 = port 4, bits 8..15 = port 5 */
 104 #define RTL8366RB_PSTAT2                0x0016
 105
 106 #define RTL8366RB_POWER_SAVING_REG      0x0021
 107
 108 /* Spanning tree status (STP) control, two bits per port per FID */
 109 #define RTL8366RB_STP_STATE_BASE        0x0050 /* 0x0050..0x0057 */
 110 #define RTL8366RB_STP_STATE_DISABLED    0x0
 111 #define RTL8366RB_STP_STATE_BLOCKING    0x1
 112 #define RTL8366RB_STP_STATE_LEARNING    0x2
 113 #define RTL8366RB_STP_STATE_FORWARDING  0x3
 114 #define RTL8366RB_STP_MASK              GENMASK(1, 0)
 115 #define RTL8366RB_STP_STATE(port, state) \
 116         ((state) << ((port) * 2))
 117 #define RTL8366RB_STP_STATE_MASK(port) \
 118         RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
 119
 120 /* CPU port control reg */
 121 #define RTL8366RB_CPU_CTRL_REG          0x0061
 122 #define RTL8366RB_CPU_PORTS_MSK         0x00FF
 123 /* Disables inserting custom tag length/type 0x8899 */
 124 #define RTL8366RB_CPU_NO_TAG            BIT(15)
 125 #define RTL8366RB_CPU_TAG_SIZE          4
 126
 127 #define RTL8366RB_SMAR0                 0x0070 /* bits 0..15 */
 128 #define RTL8366RB_SMAR1                 0x0071 /* bits 16..31 */
 129 #define RTL8366RB_SMAR2                 0x0072 /* bits 32..47 */
 130
 131 #define RTL8366RB_RESET_CTRL_REG                0x0100
 132 #define RTL8366RB_CHIP_CTRL_RESET_HW            BIT(0)
 133 #define RTL8366RB_CHIP_CTRL_RESET_SW            BIT(1)
 134
 135 #define RTL8366RB_CHIP_ID_REG                   0x0509
 136 #define RTL8366RB_CHIP_ID_8366                  0x5937
 137 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
 138 #define RTL8366RB_CHIP_VERSION_MASK             0xf
 139
 140 /* PHY registers control */
 141 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
 142 #define RTL8366RB_PHY_CTRL_READ                 BIT(0)
 143 #define RTL8366RB_PHY_CTRL_WRITE                0
 144 #define RTL8366RB_PHY_ACCESS_BUSY_REG           0x8001
 145 #define RTL8366RB_PHY_INT_BUSY                  BIT(0)
 146 #define RTL8366RB_PHY_EXT_BUSY                  BIT(4)
 147 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
 148 #define RTL8366RB_PHY_EXT_CTRL_REG              0x8010
 149 #define RTL8366RB_PHY_EXT_WRDATA_REG            0x8011
 150 #define RTL8366RB_PHY_EXT_RDDATA_REG            0x8012
 151
 152 #define RTL8366RB_PHY_REG_MASK                  0x1f
 153 #define RTL8366RB_PHY_PAGE_OFFSET               5
 154 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
 155 #define RTL8366RB_PHY_NO_OFFSET                 9
 156 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
 157
 158 /* VLAN Ingress Control Register 1, one bit per port.
 159  * bit 0 .. 5 will make the switch drop ingress frames without
 160  * VID such as untagged or priority-tagged frames for respective
 161  * port.
 162  * bit 6 .. 11 will make the switch drop ingress frames carrying
 163  * a C-tag with VID != 0 for respective port.
 164  */
 165 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG        0x037E
 166 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
 167
 168 /* VLAN Ingress Control Register 2, one bit per port.
 169  * bit0 .. bit5 will make the switch drop all ingress frames with
 170  * a VLAN classification that does not include the port is in its
 171  * member set.
 172  */
 173 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
 174
 175 /* LED control registers */
 176 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
 177 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
 178 #define RTL8366RB_LED_BLINKRATE_28MS            0x0000
 179 #define RTL8366RB_LED_BLINKRATE_56MS            0x0001
 180 #define RTL8366RB_LED_BLINKRATE_84MS            0x0002
 181 #define RTL8366RB_LED_BLINKRATE_111MS           0x0003
 182 #define RTL8366RB_LED_BLINKRATE_222MS           0x0004
 183 #define RTL8366RB_LED_BLINKRATE_446MS           0x0005
 184
 185 #define RTL8366RB_LED_CTRL_REG                  0x0431
 186 #define RTL8366RB_LED_OFF                       0x0
 187 #define RTL8366RB_LED_DUP_COL                   0x1
 188 #define RTL8366RB_LED_LINK_ACT                  0x2
 189 #define RTL8366RB_LED_SPD1000                   0x3
 190 #define RTL8366RB_LED_SPD100                    0x4
 191 #define RTL8366RB_LED_SPD10                     0x5
 192 #define RTL8366RB_LED_SPD1000_ACT               0x6
 193 #define RTL8366RB_LED_SPD100_ACT                0x7
 194 #define RTL8366RB_LED_SPD10_ACT                 0x8
 195 #define RTL8366RB_LED_SPD100_10_ACT             0x9
 196 #define RTL8366RB_LED_FIBER                     0xa
 197 #define RTL8366RB_LED_AN_FAULT                  0xb
 198 #define RTL8366RB_LED_LINK_RX                   0xc
 199 #define RTL8366RB_LED_LINK_TX                   0xd
 200 #define RTL8366RB_LED_MASTER                    0xe
 201 #define RTL8366RB_LED_FORCE                     0xf
 202 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
 203 #define RTL8366RB_LED_1_OFFSET                  6
 204 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
 205 #define RTL8366RB_LED_3_OFFSET                  6
 206
 207 #define RTL8366RB_MIB_COUNT                     33
 208 #define RTL8366RB_GLOBAL_MIB_COUNT              1
 209 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
 210 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
 211 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
 212 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
 213 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
 214 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
 215 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
 216 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
 217
 218 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
 219 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
 220                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 221 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 222 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 223
 224 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 225 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 226
 227 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 228 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 229 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 230
 231 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 232
 233 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 234 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 235 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 236 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 237 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 238 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 239 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 240
 241 #define RTL8366RB_NUM_VLANS             16
 242 #define RTL8366RB_NUM_LEDGROUPS         4
 243 #define RTL8366RB_NUM_VIDS              4096
 244 #define RTL8366RB_PRIORITYMAX           7
 245 #define RTL8366RB_NUM_FIDS              8
 246 #define RTL8366RB_FIDMAX                7
 247
 248 #define RTL8366RB_PORT_1                BIT(0) /* In userspace port 0 */
 249 #define RTL8366RB_PORT_2                BIT(1) /* In userspace port 1 */
 250 #define RTL8366RB_PORT_3                BIT(2) /* In userspace port 2 */
 251 #define RTL8366RB_PORT_4                BIT(3) /* In userspace port 3 */
 252 #define RTL8366RB_PORT_5                BIT(4) /* In userspace port 4 */
 253
 254 #define RTL8366RB_PORT_CPU              BIT(5) /* CPU port */
 255
 256 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 257                                          RTL8366RB_PORT_2 |     \
 258                                          RTL8366RB_PORT_3 |     \
 259                                          RTL8366RB_PORT_4 |     \
 260                                          RTL8366RB_PORT_5 |     \
 261                                          RTL8366RB_PORT_CPU)
 262
 263 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 264                                          RTL8366RB_PORT_2 |     \
 265                                          RTL8366RB_PORT_3 |     \
 266                                          RTL8366RB_PORT_4 |     \
 267                                          RTL8366RB_PORT_5)
 268
 269 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 270                                          RTL8366RB_PORT_2 |     \
 271                                          RTL8366RB_PORT_3 |     \
 272                                          RTL8366RB_PORT_4)
 273
 274 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 275
 276 /* First configuration word per member config, VID and prio */
 277 #define RTL8366RB_VLAN_VID_MASK         0xfff
 278 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 279 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 280 /* Second configuration word per member config, member and untagged */
 281 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 282 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 283 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 284 /* Third config word per member config, STAG currently unused */
 285 #define RTL8366RB_VLAN_STAG_MBR_MASK    0xff
 286 #define RTL8366RB_VLAN_STAG_MBR_SHIFT   8
 287 #define RTL8366RB_VLAN_STAG_IDX_MASK    0x7
 288 #define RTL8366RB_VLAN_STAG_IDX_SHIFT   5
 289 #define RTL8366RB_VLAN_FID_MASK         0x7
 290
 291 /* Port ingress bandwidth control */
 292 #define RTL8366RB_IB_BASE               0x0200
 293 #define RTL8366RB_IB_REG(pnum)          (RTL8366RB_IB_BASE + (pnum))
 294 #define RTL8366RB_IB_BDTH_MASK          0x3fff
 295 #define RTL8366RB_IB_PREIFG             BIT(14)
 296
 297 /* Port egress bandwidth control */
 298 #define RTL8366RB_EB_BASE               0x02d1
 299 #define RTL8366RB_EB_REG(pnum)          (RTL8366RB_EB_BASE + (pnum))
 300 #define RTL8366RB_EB_BDTH_MASK          0x3fff
 301 #define RTL8366RB_EB_PREIFG_REG         0x02f8
 302 #define RTL8366RB_EB_PREIFG             BIT(9)
 303
 304 #define RTL8366RB_BDTH_SW_MAX           1048512 /* 1048576? */
 305 #define RTL8366RB_BDTH_UNIT             64
 306 #define RTL8366RB_BDTH_REG_DEFAULT      16383
 307
 308 /* QOS */
 309 #define RTL8366RB_QOS                   BIT(15)
 310 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
 311 #define RTL8366RB_QOS_DEFAULT_PREIFG    1
 312
 313 /* Interrupt handling */
 314 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
 315 #define RTL8366RB_INTERRUPT_POLARITY    BIT(0)
 316 #define RTL8366RB_P4_RGMII_LED          BIT(2)
 317 #define RTL8366RB_INTERRUPT_MASK_REG    0x0441
 318 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
 319 #define RTL8366RB_INTERRUPT_ACLEXCEED   BIT(8)
 320 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
 321 #define RTL8366RB_INTERRUPT_P4_FIBER    BIT(12)
 322 #define RTL8366RB_INTERRUPT_P4_UTP      BIT(13)
 323 #define RTL8366RB_INTERRUPT_VALID       (RTL8366RB_INTERRUPT_LINK_CHGALL | \
 324                                          RTL8366RB_INTERRUPT_ACLEXCEED | \
 325                                          RTL8366RB_INTERRUPT_STORMEXCEED | \
 326                                          RTL8366RB_INTERRUPT_P4_FIBER | \
 327                                          RTL8366RB_INTERRUPT_P4_UTP)
 328 #define RTL8366RB_INTERRUPT_STATUS_REG  0x0442
 329 #define RTL8366RB_NUM_INTERRUPT         14 /* 0..13 */
 330
 331 /* Port isolation registers */
 332 #define RTL8366RB_PORT_ISO_BASE         0x0F08
 333 #define RTL8366RB_PORT_ISO(pnum)        (RTL8366RB_PORT_ISO_BASE + (pnum))
 334 #define RTL8366RB_PORT_ISO_EN           BIT(0)
 335 #define RTL8366RB_PORT_ISO_PORTS_MASK   GENMASK(7, 1)
 336 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
 337
 338 /* bits 0..5 enable force when cleared */
 339 #define RTL8366RB_MAC_FORCE_CTRL_REG    0x0F11
 340
 341 #define RTL8366RB_OAM_PARSER_REG        0x0F14
 342 #define RTL8366RB_OAM_MULTIPLEXER_REG   0x0F15
 343
 344 #define RTL8366RB_GREEN_FEATURE_REG     0x0F51
 345 #define RTL8366RB_GREEN_FEATURE_MSK     0x0007
 346 #define RTL8366RB_GREEN_FEATURE_TX      BIT(0)
 347 #define RTL8366RB_GREEN_FEATURE_RX      BIT(2)
 348
 349 /**
 350  * struct rtl8366rb - RTL8366RB-specific data
 351  * @max_mtu: per-port max MTU setting
 352  * @pvid_enabled: if PVID is set for respective port
 353  */
 354 struct rtl8366rb {
 355         unsigned int max_mtu[RTL8366RB_NUM_PORTS];
 356         bool pvid_enabled[RTL8366RB_NUM_PORTS];
 357 };
 358
 359 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 360         { 0,  0, 4, "IfInOctets"                                },
 361         { 0,  4, 4, "EtherStatsOctets"                          },
 362         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 363         { 0, 10, 2, "EtherFragments"                            },
 364         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 365         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 366         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 367         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 368         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 369         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 370         { 0, 24, 2, "EtherOversizeStats"                        },
 371         { 0, 26, 2, "EtherStatsJabbers"                         },
 372         { 0, 28, 2, "IfInUcastPkts"                             },
 373         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 374         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 375         { 0, 34, 2, "EtherStatsDropEvents"                      },
 376         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 377         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 378         { 0, 40, 2, "Dot3InPauseFrames"                         },
 379         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 380         { 0, 44, 4, "IfOutOctets"                               },
 381         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 382         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 383         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 384         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 385         { 0, 56, 2, "EtherStatsCollisions"                      },
 386         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 387         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 388         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 389         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 390         { 0, 66, 2, "IfOutUcastPkts"                            },
 391         { 0, 68, 2, "IfOutMulticastPkts"                        },
 392         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 393 };
 394
 395 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
 396                                      int port,
 397                                      struct rtl8366_mib_counter *mib,
 398                                      u64 *mibvalue)
 399 {
 400         u32 addr, val;
 401         int ret;
 402         int i;
 403
 404         addr = RTL8366RB_MIB_COUNTER_BASE +
 405                 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 406                 mib->offset;
 407
 408         /* Writing access counter address first
 409          * then ASIC will prepare 64bits counter wait for being retrived
 410          */
 411         ret = regmap_write(priv->map, addr, 0); /* Write whatever */
 412         if (ret)
 413                 return ret;
 414
 415         /* Read MIB control register */
 416         ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
 417         if (ret)
 418                 return -EIO;
 419
 420         if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
 421                 return -EBUSY;
 422
 423         if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
 424                 return -EIO;
 425
 426         /* Read each individual MIB 16 bits at the time */
 427         *mibvalue = 0;
 428         for (i = mib->length; i > 0; i--) {
 429                 ret = regmap_read(priv->map, addr + (i - 1), &val);
 430                 if (ret)
 431                         return ret;
 432                 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
 433         }
 434         return 0;
 435 }
 436
 437 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
 438 {
 439         int line = irqd_to_hwirq(d);
 440         u32 val;
 441
 442         /* For line interrupts we combine link down in bits
 443          * 6..11 with link up in bits 0..5 into one interrupt.
 444          */
 445         if (line < 12)
 446                 val = BIT(line) | BIT(line + 6);
 447         else
 448                 val = BIT(line);
 449         return val;
 450 }
 451
 452 static void rtl8366rb_mask_irq(struct irq_data *d)
 453 {
 454         struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
 455         int ret;
 456
 457         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
 458                                  rtl8366rb_get_irqmask(d), 0);
 459         if (ret)
 460                 dev_err(priv->dev, "could not mask IRQ\n");
 461 }
 462
 463 static void rtl8366rb_unmask_irq(struct irq_data *d)
 464 {
 465         struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
 466         int ret;
 467
 468         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
 469                                  rtl8366rb_get_irqmask(d),
 470                                  rtl8366rb_get_irqmask(d));
 471         if (ret)
 472                 dev_err(priv->dev, "could not unmask IRQ\n");
 473 }
 474
 475 static irqreturn_t rtl8366rb_irq(int irq, void *data)
 476 {
 477         struct realtek_priv *priv = data;
 478         u32 stat;
 479         int ret;
 480
 481         /* This clears the IRQ status register */
 482         ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
 483                           &stat);
 484         if (ret) {
 485                 dev_err(priv->dev, "can't read interrupt status\n");
 486                 return IRQ_NONE;
 487         }
 488         stat &= RTL8366RB_INTERRUPT_VALID;
 489         if (!stat)
 490                 return IRQ_NONE;
 491         while (stat) {
 492                 int line = __ffs(stat);
 493                 int child_irq;
 494
 495                 stat &= ~BIT(line);
 496                 /* For line interrupts we combine link down in bits
 497                  * 6..11 with link up in bits 0..5 into one interrupt.
 498                  */
 499                 if (line < 12 && line > 5)
 500                         line -= 5;
 501                 child_irq = irq_find_mapping(priv->irqdomain, line);
 502                 handle_nested_irq(child_irq);
 503         }
 504         return IRQ_HANDLED;
 505 }
 506
 507 static struct irq_chip rtl8366rb_irq_chip = {
 508         .name = "RTL8366RB",
 509         .irq_mask = rtl8366rb_mask_irq,
 510         .irq_unmask = rtl8366rb_unmask_irq,
 511 };
 512
 513 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
 514                              irq_hw_number_t hwirq)
 515 {
 516         irq_set_chip_data(irq, domain->host_data);
 517         irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
 518         irq_set_nested_thread(irq, 1);
 519         irq_set_noprobe(irq);
 520
 521         return 0;
 522 }
 523
 524 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
 525 {
 526         irq_set_nested_thread(irq, 0);
 527         irq_set_chip_and_handler(irq, NULL, NULL);
 528         irq_set_chip_data(irq, NULL);
 529 }
 530
 531 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
 532         .map = rtl8366rb_irq_map,
 533         .unmap = rtl8366rb_irq_unmap,
 534         .xlate  = irq_domain_xlate_onecell,
 535 };
 536
 537 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
 538 {
 539         struct device_node *intc;
 540         unsigned long irq_trig;
 541         int irq;
 542         int ret;
 543         u32 val;
 544         int i;
 545
 546         intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
 547         if (!intc) {
 548                 dev_err(priv->dev, "missing child interrupt-controller node\n");
 549                 return -EINVAL;
 550         }
 551         /* RB8366RB IRQs cascade off this one */
 552         irq = of_irq_get(intc, 0);
 553         if (irq <= 0) {
 554                 dev_err(priv->dev, "failed to get parent IRQ\n");
 555                 ret = irq ? irq : -EINVAL;
 556                 goto out_put_node;
 557         }
 558
 559         /* This clears the IRQ status register */
 560         ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
 561                           &val);
 562         if (ret) {
 563                 dev_err(priv->dev, "can't read interrupt status\n");
 564                 goto out_put_node;
 565         }
 566
 567         /* Fetch IRQ edge information from the descriptor */
 568         irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
 569         switch (irq_trig) {
 570         case IRQF_TRIGGER_RISING:
 571         case IRQF_TRIGGER_HIGH:
 572                 dev_info(priv->dev, "active high/rising IRQ\n");
 573                 val = 0;
 574                 break;
 575         case IRQF_TRIGGER_FALLING:
 576         case IRQF_TRIGGER_LOW:
 577                 dev_info(priv->dev, "active low/falling IRQ\n");
 578                 val = RTL8366RB_INTERRUPT_POLARITY;
 579                 break;
 580         }
 581         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
 582                                  RTL8366RB_INTERRUPT_POLARITY,
 583                                  val);
 584         if (ret) {
 585                 dev_err(priv->dev, "could not configure IRQ polarity\n");
 586                 goto out_put_node;
 587         }
 588
 589         ret = devm_request_threaded_irq(priv->dev, irq, NULL,
 590                                         rtl8366rb_irq, IRQF_ONESHOT,
 591                                         "RTL8366RB", priv);
 592         if (ret) {
 593                 dev_err(priv->dev, "unable to request irq: %d\n", ret);
 594                 goto out_put_node;
 595         }
 596         priv->irqdomain = irq_domain_add_linear(intc,
 597                                                 RTL8366RB_NUM_INTERRUPT,
 598                                                 &rtl8366rb_irqdomain_ops,
 599                                                 priv);
 600         if (!priv->irqdomain) {
 601                 dev_err(priv->dev, "failed to create IRQ domain\n");
 602                 ret = -EINVAL;
 603                 goto out_put_node;
 604         }
 605         for (i = 0; i < priv->num_ports; i++)
 606                 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
 607
 608 out_put_node:
 609         of_node_put(intc);
 610         return ret;
 611 }
 612
 613 static int rtl8366rb_set_addr(struct realtek_priv *priv)
 614 {
 615         u8 addr[ETH_ALEN];
 616         u16 val;
 617         int ret;
 618
 619         eth_random_addr(addr);
 620
 621         dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
 622                  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 623         val = addr[0] << 8 | addr[1];
 624         ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
 625         if (ret)
 626                 return ret;
 627         val = addr[2] << 8 | addr[3];
 628         ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
 629         if (ret)
 630                 return ret;
 631         val = addr[4] << 8 | addr[5];
 632         ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
 633         if (ret)
 634                 return ret;
 635
 636         return 0;
 637 }
 638
 639 /* Found in a vendor driver */
 640
 641 /* Struct for handling the jam tables' entries */
 642 struct rtl8366rb_jam_tbl_entry {
 643         u16 reg;
 644         u16 val;
 645 };
 646
 647 /* For the "version 0" early silicon, appear in most source releases */
 648 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
 649         {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
 650         {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
 651         {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
 652         {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
 653         {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
 654         {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
 655         {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
 656         {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
 657         {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
 658         {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
 659         {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
 660         {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
 661         {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
 662         {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
 663         {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
 664         {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
 665         {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
 666         {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
 667         {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
 668         {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
 669         {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
 670         {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
 671         {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
 672         {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
 673         {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
 674         {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
 675         {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
 676         {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
 677         {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
 678 };
 679
 680 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
 681 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
 682         {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
 683         {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
 684         {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
 685         {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
 686         {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
 687         {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
 688         {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
 689         {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
 690         {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
 691         {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
 692         {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
 693 };
 694
 695 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
 696 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
 697         {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
 698         {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
 699         {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
 700         {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
 701         {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
 702         {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
 703         {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
 704         {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
 705         {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
 706         {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
 707         {0xBE00, 0x1340}, {0x0F51, 0x0010},
 708 };
 709
 710 /* Appears in a DDWRT code dump */
 711 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
 712         {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
 713         {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
 714         {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
 715         {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
 716         {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
 717         {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
 718         {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
 719         {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
 720         {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
 721         {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
 722         {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
 723         {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
 724         {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
 725         {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
 726         {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
 727         {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
 728         {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
 729 };
 730
 731 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
 732 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
 733         {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
 734         {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
 735         {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
 736         {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
 737         {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
 738         {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
 739         {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
 740         {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
 741         {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
 742 };
 743
 744 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
 745 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
 746         {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
 747         {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
 748         {0x0401, 0x0000}, {0x0431, 0x0960},
 749 };
 750
 751 /* This jam table activates "green ethernet", which means low power mode
 752  * and is claimed to detect the cable length and not use more power than
 753  * necessary, and the ports should enter power saving mode 10 seconds after
 754  * a cable is disconnected. Seems to always be the same.
 755  */
 756 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
 757         {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
 758         {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
 759         {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
 760 };
 761
 762 /* Function that jams the tables in the proper registers */
 763 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
 764                                int jam_size, struct realtek_priv *priv,
 765                                bool write_dbg)
 766 {
 767         u32 val;
 768         int ret;
 769         int i;
 770
 771         for (i = 0; i < jam_size; i++) {
 772                 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
 773                         ret = regmap_read(priv->map,
 774                                           RTL8366RB_PHY_ACCESS_BUSY_REG,
 775                                           &val);
 776                         if (ret)
 777                                 return ret;
 778                         if (!(val & RTL8366RB_PHY_INT_BUSY)) {
 779                                 ret = regmap_write(priv->map,
 780                                                    RTL8366RB_PHY_ACCESS_CTRL_REG,
 781                                                    RTL8366RB_PHY_CTRL_WRITE);
 782                                 if (ret)
 783                                         return ret;
 784                         }
 785                 }
 786                 if (write_dbg)
 787                         dev_dbg(priv->dev, "jam %04x into register %04x\n",
 788                                 jam_table[i].val,
 789                                 jam_table[i].reg);
 790                 ret = regmap_write(priv->map,
 791                                    jam_table[i].reg,
 792                                    jam_table[i].val);
 793                 if (ret)
 794                         return ret;
 795         }
 796         return 0;
 797 }
 798
 799 static int rtl8366rb_setup(struct dsa_switch *ds)
 800 {
 801         struct realtek_priv *priv = ds->priv;
 802         const struct rtl8366rb_jam_tbl_entry *jam_table;
 803         struct rtl8366rb *rb;
 804         u32 chip_ver = 0;
 805         u32 chip_id = 0;
 806         int jam_size;
 807         u32 val;
 808         int ret;
 809         int i;
 810
 811         rb = priv->chip_data;
 812
 813         ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
 814         if (ret) {
 815                 dev_err(priv->dev, "unable to read chip id\n");
 816                 return ret;
 817         }
 818
 819         switch (chip_id) {
 820         case RTL8366RB_CHIP_ID_8366:
 821                 break;
 822         default:
 823                 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
 824                 return -ENODEV;
 825         }
 826
 827         ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
 828                           &chip_ver);
 829         if (ret) {
 830                 dev_err(priv->dev, "unable to read chip version\n");
 831                 return ret;
 832         }
 833
 834         dev_info(priv->dev, "RTL%04x ver %u chip found\n",
 835                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
 836
 837         /* Do the init dance using the right jam table */
 838         switch (chip_ver) {
 839         case 0:
 840                 jam_table = rtl8366rb_init_jam_ver_0;
 841                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
 842                 break;
 843         case 1:
 844                 jam_table = rtl8366rb_init_jam_ver_1;
 845                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
 846                 break;
 847         case 2:
 848                 jam_table = rtl8366rb_init_jam_ver_2;
 849                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
 850                 break;
 851         default:
 852                 jam_table = rtl8366rb_init_jam_ver_3;
 853                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
 854                 break;
 855         }
 856
 857         /* Special jam tables for special routers
 858          * TODO: are these necessary? Maintainers, please test
 859          * without them, using just the off-the-shelf tables.
 860          */
 861         if (of_machine_is_compatible("belkin,f5d8235-v1")) {
 862                 jam_table = rtl8366rb_init_jam_f5d8235;
 863                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
 864         }
 865         if (of_machine_is_compatible("netgear,dgn3500") ||
 866             of_machine_is_compatible("netgear,dgn3500b")) {
 867                 jam_table = rtl8366rb_init_jam_dgn3500;
 868                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
 869         }
 870
 871         ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
 872         if (ret)
 873                 return ret;
 874
 875         /* Isolate all user ports so they can only send packets to itself and the CPU port */
 876         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
 877                 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
 878                                    RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
 879                                    RTL8366RB_PORT_ISO_EN);
 880                 if (ret)
 881                         return ret;
 882         }
 883         /* CPU port can send packets to all ports */
 884         ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
 885                            RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
 886                            RTL8366RB_PORT_ISO_EN);
 887         if (ret)
 888                 return ret;
 889
 890         /* Set up the "green ethernet" feature */
 891         ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
 892                                   ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
 893         if (ret)
 894                 return ret;
 895
 896         ret = regmap_write(priv->map,
 897                            RTL8366RB_GREEN_FEATURE_REG,
 898                            (chip_ver == 1) ? 0x0007 : 0x0003);
 899         if (ret)
 900                 return ret;
 901
 902         /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
 903         ret = regmap_write(priv->map, 0x0c, 0x240);
 904         if (ret)
 905                 return ret;
 906         ret = regmap_write(priv->map, 0x0d, 0x240);
 907         if (ret)
 908                 return ret;
 909
 910         /* Set some random MAC address */
 911         ret = rtl8366rb_set_addr(priv);
 912         if (ret)
 913                 return ret;
 914
 915         /* Enable CPU port with custom DSA tag 8899.
 916          *
 917          * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
 918          * the custom tag is turned off.
 919          */
 920         ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
 921                                  0xFFFF,
 922                                  BIT(priv->cpu_port));
 923         if (ret)
 924                 return ret;
 925
 926         /* Make sure we default-enable the fixed CPU port */
 927         ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
 928                                  BIT(priv->cpu_port),
 929                                  0);
 930         if (ret)
 931                 return ret;
 932
 933         /* Set default maximum packet length to 1536 bytes */
 934         ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
 935                                  RTL8366RB_SGCR_MAX_LENGTH_MASK,
 936                                  RTL8366RB_SGCR_MAX_LENGTH_1536);
 937         if (ret)
 938                 return ret;
 939         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 940                 if (i == priv->cpu_port)
 941                         /* CPU port need to also accept the tag */
 942                         rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
 943                 else
 944                         rb->max_mtu[i] = ETH_DATA_LEN;
 945         }
 946
 947         /* Disable learning for all ports */
 948         ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
 949                            RTL8366RB_PORT_ALL);
 950         if (ret)
 951                 return ret;
 952
 953         /* Enable auto ageing for all ports */
 954         ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
 955         if (ret)
 956                 return ret;
 957
 958         /* Port 4 setup: this enables Port 4, usually the WAN port,
 959          * common PHY IO mode is apparently mode 0, and this is not what
 960          * the port is initialized to. There is no explanation of the
 961          * IO modes in the Realtek source code, if your WAN port is
 962          * connected to something exotic such as fiber, then this might
 963          * be worth experimenting with.
 964          */
 965         ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
 966                                  RTL8366RB_PMC0_P4_IOMODE_MASK,
 967                                  0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
 968         if (ret)
 969                 return ret;
 970
 971         /* Accept all packets by default, we enable filtering on-demand */
 972         ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
 973                            0);
 974         if (ret)
 975                 return ret;
 976         ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
 977                            0);
 978         if (ret)
 979                 return ret;
 980
 981         /* Don't drop packets whose DA has not been learned */
 982         ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
 983                                  RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 984         if (ret)
 985                 return ret;
 986
 987         /* Set blinking, TODO: make this configurable */
 988         ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
 989                                  RTL8366RB_LED_BLINKRATE_MASK,
 990                                  RTL8366RB_LED_BLINKRATE_56MS);
 991         if (ret)
 992                 return ret;
 993
 994         /* Set up LED activity:
 995          * Each port has 4 LEDs, we configure all ports to the same
 996          * behaviour (no individual config) but we can set up each
 997          * LED separately.
 998          */
 999         if (priv->leds_disabled) {
1000                 /* Turn everything off */
1001                 regmap_update_bits(priv->map,
1002                                    RTL8366RB_LED_0_1_CTRL_REG,
1003                                    0x0FFF, 0);
1004                 regmap_update_bits(priv->map,
1005                                    RTL8366RB_LED_2_3_CTRL_REG,
1006                                    0x0FFF, 0);
1007                 regmap_update_bits(priv->map,
1008                                    RTL8366RB_INTERRUPT_CONTROL_REG,
1009                                    RTL8366RB_P4_RGMII_LED,
1010                                    0);
1011                 val = RTL8366RB_LED_OFF;
1012         } else {
1013                 /* TODO: make this configurable per LED */
1014                 val = RTL8366RB_LED_FORCE;
1015         }
1016         for (i = 0; i < 4; i++) {
1017                 ret = regmap_update_bits(priv->map,
1018                                          RTL8366RB_LED_CTRL_REG,
1019                                          0xf << (i * 4),
1020                                          val << (i * 4));
1021                 if (ret)
1022                         return ret;
1023         }
1024
1025         ret = rtl8366_reset_vlan(priv);
1026         if (ret)
1027                 return ret;
1028
1029         ret = rtl8366rb_setup_cascaded_irq(priv);
1030         if (ret)
1031                 dev_info(priv->dev, "no interrupt support\n");
1032
1033         if (priv->setup_interface) {
1034                 ret = priv->setup_interface(ds);
1035                 if (ret) {
1036                         dev_err(priv->dev, "could not set up MDIO bus\n");
1037                         return -ENODEV;
1038                 }
1039         }
1040
1041         return 0;
1042 }
1043
1044 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1045                                                       int port,
1046                                                       enum dsa_tag_protocol mp)
1047 {
1048         /* This switch uses the 4 byte protocol A Realtek DSA tag */
1049         return DSA_TAG_PROTO_RTL4_A;
1050 }
1051
1052 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1053                                        struct phylink_config *config)
1054 {
1055         unsigned long *interfaces = config->supported_interfaces;
1056         struct realtek_priv *priv = ds->priv;
1057
1058         if (port == priv->cpu_port) {
1059                 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1060                 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1061                 /* REVMII only supports 100M FD */
1062                 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1063                 /* RGMII only supports 1G FD */
1064                 phy_interface_set_rgmii(interfaces);
1065
1066                 config->mac_capabilities = MAC_1000 | MAC_100 |
1067                                            MAC_SYM_PAUSE;
1068         } else {
1069                 /* RSGMII port, but we don't have that, and we don't
1070                  * specify in DT, so phylib uses the default of GMII
1071                  */
1072                 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1073                 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1074                                            MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1075         }
1076 }
1077
1078 static void
1079 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1080                       phy_interface_t interface, struct phy_device *phydev,
1081                       int speed, int duplex, bool tx_pause, bool rx_pause)
1082 {
1083         struct realtek_priv *priv = ds->priv;
1084         unsigned int val;
1085         int ret;
1086
1087         /* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1088          * We assume autonegotiation works on the PHY-facing ports.
1089          */
1090         if (port != priv->cpu_port)
1091                 return;
1092
1093         dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1094
1095         ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1096                                  BIT(port), BIT(port));
1097         if (ret) {
1098                 dev_err(priv->dev, "failed to force CPU port\n");
1099                 return;
1100         }
1101
1102         /* Conjure port config */
1103         switch (speed) {
1104         case SPEED_10:
1105                 val = RTL8366RB_PAACR_SPEED_10M;
1106                 break;
1107         case SPEED_100:
1108                 val = RTL8366RB_PAACR_SPEED_100M;
1109                 break;
1110         case SPEED_1000:
1111                 val = RTL8366RB_PAACR_SPEED_1000M;
1112                 break;
1113         default:
1114                 val = RTL8366RB_PAACR_SPEED_1000M;
1115                 break;
1116         }
1117
1118         if (duplex == DUPLEX_FULL)
1119                 val |= RTL8366RB_PAACR_FULL_DUPLEX;
1120
1121         if (tx_pause)
1122                 val |=  RTL8366RB_PAACR_TX_PAUSE;
1123
1124         if (rx_pause)
1125                 val |= RTL8366RB_PAACR_RX_PAUSE;
1126
1127         val |= RTL8366RB_PAACR_LINK_UP;
1128
1129         ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1130                                  0xFF00U,
1131                                  val << 8);
1132         if (ret) {
1133                 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1134                 return;
1135         }
1136
1137         dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1138
1139         /* Enable the CPU port */
1140         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1141                                  0);
1142         if (ret) {
1143                 dev_err(priv->dev, "failed to enable the CPU port\n");
1144                 return;
1145         }
1146 }
1147
1148 static void
1149 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1150                         phy_interface_t interface)
1151 {
1152         struct realtek_priv *priv = ds->priv;
1153         int ret;
1154
1155         if (port != priv->cpu_port)
1156                 return;
1157
1158         dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1159
1160         /* Disable the CPU port */
1161         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1162                                  BIT(port));
1163         if (ret) {
1164                 dev_err(priv->dev, "failed to disable the CPU port\n");
1165                 return;
1166         }
1167 }
1168
1169 static void rb8366rb_set_port_led(struct realtek_priv *priv,
1170                                   int port, bool enable)
1171 {
1172         u16 val = enable ? 0x3f : 0;
1173         int ret;
1174
1175         if (priv->leds_disabled)
1176                 return;
1177
1178         switch (port) {
1179         case 0:
1180                 ret = regmap_update_bits(priv->map,
1181                                          RTL8366RB_LED_0_1_CTRL_REG,
1182                                          0x3F, val);
1183                 break;
1184         case 1:
1185                 ret = regmap_update_bits(priv->map,
1186                                          RTL8366RB_LED_0_1_CTRL_REG,
1187                                          0x3F << RTL8366RB_LED_1_OFFSET,
1188                                          val << RTL8366RB_LED_1_OFFSET);
1189                 break;
1190         case 2:
1191                 ret = regmap_update_bits(priv->map,
1192                                          RTL8366RB_LED_2_3_CTRL_REG,
1193                                          0x3F, val);
1194                 break;
1195         case 3:
1196                 ret = regmap_update_bits(priv->map,
1197                                          RTL8366RB_LED_2_3_CTRL_REG,
1198                                          0x3F << RTL8366RB_LED_3_OFFSET,
1199                                          val << RTL8366RB_LED_3_OFFSET);
1200                 break;
1201         case 4:
1202                 ret = regmap_update_bits(priv->map,
1203                                          RTL8366RB_INTERRUPT_CONTROL_REG,
1204                                          RTL8366RB_P4_RGMII_LED,
1205                                          enable ? RTL8366RB_P4_RGMII_LED : 0);
1206                 break;
1207         default:
1208                 dev_err(priv->dev, "no LED for port %d\n", port);
1209                 return;
1210         }
1211         if (ret)
1212                 dev_err(priv->dev, "error updating LED on port %d\n", port);
1213 }
1214
1215 static int
1216 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1217                       struct phy_device *phy)
1218 {
1219         struct realtek_priv *priv = ds->priv;
1220         int ret;
1221
1222         dev_dbg(priv->dev, "enable port %d\n", port);
1223         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1224                                  0);
1225         if (ret)
1226                 return ret;
1227
1228         rb8366rb_set_port_led(priv, port, true);
1229         return 0;
1230 }
1231
1232 static void
1233 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1234 {
1235         struct realtek_priv *priv = ds->priv;
1236         int ret;
1237
1238         dev_dbg(priv->dev, "disable port %d\n", port);
1239         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1240                                  BIT(port));
1241         if (ret)
1242                 return;
1243
1244         rb8366rb_set_port_led(priv, port, false);
1245 }
1246
1247 static int
1248 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1249                            struct dsa_bridge bridge,
1250                            bool *tx_fwd_offload,
1251                            struct netlink_ext_ack *extack)
1252 {
1253         struct realtek_priv *priv = ds->priv;
1254         unsigned int port_bitmap = 0;
1255         int ret, i;
1256
1257         /* Loop over all other ports than the current one */
1258         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1259                 /* Current port handled last */
1260                 if (i == port)
1261                         continue;
1262                 /* Not on this bridge */
1263                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1264                         continue;
1265                 /* Join this port to each other port on the bridge */
1266                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1267                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1268                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1269                 if (ret)
1270                         dev_err(priv->dev, "failed to join port %d\n", port);
1271
1272                 port_bitmap |= BIT(i);
1273         }
1274
1275         /* Set the bits for the ports we can access */
1276         return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1277                                   RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1278                                   RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1279 }
1280
1281 static void
1282 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1283                             struct dsa_bridge bridge)
1284 {
1285         struct realtek_priv *priv = ds->priv;
1286         unsigned int port_bitmap = 0;
1287         int ret, i;
1288
1289         /* Loop over all other ports than this one */
1290         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1291                 /* Current port handled last */
1292                 if (i == port)
1293                         continue;
1294                 /* Not on this bridge */
1295                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1296                         continue;
1297                 /* Remove this port from any other port on the bridge */
1298                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1299                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1300                 if (ret)
1301                         dev_err(priv->dev, "failed to leave port %d\n", port);
1302
1303                 port_bitmap |= BIT(i);
1304         }
1305
1306         /* Clear the bits for the ports we can not access, leave ourselves */
1307         regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1308                            RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1309 }
1310
1311 /**
1312  * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1313  * @priv: SMI state container
1314  * @port: the port to drop untagged and C-tagged frames on
1315  * @drop: whether to drop or pass untagged and C-tagged frames
1316  *
1317  * Return: zero for success, a negative number on error.
1318  */
1319 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1320 {
1321         return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1322                                   RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1323                                   drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1324 }
1325
1326 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1327                                     bool vlan_filtering,
1328                                     struct netlink_ext_ack *extack)
1329 {
1330         struct realtek_priv *priv = ds->priv;
1331         struct rtl8366rb *rb;
1332         int ret;
1333
1334         rb = priv->chip_data;
1335
1336         dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1337                 vlan_filtering ? "enable" : "disable");
1338
1339         /* If the port is not in the member set, the frame will be dropped */
1340         ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1341                                  BIT(port), vlan_filtering ? BIT(port) : 0);
1342         if (ret)
1343                 return ret;
1344
1345         /* If VLAN filtering is enabled and PVID is also enabled, we must
1346          * not drop any untagged or C-tagged frames. If we turn off VLAN
1347          * filtering on a port, we need to accept any frames.
1348          */
1349         if (vlan_filtering)
1350                 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1351         else
1352                 ret = rtl8366rb_drop_untagged(priv, port, false);
1353
1354         return ret;
1355 }
1356
1357 static int
1358 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1359                                 struct switchdev_brport_flags flags,
1360                                 struct netlink_ext_ack *extack)
1361 {
1362         /* We support enabling/disabling learning */
1363         if (flags.mask & ~(BR_LEARNING))
1364                 return -EINVAL;
1365
1366         return 0;
1367 }
1368
1369 static int
1370 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1371                             struct switchdev_brport_flags flags,
1372                             struct netlink_ext_ack *extack)
1373 {
1374         struct realtek_priv *priv = ds->priv;
1375         int ret;
1376
1377         if (flags.mask & BR_LEARNING) {
1378                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1379                                          BIT(port),
1380                                          (flags.val & BR_LEARNING) ? 0 : BIT(port));
1381                 if (ret)
1382                         return ret;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static void
1389 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1390 {
1391         struct realtek_priv *priv = ds->priv;
1392         u32 val;
1393         int i;
1394
1395         switch (state) {
1396         case BR_STATE_DISABLED:
1397                 val = RTL8366RB_STP_STATE_DISABLED;
1398                 break;
1399         case BR_STATE_BLOCKING:
1400         case BR_STATE_LISTENING:
1401                 val = RTL8366RB_STP_STATE_BLOCKING;
1402                 break;
1403         case BR_STATE_LEARNING:
1404                 val = RTL8366RB_STP_STATE_LEARNING;
1405                 break;
1406         case BR_STATE_FORWARDING:
1407                 val = RTL8366RB_STP_STATE_FORWARDING;
1408                 break;
1409         default:
1410                 dev_err(priv->dev, "unknown bridge state requested\n");
1411                 return;
1412         }
1413
1414         /* Set the same status for the port on all the FIDs */
1415         for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1416                 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1417                                    RTL8366RB_STP_STATE_MASK(port),
1418                                    RTL8366RB_STP_STATE(port, val));
1419         }
1420 }
1421
1422 static void
1423 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1424 {
1425         struct realtek_priv *priv = ds->priv;
1426
1427         /* This will age out any learned L2 entries */
1428         regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1429                            BIT(port), BIT(port));
1430         /* Restore the normal state of things */
1431         regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1432                            BIT(port), 0);
1433 }
1434
1435 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1436 {
1437         struct realtek_priv *priv = ds->priv;
1438         struct rtl8366rb *rb;
1439         unsigned int max_mtu;
1440         u32 len;
1441         int i;
1442
1443         /* Cache the per-port MTU setting */
1444         rb = priv->chip_data;
1445         rb->max_mtu[port] = new_mtu;
1446
1447         /* Roof out the MTU for the entire switch to the greatest
1448          * common denominator: the biggest set for any one port will
1449          * be the biggest MTU for the switch.
1450          */
1451         max_mtu = ETH_DATA_LEN;
1452         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1453                 if (rb->max_mtu[i] > max_mtu)
1454                         max_mtu = rb->max_mtu[i];
1455         }
1456
1457         /* Translate to layer 2 size.
1458          * Add ethernet and (possible) VLAN headers, and checksum to the size.
1459          * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1460          */
1461         max_mtu += VLAN_ETH_HLEN;
1462         max_mtu += ETH_FCS_LEN;
1463
1464         if (max_mtu <= 1522)
1465                 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1466         else if (max_mtu > 1522 && max_mtu <= 1536)
1467                 /* This will be the most common default if using VLAN and
1468                  * CPU tagging on a port as both VLAN and CPU tag will
1469                  * result in 1518 + 4 + 4 = 1526 bytes.
1470                  */
1471                 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1472         else if (max_mtu > 1536 && max_mtu <= 1552)
1473                 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1474         else
1475                 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1476
1477         return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1478                                   RTL8366RB_SGCR_MAX_LENGTH_MASK,
1479                                   len);
1480 }
1481
1482 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1483 {
1484         /* The max MTU is 16000 bytes, so we subtract the ethernet
1485          * headers with VLAN and checksum and arrive at
1486          * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1487          * since that is added to the requested MTU by the DSA framework.
1488          */
1489         return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1490 }
1491
1492 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1493                                  struct rtl8366_vlan_4k *vlan4k)
1494 {
1495         u32 data[3];
1496         int ret;
1497         int i;
1498
1499         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1500
1501         if (vid >= RTL8366RB_NUM_VIDS)
1502                 return -EINVAL;
1503
1504         /* write VID */
1505         ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1506                            vid & RTL8366RB_VLAN_VID_MASK);
1507         if (ret)
1508                 return ret;
1509
1510         /* write table access control word */
1511         ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1512                            RTL8366RB_TABLE_VLAN_READ_CTRL);
1513         if (ret)
1514                 return ret;
1515
1516         for (i = 0; i < 3; i++) {
1517                 ret = regmap_read(priv->map,
1518                                   RTL8366RB_VLAN_TABLE_READ_BASE + i,
1519                                   &data[i]);
1520                 if (ret)
1521                         return ret;
1522         }
1523
1524         vlan4k->vid = vid;
1525         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1526                         RTL8366RB_VLAN_UNTAG_MASK;
1527         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1528         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1529
1530         return 0;
1531 }
1532
1533 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1534                                  const struct rtl8366_vlan_4k *vlan4k)
1535 {
1536         u32 data[3];
1537         int ret;
1538         int i;
1539
1540         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1541             vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1542             vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1543             vlan4k->fid > RTL8366RB_FIDMAX)
1544                 return -EINVAL;
1545
1546         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1547         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1548                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1549                         RTL8366RB_VLAN_UNTAG_SHIFT);
1550         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1551
1552         for (i = 0; i < 3; i++) {
1553                 ret = regmap_write(priv->map,
1554                                    RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1555                                    data[i]);
1556                 if (ret)
1557                         return ret;
1558         }
1559
1560         /* write table access control word */
1561         ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1562                            RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1563
1564         return ret;
1565 }
1566
1567 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1568                                  struct rtl8366_vlan_mc *vlanmc)
1569 {
1570         u32 data[3];
1571         int ret;
1572         int i;
1573
1574         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1575
1576         if (index >= RTL8366RB_NUM_VLANS)
1577                 return -EINVAL;
1578
1579         for (i = 0; i < 3; i++) {
1580                 ret = regmap_read(priv->map,
1581                                   RTL8366RB_VLAN_MC_BASE(index) + i,
1582                                   &data[i]);
1583                 if (ret)
1584                         return ret;
1585         }
1586
1587         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1588         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1589                 RTL8366RB_VLAN_PRIORITY_MASK;
1590         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1591                 RTL8366RB_VLAN_UNTAG_MASK;
1592         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1593         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1594
1595         return 0;
1596 }
1597
1598 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1599                                  const struct rtl8366_vlan_mc *vlanmc)
1600 {
1601         u32 data[3];
1602         int ret;
1603         int i;
1604
1605         if (index >= RTL8366RB_NUM_VLANS ||
1606             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1607             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1608             vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1609             vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1610             vlanmc->fid > RTL8366RB_FIDMAX)
1611                 return -EINVAL;
1612
1613         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1614                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1615                         RTL8366RB_VLAN_PRIORITY_SHIFT);
1616         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1617                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1618                         RTL8366RB_VLAN_UNTAG_SHIFT);
1619         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1620
1621         for (i = 0; i < 3; i++) {
1622                 ret = regmap_write(priv->map,
1623                                    RTL8366RB_VLAN_MC_BASE(index) + i,
1624                                    data[i]);
1625                 if (ret)
1626                         return ret;
1627         }
1628
1629         return 0;
1630 }
1631
1632 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1633 {
1634         u32 data;
1635         int ret;
1636
1637         if (port >= priv->num_ports)
1638                 return -EINVAL;
1639
1640         ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1641                           &data);
1642         if (ret)
1643                 return ret;
1644
1645         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1646                 RTL8366RB_PORT_VLAN_CTRL_MASK;
1647
1648         return 0;
1649 }
1650
1651 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1652 {
1653         struct rtl8366rb *rb;
1654         bool pvid_enabled;
1655         int ret;
1656
1657         rb = priv->chip_data;
1658         pvid_enabled = !!index;
1659
1660         if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1661                 return -EINVAL;
1662
1663         ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1664                                  RTL8366RB_PORT_VLAN_CTRL_MASK <<
1665                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1666                                  (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1667                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1668         if (ret)
1669                 return ret;
1670
1671         rb->pvid_enabled[port] = pvid_enabled;
1672
1673         /* If VLAN filtering is enabled and PVID is also enabled, we must
1674          * not drop any untagged or C-tagged frames. Make sure to update the
1675          * filtering setting.
1676          */
1677         if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port)))
1678                 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1679
1680         return ret;
1681 }
1682
1683 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1684 {
1685         unsigned int max = RTL8366RB_NUM_VLANS - 1;
1686
1687         if (priv->vlan4k_enabled)
1688                 max = RTL8366RB_NUM_VIDS - 1;
1689
1690         if (vlan > max)
1691                 return false;
1692
1693         return true;
1694 }
1695
1696 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1697 {
1698         dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");
1699         return regmap_update_bits(priv->map,
1700                                   RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1701                                   enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1702 }
1703
1704 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1705 {
1706         dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1707         return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1708                                   RTL8366RB_SGCR_EN_VLAN_4KTB,
1709                                   enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1710 }
1711
1712 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1713 {
1714         u32 val;
1715         u32 reg;
1716         int ret;
1717
1718         if (phy > RTL8366RB_PHY_NO_MAX)
1719                 return -EINVAL;
1720
1721         mutex_lock(&priv->map_lock);
1722
1723         ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1724                            RTL8366RB_PHY_CTRL_READ);
1725         if (ret)
1726                 goto out;
1727
1728         reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1729
1730         ret = regmap_write(priv->map_nolock, reg, 0);
1731         if (ret) {
1732                 dev_err(priv->dev,
1733                         "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1734                         phy, regnum, reg, ret);
1735                 goto out;
1736         }
1737
1738         ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1739                           &val);
1740         if (ret)
1741                 goto out;
1742
1743         ret = val;
1744
1745         dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1746                 phy, regnum, reg, val);
1747
1748 out:
1749         mutex_unlock(&priv->map_lock);
1750
1751         return ret;
1752 }
1753
1754 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1755                                u16 val)
1756 {
1757         u32 reg;
1758         int ret;
1759
1760         if (phy > RTL8366RB_PHY_NO_MAX)
1761                 return -EINVAL;
1762
1763         mutex_lock(&priv->map_lock);
1764
1765         ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1766                            RTL8366RB_PHY_CTRL_WRITE);
1767         if (ret)
1768                 goto out;
1769
1770         reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1771
1772         dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1773                 phy, regnum, reg, val);
1774
1775         ret = regmap_write(priv->map_nolock, reg, val);
1776         if (ret)
1777                 goto out;
1778
1779 out:
1780         mutex_unlock(&priv->map_lock);
1781
1782         return ret;
1783 }
1784
1785 static int rtl8366rb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
1786 {
1787         return rtl8366rb_phy_read(ds->priv, phy, regnum);
1788 }
1789
1790 static int rtl8366rb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
1791                                    u16 val)
1792 {
1793         return rtl8366rb_phy_write(ds->priv, phy, regnum, val);
1794 }
1795
1796 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1797 {
1798         int timeout = 10;
1799         u32 val;
1800         int ret;
1801
1802         priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1803                               RTL8366RB_CHIP_CTRL_RESET_HW);
1804         do {
1805                 usleep_range(20000, 25000);
1806                 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1807                 if (ret)
1808                         return ret;
1809
1810                 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1811                         break;
1812         } while (--timeout);
1813
1814         if (!timeout) {
1815                 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1816                 return -EIO;
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int rtl8366rb_detect(struct realtek_priv *priv)
1823 {
1824         struct device *dev = priv->dev;
1825         int ret;
1826         u32 val;
1827
1828         /* Detect device */
1829         ret = regmap_read(priv->map, 0x5c, &val);
1830         if (ret) {
1831                 dev_err(dev, "can't get chip ID (%d)\n", ret);
1832                 return ret;
1833         }
1834
1835         switch (val) {
1836         case 0x6027:
1837                 dev_info(dev, "found an RTL8366S switch\n");
1838                 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1839                 return -ENODEV;
1840         case 0x5937:
1841                 dev_info(dev, "found an RTL8366RB switch\n");
1842                 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1843                 priv->num_ports = RTL8366RB_NUM_PORTS;
1844                 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1845                 priv->mib_counters = rtl8366rb_mib_counters;
1846                 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1847                 break;
1848         default:
1849                 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1850                          val);
1851                 break;
1852         }
1853
1854         ret = rtl8366rb_reset_chip(priv);
1855         if (ret)
1856                 return ret;
1857
1858         return 0;
1859 }
1860
1861 static const struct dsa_switch_ops rtl8366rb_switch_ops_smi = {
1862         .get_tag_protocol = rtl8366_get_tag_protocol,
1863         .setup = rtl8366rb_setup,
1864         .phylink_get_caps = rtl8366rb_phylink_get_caps,
1865         .phylink_mac_link_up = rtl8366rb_mac_link_up,
1866         .phylink_mac_link_down = rtl8366rb_mac_link_down,
1867         .get_strings = rtl8366_get_strings,
1868         .get_ethtool_stats = rtl8366_get_ethtool_stats,
1869         .get_sset_count = rtl8366_get_sset_count,
1870         .port_bridge_join = rtl8366rb_port_bridge_join,
1871         .port_bridge_leave = rtl8366rb_port_bridge_leave,
1872         .port_vlan_filtering = rtl8366rb_vlan_filtering,
1873         .port_vlan_add = rtl8366_vlan_add,
1874         .port_vlan_del = rtl8366_vlan_del,
1875         .port_enable = rtl8366rb_port_enable,
1876         .port_disable = rtl8366rb_port_disable,
1877         .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1878         .port_bridge_flags = rtl8366rb_port_bridge_flags,
1879         .port_stp_state_set = rtl8366rb_port_stp_state_set,
1880         .port_fast_age = rtl8366rb_port_fast_age,
1881         .port_change_mtu = rtl8366rb_change_mtu,
1882         .port_max_mtu = rtl8366rb_max_mtu,
1883 };
1884
1885 static const struct dsa_switch_ops rtl8366rb_switch_ops_mdio = {
1886         .get_tag_protocol = rtl8366_get_tag_protocol,
1887         .setup = rtl8366rb_setup,
1888         .phy_read = rtl8366rb_dsa_phy_read,
1889         .phy_write = rtl8366rb_dsa_phy_write,
1890         .phylink_get_caps = rtl8366rb_phylink_get_caps,
1891         .phylink_mac_link_up = rtl8366rb_mac_link_up,
1892         .phylink_mac_link_down = rtl8366rb_mac_link_down,
1893         .get_strings = rtl8366_get_strings,
1894         .get_ethtool_stats = rtl8366_get_ethtool_stats,
1895         .get_sset_count = rtl8366_get_sset_count,
1896         .port_bridge_join = rtl8366rb_port_bridge_join,
1897         .port_bridge_leave = rtl8366rb_port_bridge_leave,
1898         .port_vlan_filtering = rtl8366rb_vlan_filtering,
1899         .port_vlan_add = rtl8366_vlan_add,
1900         .port_vlan_del = rtl8366_vlan_del,
1901         .port_enable = rtl8366rb_port_enable,
1902         .port_disable = rtl8366rb_port_disable,
1903         .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1904         .port_bridge_flags = rtl8366rb_port_bridge_flags,
1905         .port_stp_state_set = rtl8366rb_port_stp_state_set,
1906         .port_fast_age = rtl8366rb_port_fast_age,
1907         .port_change_mtu = rtl8366rb_change_mtu,
1908         .port_max_mtu = rtl8366rb_max_mtu,
1909 };
1910
1911 static const struct realtek_ops rtl8366rb_ops = {
1912         .detect         = rtl8366rb_detect,
1913         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1914         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1915         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1916         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1917         .get_mc_index   = rtl8366rb_get_mc_index,
1918         .set_mc_index   = rtl8366rb_set_mc_index,
1919         .get_mib_counter = rtl8366rb_get_mib_counter,
1920         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
1921         .enable_vlan    = rtl8366rb_enable_vlan,
1922         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
1923         .phy_read       = rtl8366rb_phy_read,
1924         .phy_write      = rtl8366rb_phy_write,
1925 };
1926
1927 const struct realtek_variant rtl8366rb_variant = {
1928         .ds_ops_smi = &rtl8366rb_switch_ops_smi,
1929         .ds_ops_mdio = &rtl8366rb_switch_ops_mdio,
1930         .ops = &rtl8366rb_ops,
1931         .clk_delay = 10,
1932         .cmd_read = 0xa9,
1933         .cmd_write = 0xa8,
1934         .chip_data_sz = sizeof(struct rtl8366rb),
1935 };
1936 EXPORT_SYMBOL_GPL(rtl8366rb_variant);
1937
1938 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1939 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1940 MODULE_LICENSE("GPL");