drivers/net/dsa/qca8k.c

   1 /*
   2  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   3  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   4  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   5  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 and
   9  * only version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/phy.h>
  19 #include <linux/netdevice.h>
  20 #include <net/dsa.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/if_bridge.h>
  24 #include <linux/mdio.h>
  25 #include <linux/etherdevice.h>
  26
  27 #include "qca8k.h"
  28
  29 #define MIB_DESC(_s, _o, _n)    \
  30         {                       \
  31                 .size = (_s),   \
  32                 .offset = (_o), \
  33                 .name = (_n),   \
  34         }
  35
  36 static const struct qca8k_mib_desc ar8327_mib[] = {
  37         MIB_DESC(1, 0x00, "RxBroad"),
  38         MIB_DESC(1, 0x04, "RxPause"),
  39         MIB_DESC(1, 0x08, "RxMulti"),
  40         MIB_DESC(1, 0x0c, "RxFcsErr"),
  41         MIB_DESC(1, 0x10, "RxAlignErr"),
  42         MIB_DESC(1, 0x14, "RxRunt"),
  43         MIB_DESC(1, 0x18, "RxFragment"),
  44         MIB_DESC(1, 0x1c, "Rx64Byte"),
  45         MIB_DESC(1, 0x20, "Rx128Byte"),
  46         MIB_DESC(1, 0x24, "Rx256Byte"),
  47         MIB_DESC(1, 0x28, "Rx512Byte"),
  48         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  49         MIB_DESC(1, 0x30, "Rx1518Byte"),
  50         MIB_DESC(1, 0x34, "RxMaxByte"),
  51         MIB_DESC(1, 0x38, "RxTooLong"),
  52         MIB_DESC(2, 0x3c, "RxGoodByte"),
  53         MIB_DESC(2, 0x44, "RxBadByte"),
  54         MIB_DESC(1, 0x4c, "RxOverFlow"),
  55         MIB_DESC(1, 0x50, "Filtered"),
  56         MIB_DESC(1, 0x54, "TxBroad"),
  57         MIB_DESC(1, 0x58, "TxPause"),
  58         MIB_DESC(1, 0x5c, "TxMulti"),
  59         MIB_DESC(1, 0x60, "TxUnderRun"),
  60         MIB_DESC(1, 0x64, "Tx64Byte"),
  61         MIB_DESC(1, 0x68, "Tx128Byte"),
  62         MIB_DESC(1, 0x6c, "Tx256Byte"),
  63         MIB_DESC(1, 0x70, "Tx512Byte"),
  64         MIB_DESC(1, 0x74, "Tx1024Byte"),
  65         MIB_DESC(1, 0x78, "Tx1518Byte"),
  66         MIB_DESC(1, 0x7c, "TxMaxByte"),
  67         MIB_DESC(1, 0x80, "TxOverSize"),
  68         MIB_DESC(2, 0x84, "TxByte"),
  69         MIB_DESC(1, 0x8c, "TxCollision"),
  70         MIB_DESC(1, 0x90, "TxAbortCol"),
  71         MIB_DESC(1, 0x94, "TxMultiCol"),
  72         MIB_DESC(1, 0x98, "TxSingleCol"),
  73         MIB_DESC(1, 0x9c, "TxExcDefer"),
  74         MIB_DESC(1, 0xa0, "TxDefer"),
  75         MIB_DESC(1, 0xa4, "TxLateCol"),
  76 };
  77
  78 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  79  * to set the page of the register. Track the last page that was set to reduce
  80  * mdio writes
  81  */
  82 static u16 qca8k_current_page = 0xffff;
  83
  84 static void
  85 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  86 {
  87         regaddr >>= 1;
  88         *r1 = regaddr & 0x1e;
  89
  90         regaddr >>= 5;
  91         *r2 = regaddr & 0x7;
  92
  93         regaddr >>= 3;
  94         *page = regaddr & 0x3ff;
  95 }
  96
  97 static u32
  98 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
  99 {
 100         u32 val;
 101         int ret;
 102
 103         ret = bus->read(bus, phy_id, regnum);
 104         if (ret >= 0) {
 105                 val = ret;
 106                 ret = bus->read(bus, phy_id, regnum + 1);
 107                 val |= ret << 16;
 108         }
 109
 110         if (ret < 0) {
 111                 dev_err_ratelimited(&bus->dev,
 112                                     "failed to read qca8k 32bit register\n");
 113                 return ret;
 114         }
 115
 116         return val;
 117 }
 118
 119 static void
 120 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 121 {
 122         u16 lo, hi;
 123         int ret;
 124
 125         lo = val & 0xffff;
 126         hi = (u16)(val >> 16);
 127
 128         ret = bus->write(bus, phy_id, regnum, lo);
 129         if (ret >= 0)
 130                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 131         if (ret < 0)
 132                 dev_err_ratelimited(&bus->dev,
 133                                     "failed to write qca8k 32bit register\n");
 134 }
 135
 136 static void
 137 qca8k_set_page(struct mii_bus *bus, u16 page)
 138 {
 139         if (page == qca8k_current_page)
 140                 return;
 141
 142         if (bus->write(bus, 0x18, 0, page) < 0)
 143                 dev_err_ratelimited(&bus->dev,
 144                                     "failed to set qca8k page\n");
 145         qca8k_current_page = page;
 146 }
 147
 148 static u32
 149 qca8k_read(struct qca8k_priv *priv, u32 reg)
 150 {
 151         u16 r1, r2, page;
 152         u32 val;
 153
 154         qca8k_split_addr(reg, &r1, &r2, &page);
 155
 156         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 157
 158         qca8k_set_page(priv->bus, page);
 159         val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 160
 161         mutex_unlock(&priv->bus->mdio_lock);
 162
 163         return val;
 164 }
 165
 166 static void
 167 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 168 {
 169         u16 r1, r2, page;
 170
 171         qca8k_split_addr(reg, &r1, &r2, &page);
 172
 173         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 174
 175         qca8k_set_page(priv->bus, page);
 176         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
 177
 178         mutex_unlock(&priv->bus->mdio_lock);
 179 }
 180
 181 static u32
 182 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
 183 {
 184         u16 r1, r2, page;
 185         u32 ret;
 186
 187         qca8k_split_addr(reg, &r1, &r2, &page);
 188
 189         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 190
 191         qca8k_set_page(priv->bus, page);
 192         ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 193         ret &= ~mask;
 194         ret |= val;
 195         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
 196
 197         mutex_unlock(&priv->bus->mdio_lock);
 198
 199         return ret;
 200 }
 201
 202 static void
 203 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 204 {
 205         qca8k_rmw(priv, reg, 0, val);
 206 }
 207
 208 static void
 209 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 210 {
 211         qca8k_rmw(priv, reg, val, 0);
 212 }
 213
 214 static int
 215 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 216 {
 217         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 218
 219         *val = qca8k_read(priv, reg);
 220
 221         return 0;
 222 }
 223
 224 static int
 225 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 226 {
 227         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 228
 229         qca8k_write(priv, reg, val);
 230
 231         return 0;
 232 }
 233
 234 static const struct regmap_range qca8k_readable_ranges[] = {
 235         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 236         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 237         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 238         regmap_reg_range(0x0400, 0x0454), /* ACL */
 239         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 240         regmap_reg_range(0x0800, 0x0b70), /* QM */
 241         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 242         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 243         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 244         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 245         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 246         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 247         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 248         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 249         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 250
 251 };
 252
 253 static const struct regmap_access_table qca8k_readable_table = {
 254         .yes_ranges = qca8k_readable_ranges,
 255         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 256 };
 257
 258 static struct regmap_config qca8k_regmap_config = {
 259         .reg_bits = 16,
 260         .val_bits = 32,
 261         .reg_stride = 4,
 262         .max_register = 0x16ac, /* end MIB - Port6 range */
 263         .reg_read = qca8k_regmap_read,
 264         .reg_write = qca8k_regmap_write,
 265         .rd_table = &qca8k_readable_table,
 266 };
 267
 268 static int
 269 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 270 {
 271         unsigned long timeout;
 272
 273         timeout = jiffies + msecs_to_jiffies(20);
 274
 275         /* loop until the busy flag has cleared */
 276         do {
 277                 u32 val = qca8k_read(priv, reg);
 278                 int busy = val & mask;
 279
 280                 if (!busy)
 281                         break;
 282                 cond_resched();
 283         } while (!time_after_eq(jiffies, timeout));
 284
 285         return time_after_eq(jiffies, timeout);
 286 }
 287
 288 static void
 289 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 290 {
 291         u32 reg[4];
 292         int i;
 293
 294         /* load the ARL table into an array */
 295         for (i = 0; i < 4; i++)
 296                 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
 297
 298         /* vid - 83:72 */
 299         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 300         /* aging - 67:64 */
 301         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 302         /* portmask - 54:48 */
 303         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 304         /* mac - 47:0 */
 305         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 306         fdb->mac[1] = reg[1] & 0xff;
 307         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 308         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 309         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 310         fdb->mac[5] = reg[0] & 0xff;
 311 }
 312
 313 static void
 314 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 315                 u8 aging)
 316 {
 317         u32 reg[3] = { 0 };
 318         int i;
 319
 320         /* vid - 83:72 */
 321         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 322         /* aging - 67:64 */
 323         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 324         /* portmask - 54:48 */
 325         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 326         /* mac - 47:0 */
 327         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 328         reg[1] |= mac[1];
 329         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 330         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 331         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 332         reg[0] |= mac[5];
 333
 334         /* load the array into the ARL table */
 335         for (i = 0; i < 3; i++)
 336                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 337 }
 338
 339 static int
 340 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 341 {
 342         u32 reg;
 343
 344         /* Set the command and FDB index */
 345         reg = QCA8K_ATU_FUNC_BUSY;
 346         reg |= cmd;
 347         if (port >= 0) {
 348                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 349                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 350         }
 351
 352         /* Write the function register triggering the table access */
 353         qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 354
 355         /* wait for completion */
 356         if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
 357                 return -1;
 358
 359         /* Check for table full violation when adding an entry */
 360         if (cmd == QCA8K_FDB_LOAD) {
 361                 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
 362                 if (reg & QCA8K_ATU_FUNC_FULL)
 363                         return -1;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int
 370 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 371 {
 372         int ret;
 373
 374         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 375         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 376         if (ret >= 0)
 377                 qca8k_fdb_read(priv, fdb);
 378
 379         return ret;
 380 }
 381
 382 static int
 383 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 384               u16 vid, u8 aging)
 385 {
 386         int ret;
 387
 388         mutex_lock(&priv->reg_mutex);
 389         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 390         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 391         mutex_unlock(&priv->reg_mutex);
 392
 393         return ret;
 394 }
 395
 396 static int
 397 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 398 {
 399         int ret;
 400
 401         mutex_lock(&priv->reg_mutex);
 402         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 403         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 404         mutex_unlock(&priv->reg_mutex);
 405
 406         return ret;
 407 }
 408
 409 static void
 410 qca8k_fdb_flush(struct qca8k_priv *priv)
 411 {
 412         mutex_lock(&priv->reg_mutex);
 413         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 414         mutex_unlock(&priv->reg_mutex);
 415 }
 416
 417 static void
 418 qca8k_mib_init(struct qca8k_priv *priv)
 419 {
 420         mutex_lock(&priv->reg_mutex);
 421         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 422         qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 423         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 424         qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 425         mutex_unlock(&priv->reg_mutex);
 426 }
 427
 428 static int
 429 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 430 {
 431         u32 reg;
 432
 433         switch (port) {
 434         case 0:
 435                 reg = QCA8K_REG_PORT0_PAD_CTRL;
 436                 break;
 437         case 6:
 438                 reg = QCA8K_REG_PORT6_PAD_CTRL;
 439                 break;
 440         default:
 441                 pr_err("Can't set PAD_CTRL on port %d\n", port);
 442                 return -EINVAL;
 443         }
 444
 445         /* Configure a port to be directly connected to an external
 446          * PHY or MAC.
 447          */
 448         switch (mode) {
 449         case PHY_INTERFACE_MODE_RGMII:
 450                 qca8k_write(priv, reg,
 451                             QCA8K_PORT_PAD_RGMII_EN |
 452                             QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
 453                             QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
 454
 455                 /* According to the datasheet, RGMII delay is enabled through
 456                  * PORT5_PAD_CTRL for all ports, rather than individual port
 457                  * registers
 458                  */
 459                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 460                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 461                 break;
 462         case PHY_INTERFACE_MODE_RGMII_ID:
 463                 /* RGMII_ID needs internal delay. This is enabled through
 464                  * PORT5_PAD_CTRL for all ports, rather than individual port
 465                  * registers
 466                  */
 467                 qca8k_write(priv, reg,
 468                             QCA8K_PORT_PAD_RGMII_EN |
 469                             QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
 470                             QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
 471                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 472                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 473                 break;
 474         case PHY_INTERFACE_MODE_SGMII:
 475                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 476                 break;
 477         default:
 478                 pr_err("xMII mode %d not supported\n", mode);
 479                 return -EINVAL;
 480         }
 481
 482         return 0;
 483 }
 484
 485 static void
 486 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 487 {
 488         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 489
 490         /* Port 0 and 6 have no internal PHY */
 491         if ((port > 0) && (port < 6))
 492                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 493
 494         if (enable)
 495                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 496         else
 497                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 498 }
 499
 500 static int
 501 qca8k_setup(struct dsa_switch *ds)
 502 {
 503         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 504         int ret, i, phy_mode = -1;
 505         u32 mask;
 506
 507         /* Make sure that port 0 is the cpu port */
 508         if (!dsa_is_cpu_port(ds, 0)) {
 509                 pr_err("port 0 is not the CPU port\n");
 510                 return -EINVAL;
 511         }
 512
 513         mutex_init(&priv->reg_mutex);
 514
 515         /* Start by setting up the register mapping */
 516         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
 517                                         &qca8k_regmap_config);
 518         if (IS_ERR(priv->regmap))
 519                 pr_warn("regmap initialization failed");
 520
 521         /* Initialize CPU port pad mode (xMII type, delays...) */
 522         phy_mode = of_get_phy_mode(ds->dst->cpu_dp->dn);
 523         if (phy_mode < 0) {
 524                 pr_err("Can't find phy-mode for master device\n");
 525                 return phy_mode;
 526         }
 527         ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
 528         if (ret < 0)
 529                 return ret;
 530
 531         /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
 532         mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
 533                QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
 534         qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
 535         qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 536                       QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 537         qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
 538         priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
 539
 540         /* Enable MIB counters */
 541         qca8k_mib_init(priv);
 542
 543         /* Enable QCA header mode on the cpu port */
 544         qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
 545                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 546                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 547
 548         /* Disable forwarding by default on all ports */
 549         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 550                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 551                           QCA8K_PORT_LOOKUP_MEMBER, 0);
 552
 553         /* Disable MAC by default on all user ports */
 554         for (i = 1; i < QCA8K_NUM_PORTS; i++)
 555                 if (ds->enabled_port_mask & BIT(i))
 556                         qca8k_port_set_status(priv, i, 0);
 557
 558         /* Forward all unknown frames to CPU port for Linux processing */
 559         qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
 560                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
 561                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
 562                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
 563                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
 564
 565         /* Setup connection between CPU port & user ports */
 566         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 567                 /* CPU port gets connected to all user ports of the switch */
 568                 if (dsa_is_cpu_port(ds, i)) {
 569                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
 570                                   QCA8K_PORT_LOOKUP_MEMBER,
 571                                   ds->enabled_port_mask);
 572                 }
 573
 574                 /* Invividual user ports get connected to CPU port only */
 575                 if (ds->enabled_port_mask & BIT(i)) {
 576                         int shift = 16 * (i % 2);
 577
 578                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 579                                   QCA8K_PORT_LOOKUP_MEMBER,
 580                                   BIT(QCA8K_CPU_PORT));
 581
 582                         /* Enable ARP Auto-learning by default */
 583                         qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 584                                       QCA8K_PORT_LOOKUP_LEARN);
 585
 586                         /* For port based vlans to work we need to set the
 587                          * default egress vid
 588                          */
 589                         qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
 590                                   0xffff << shift, 1 << shift);
 591                         qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
 592                                     QCA8K_PORT_VLAN_CVID(1) |
 593                                     QCA8K_PORT_VLAN_SVID(1));
 594                 }
 595         }
 596
 597         /* Flush the FDB table */
 598         qca8k_fdb_flush(priv);
 599
 600         return 0;
 601 }
 602
 603 static void
 604 qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
 605 {
 606         struct qca8k_priv *priv = ds->priv;
 607         u32 reg;
 608
 609         /* Force fixed-link setting for CPU port, skip others. */
 610         if (!phy_is_pseudo_fixed_link(phy))
 611                 return;
 612
 613         /* Set port speed */
 614         switch (phy->speed) {
 615         case 10:
 616                 reg = QCA8K_PORT_STATUS_SPEED_10;
 617                 break;
 618         case 100:
 619                 reg = QCA8K_PORT_STATUS_SPEED_100;
 620                 break;
 621         case 1000:
 622                 reg = QCA8K_PORT_STATUS_SPEED_1000;
 623                 break;
 624         default:
 625                 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
 626                         port, phy->speed);
 627                 return;
 628         }
 629
 630         /* Set duplex mode */
 631         if (phy->duplex == DUPLEX_FULL)
 632                 reg |= QCA8K_PORT_STATUS_DUPLEX;
 633
 634         /* Force flow control */
 635         if (dsa_is_cpu_port(ds, port))
 636                 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
 637
 638         /* Force link down before changing MAC options */
 639         qca8k_port_set_status(priv, port, 0);
 640         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
 641         qca8k_port_set_status(priv, port, 1);
 642 }
 643
 644 static void
 645 qca8k_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 646 {
 647         int i;
 648
 649         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
 650                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
 651                         ETH_GSTRING_LEN);
 652 }
 653
 654 static void
 655 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
 656                         uint64_t *data)
 657 {
 658         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 659         const struct qca8k_mib_desc *mib;
 660         u32 reg, i;
 661         u64 hi;
 662
 663         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
 664                 mib = &ar8327_mib[i];
 665                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
 666
 667                 data[i] = qca8k_read(priv, reg);
 668                 if (mib->size == 2) {
 669                         hi = qca8k_read(priv, reg + 4);
 670                         data[i] |= hi << 32;
 671                 }
 672         }
 673 }
 674
 675 static int
 676 qca8k_get_sset_count(struct dsa_switch *ds)
 677 {
 678         return ARRAY_SIZE(ar8327_mib);
 679 }
 680
 681 static int
 682 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
 683 {
 684         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 685         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
 686         u32 reg;
 687
 688         mutex_lock(&priv->reg_mutex);
 689         reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
 690         if (eee->eee_enabled)
 691                 reg |= lpi_en;
 692         else
 693                 reg &= ~lpi_en;
 694         qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
 695         mutex_unlock(&priv->reg_mutex);
 696
 697         return 0;
 698 }
 699
 700 static int
 701 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
 702 {
 703         /* Nothing to do on the port's MAC */
 704         return 0;
 705 }
 706
 707 static void
 708 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
 709 {
 710         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 711         u32 stp_state;
 712
 713         switch (state) {
 714         case BR_STATE_DISABLED:
 715                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
 716                 break;
 717         case BR_STATE_BLOCKING:
 718                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
 719                 break;
 720         case BR_STATE_LISTENING:
 721                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
 722                 break;
 723         case BR_STATE_LEARNING:
 724                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
 725                 break;
 726         case BR_STATE_FORWARDING:
 727         default:
 728                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
 729                 break;
 730         }
 731
 732         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 733                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
 734 }
 735
 736 static int
 737 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
 738 {
 739         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 740         int port_mask = BIT(QCA8K_CPU_PORT);
 741         int i;
 742
 743         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 744                 if (ds->ports[i].bridge_dev != br)
 745                         continue;
 746                 /* Add this port to the portvlan mask of the other ports
 747                  * in the bridge
 748                  */
 749                 qca8k_reg_set(priv,
 750                               QCA8K_PORT_LOOKUP_CTRL(i),
 751                               BIT(port));
 752                 if (i != port)
 753                         port_mask |= BIT(i);
 754         }
 755         /* Add all other ports to this ports portvlan mask */
 756         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 757                   QCA8K_PORT_LOOKUP_MEMBER, port_mask);
 758
 759         return 0;
 760 }
 761
 762 static void
 763 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
 764 {
 765         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 766         int i;
 767
 768         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 769                 if (ds->ports[i].bridge_dev != br)
 770                         continue;
 771                 /* Remove this port to the portvlan mask of the other ports
 772                  * in the bridge
 773                  */
 774                 qca8k_reg_clear(priv,
 775                                 QCA8K_PORT_LOOKUP_CTRL(i),
 776                                 BIT(port));
 777         }
 778
 779         /* Set the cpu port to be the only one in the portvlan mask of
 780          * this port
 781          */
 782         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 783                   QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
 784 }
 785
 786 static int
 787 qca8k_port_enable(struct dsa_switch *ds, int port,
 788                   struct phy_device *phy)
 789 {
 790         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 791
 792         qca8k_port_set_status(priv, port, 1);
 793         priv->port_sts[port].enabled = 1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 qca8k_port_disable(struct dsa_switch *ds, int port,
 800                    struct phy_device *phy)
 801 {
 802         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 803
 804         qca8k_port_set_status(priv, port, 0);
 805         priv->port_sts[port].enabled = 0;
 806 }
 807
 808 static int
 809 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
 810                       u16 port_mask, u16 vid)
 811 {
 812         /* Set the vid to the port vlan id if no vid is set */
 813         if (!vid)
 814                 vid = 1;
 815
 816         return qca8k_fdb_add(priv, addr, port_mask, vid,
 817                              QCA8K_ATU_STATUS_STATIC);
 818 }
 819
 820 static int
 821 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
 822                    const unsigned char *addr, u16 vid)
 823 {
 824         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 825         u16 port_mask = BIT(port);
 826
 827         return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
 828 }
 829
 830 static int
 831 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
 832                    const unsigned char *addr, u16 vid)
 833 {
 834         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 835         u16 port_mask = BIT(port);
 836
 837         if (!vid)
 838                 vid = 1;
 839
 840         return qca8k_fdb_del(priv, addr, port_mask, vid);
 841 }
 842
 843 static int
 844 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
 845                     dsa_fdb_dump_cb_t *cb, void *data)
 846 {
 847         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 848         struct qca8k_fdb _fdb = { 0 };
 849         int cnt = QCA8K_NUM_FDB_RECORDS;
 850         bool is_static;
 851         int ret = 0;
 852
 853         mutex_lock(&priv->reg_mutex);
 854         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
 855                 if (!_fdb.aging)
 856                         break;
 857                 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
 858                 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
 859                 if (ret)
 860                         break;
 861         }
 862         mutex_unlock(&priv->reg_mutex);
 863
 864         return 0;
 865 }
 866
 867 static enum dsa_tag_protocol
 868 qca8k_get_tag_protocol(struct dsa_switch *ds)
 869 {
 870         return DSA_TAG_PROTO_QCA;
 871 }
 872
 873 static const struct dsa_switch_ops qca8k_switch_ops = {
 874         .get_tag_protocol       = qca8k_get_tag_protocol,
 875         .setup                  = qca8k_setup,
 876         .adjust_link            = qca8k_adjust_link,
 877         .get_strings            = qca8k_get_strings,
 878         .get_ethtool_stats      = qca8k_get_ethtool_stats,
 879         .get_sset_count         = qca8k_get_sset_count,
 880         .get_mac_eee            = qca8k_get_mac_eee,
 881         .set_mac_eee            = qca8k_set_mac_eee,
 882         .port_enable            = qca8k_port_enable,
 883         .port_disable           = qca8k_port_disable,
 884         .port_stp_state_set     = qca8k_port_stp_state_set,
 885         .port_bridge_join       = qca8k_port_bridge_join,
 886         .port_bridge_leave      = qca8k_port_bridge_leave,
 887         .port_fdb_add           = qca8k_port_fdb_add,
 888         .port_fdb_del           = qca8k_port_fdb_del,
 889         .port_fdb_dump          = qca8k_port_fdb_dump,
 890 };
 891
 892 static int
 893 qca8k_sw_probe(struct mdio_device *mdiodev)
 894 {
 895         struct qca8k_priv *priv;
 896         u32 id;
 897
 898         /* allocate the private data struct so that we can probe the switches
 899          * ID register
 900          */
 901         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
 902         if (!priv)
 903                 return -ENOMEM;
 904
 905         priv->bus = mdiodev->bus;
 906         priv->dev = &mdiodev->dev;
 907
 908         /* read the switches ID register */
 909         id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
 910         id >>= QCA8K_MASK_CTRL_ID_S;
 911         id &= QCA8K_MASK_CTRL_ID_M;
 912         if (id != QCA8K_ID_QCA8337)
 913                 return -ENODEV;
 914
 915         priv->ds = dsa_switch_alloc(&mdiodev->dev, QCA8K_NUM_PORTS);
 916         if (!priv->ds)
 917                 return -ENOMEM;
 918
 919         priv->ds->priv = priv;
 920         priv->ds->ops = &qca8k_switch_ops;
 921         mutex_init(&priv->reg_mutex);
 922         dev_set_drvdata(&mdiodev->dev, priv);
 923
 924         return dsa_register_switch(priv->ds);
 925 }
 926
 927 static void
 928 qca8k_sw_remove(struct mdio_device *mdiodev)
 929 {
 930         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
 931         int i;
 932
 933         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 934                 qca8k_port_set_status(priv, i, 0);
 935
 936         dsa_unregister_switch(priv->ds);
 937 }
 938
 939 #ifdef CONFIG_PM_SLEEP
 940 static void
 941 qca8k_set_pm(struct qca8k_priv *priv, int enable)
 942 {
 943         int i;
 944
 945         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 946                 if (!priv->port_sts[i].enabled)
 947                         continue;
 948
 949                 qca8k_port_set_status(priv, i, enable);
 950         }
 951 }
 952
 953 static int qca8k_suspend(struct device *dev)
 954 {
 955         struct platform_device *pdev = to_platform_device(dev);
 956         struct qca8k_priv *priv = platform_get_drvdata(pdev);
 957
 958         qca8k_set_pm(priv, 0);
 959
 960         return dsa_switch_suspend(priv->ds);
 961 }
 962
 963 static int qca8k_resume(struct device *dev)
 964 {
 965         struct platform_device *pdev = to_platform_device(dev);
 966         struct qca8k_priv *priv = platform_get_drvdata(pdev);
 967
 968         qca8k_set_pm(priv, 1);
 969
 970         return dsa_switch_resume(priv->ds);
 971 }
 972 #endif /* CONFIG_PM_SLEEP */
 973
 974 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
 975                          qca8k_suspend, qca8k_resume);
 976
 977 static const struct of_device_id qca8k_of_match[] = {
 978         { .compatible = "qca,qca8334" },
 979         { .compatible = "qca,qca8337" },
 980         { /* sentinel */ },
 981 };
 982
 983 static struct mdio_driver qca8kmdio_driver = {
 984         .probe  = qca8k_sw_probe,
 985         .remove = qca8k_sw_remove,
 986         .mdiodrv.driver = {
 987                 .name = "qca8k",
 988                 .of_match_table = qca8k_of_match,
 989                 .pm = &qca8k_pm_ops,
 990         },
 991 };
 992
 993 mdio_module_driver(qca8kmdio_driver);
 994
 995 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
 996 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
 997 MODULE_LICENSE("GPL v2");
 998 MODULE_ALIAS("platform:qca8k");