drivers/net/dsa/qca8k.c

   1 /*
   2  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   3  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   4  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   5  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 and
   9  * only version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/phy.h>
  19 #include <linux/netdevice.h>
  20 #include <net/dsa.h>
  21 #include <net/switchdev.h>
  22 #include <linux/of_net.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/if_bridge.h>
  25 #include <linux/mdio.h>
  26 #include <linux/etherdevice.h>
  27
  28 #include "qca8k.h"
  29
  30 #define MIB_DESC(_s, _o, _n)    \
  31         {                       \
  32                 .size = (_s),   \
  33                 .offset = (_o), \
  34                 .name = (_n),   \
  35         }
  36
  37 static const struct qca8k_mib_desc ar8327_mib[] = {
  38         MIB_DESC(1, 0x00, "RxBroad"),
  39         MIB_DESC(1, 0x04, "RxPause"),
  40         MIB_DESC(1, 0x08, "RxMulti"),
  41         MIB_DESC(1, 0x0c, "RxFcsErr"),
  42         MIB_DESC(1, 0x10, "RxAlignErr"),
  43         MIB_DESC(1, 0x14, "RxRunt"),
  44         MIB_DESC(1, 0x18, "RxFragment"),
  45         MIB_DESC(1, 0x1c, "Rx64Byte"),
  46         MIB_DESC(1, 0x20, "Rx128Byte"),
  47         MIB_DESC(1, 0x24, "Rx256Byte"),
  48         MIB_DESC(1, 0x28, "Rx512Byte"),
  49         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  50         MIB_DESC(1, 0x30, "Rx1518Byte"),
  51         MIB_DESC(1, 0x34, "RxMaxByte"),
  52         MIB_DESC(1, 0x38, "RxTooLong"),
  53         MIB_DESC(2, 0x3c, "RxGoodByte"),
  54         MIB_DESC(2, 0x44, "RxBadByte"),
  55         MIB_DESC(1, 0x4c, "RxOverFlow"),
  56         MIB_DESC(1, 0x50, "Filtered"),
  57         MIB_DESC(1, 0x54, "TxBroad"),
  58         MIB_DESC(1, 0x58, "TxPause"),
  59         MIB_DESC(1, 0x5c, "TxMulti"),
  60         MIB_DESC(1, 0x60, "TxUnderRun"),
  61         MIB_DESC(1, 0x64, "Tx64Byte"),
  62         MIB_DESC(1, 0x68, "Tx128Byte"),
  63         MIB_DESC(1, 0x6c, "Tx256Byte"),
  64         MIB_DESC(1, 0x70, "Tx512Byte"),
  65         MIB_DESC(1, 0x74, "Tx1024Byte"),
  66         MIB_DESC(1, 0x78, "Tx1518Byte"),
  67         MIB_DESC(1, 0x7c, "TxMaxByte"),
  68         MIB_DESC(1, 0x80, "TxOverSize"),
  69         MIB_DESC(2, 0x84, "TxByte"),
  70         MIB_DESC(1, 0x8c, "TxCollision"),
  71         MIB_DESC(1, 0x90, "TxAbortCol"),
  72         MIB_DESC(1, 0x94, "TxMultiCol"),
  73         MIB_DESC(1, 0x98, "TxSingleCol"),
  74         MIB_DESC(1, 0x9c, "TxExcDefer"),
  75         MIB_DESC(1, 0xa0, "TxDefer"),
  76         MIB_DESC(1, 0xa4, "TxLateCol"),
  77 };
  78
  79 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  80  * to set the page of the register. Track the last page that was set to reduce
  81  * mdio writes
  82  */
  83 static u16 qca8k_current_page = 0xffff;
  84
  85 static void
  86 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  87 {
  88         regaddr >>= 1;
  89         *r1 = regaddr & 0x1e;
  90
  91         regaddr >>= 5;
  92         *r2 = regaddr & 0x7;
  93
  94         regaddr >>= 3;
  95         *page = regaddr & 0x3ff;
  96 }
  97
  98 static u32
  99 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
 100 {
 101         u32 val;
 102         int ret;
 103
 104         ret = bus->read(bus, phy_id, regnum);
 105         if (ret >= 0) {
 106                 val = ret;
 107                 ret = bus->read(bus, phy_id, regnum + 1);
 108                 val |= ret << 16;
 109         }
 110
 111         if (ret < 0) {
 112                 dev_err_ratelimited(&bus->dev,
 113                                     "failed to read qca8k 32bit register\n");
 114                 return ret;
 115         }
 116
 117         return val;
 118 }
 119
 120 static void
 121 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 122 {
 123         u16 lo, hi;
 124         int ret;
 125
 126         lo = val & 0xffff;
 127         hi = (u16)(val >> 16);
 128
 129         ret = bus->write(bus, phy_id, regnum, lo);
 130         if (ret >= 0)
 131                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 132         if (ret < 0)
 133                 dev_err_ratelimited(&bus->dev,
 134                                     "failed to write qca8k 32bit register\n");
 135 }
 136
 137 static void
 138 qca8k_set_page(struct mii_bus *bus, u16 page)
 139 {
 140         if (page == qca8k_current_page)
 141                 return;
 142
 143         if (bus->write(bus, 0x18, 0, page) < 0)
 144                 dev_err_ratelimited(&bus->dev,
 145                                     "failed to set qca8k page\n");
 146         qca8k_current_page = page;
 147 }
 148
 149 static u32
 150 qca8k_read(struct qca8k_priv *priv, u32 reg)
 151 {
 152         u16 r1, r2, page;
 153         u32 val;
 154
 155         qca8k_split_addr(reg, &r1, &r2, &page);
 156
 157         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 158
 159         qca8k_set_page(priv->bus, page);
 160         val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 161
 162         mutex_unlock(&priv->bus->mdio_lock);
 163
 164         return val;
 165 }
 166
 167 static void
 168 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 169 {
 170         u16 r1, r2, page;
 171
 172         qca8k_split_addr(reg, &r1, &r2, &page);
 173
 174         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 175
 176         qca8k_set_page(priv->bus, page);
 177         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
 178
 179         mutex_unlock(&priv->bus->mdio_lock);
 180 }
 181
 182 static u32
 183 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
 184 {
 185         u16 r1, r2, page;
 186         u32 ret;
 187
 188         qca8k_split_addr(reg, &r1, &r2, &page);
 189
 190         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 191
 192         qca8k_set_page(priv->bus, page);
 193         ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 194         ret &= ~mask;
 195         ret |= val;
 196         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
 197
 198         mutex_unlock(&priv->bus->mdio_lock);
 199
 200         return ret;
 201 }
 202
 203 static void
 204 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 205 {
 206         qca8k_rmw(priv, reg, 0, val);
 207 }
 208
 209 static void
 210 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 211 {
 212         qca8k_rmw(priv, reg, val, 0);
 213 }
 214
 215 static int
 216 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 217 {
 218         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 219
 220         *val = qca8k_read(priv, reg);
 221
 222         return 0;
 223 }
 224
 225 static int
 226 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 227 {
 228         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 229
 230         qca8k_write(priv, reg, val);
 231
 232         return 0;
 233 }
 234
 235 static const struct regmap_range qca8k_readable_ranges[] = {
 236         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 237         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 238         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 239         regmap_reg_range(0x0400, 0x0454), /* ACL */
 240         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 241         regmap_reg_range(0x0800, 0x0b70), /* QM */
 242         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 243         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 244         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 245         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 246         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 247         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 248         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 249         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 250         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 251
 252 };
 253
 254 static struct regmap_access_table qca8k_readable_table = {
 255         .yes_ranges = qca8k_readable_ranges,
 256         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 257 };
 258
 259 static struct regmap_config qca8k_regmap_config = {
 260         .reg_bits = 16,
 261         .val_bits = 32,
 262         .reg_stride = 4,
 263         .max_register = 0x16ac, /* end MIB - Port6 range */
 264         .reg_read = qca8k_regmap_read,
 265         .reg_write = qca8k_regmap_write,
 266         .rd_table = &qca8k_readable_table,
 267 };
 268
 269 static int
 270 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 271 {
 272         unsigned long timeout;
 273
 274         timeout = jiffies + msecs_to_jiffies(20);
 275
 276         /* loop until the busy flag has cleared */
 277         do {
 278                 u32 val = qca8k_read(priv, reg);
 279                 int busy = val & mask;
 280
 281                 if (!busy)
 282                         break;
 283                 cond_resched();
 284         } while (!time_after_eq(jiffies, timeout));
 285
 286         return time_after_eq(jiffies, timeout);
 287 }
 288
 289 static void
 290 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 291 {
 292         u32 reg[4];
 293         int i;
 294
 295         /* load the ARL table into an array */
 296         for (i = 0; i < 4; i++)
 297                 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
 298
 299         /* vid - 83:72 */
 300         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 301         /* aging - 67:64 */
 302         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 303         /* portmask - 54:48 */
 304         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 305         /* mac - 47:0 */
 306         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 307         fdb->mac[1] = reg[1] & 0xff;
 308         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 309         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 310         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 311         fdb->mac[5] = reg[0] & 0xff;
 312 }
 313
 314 static void
 315 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 316                 u8 aging)
 317 {
 318         u32 reg[3] = { 0 };
 319         int i;
 320
 321         /* vid - 83:72 */
 322         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 323         /* aging - 67:64 */
 324         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 325         /* portmask - 54:48 */
 326         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 327         /* mac - 47:0 */
 328         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 329         reg[1] |= mac[1];
 330         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 331         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 332         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 333         reg[0] |= mac[5];
 334
 335         /* load the array into the ARL table */
 336         for (i = 0; i < 3; i++)
 337                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 338 }
 339
 340 static int
 341 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 342 {
 343         u32 reg;
 344
 345         /* Set the command and FDB index */
 346         reg = QCA8K_ATU_FUNC_BUSY;
 347         reg |= cmd;
 348         if (port >= 0) {
 349                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 350                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 351         }
 352
 353         /* Write the function register triggering the table access */
 354         qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 355
 356         /* wait for completion */
 357         if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
 358                 return -1;
 359
 360         /* Check for table full violation when adding an entry */
 361         if (cmd == QCA8K_FDB_LOAD) {
 362                 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
 363                 if (reg & QCA8K_ATU_FUNC_FULL)
 364                         return -1;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int
 371 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 372 {
 373         int ret;
 374
 375         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 376         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 377         if (ret >= 0)
 378                 qca8k_fdb_read(priv, fdb);
 379
 380         return ret;
 381 }
 382
 383 static int
 384 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 385               u16 vid, u8 aging)
 386 {
 387         int ret;
 388
 389         mutex_lock(&priv->reg_mutex);
 390         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 391         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 392         mutex_unlock(&priv->reg_mutex);
 393
 394         return ret;
 395 }
 396
 397 static int
 398 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 399 {
 400         int ret;
 401
 402         mutex_lock(&priv->reg_mutex);
 403         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 404         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 405         mutex_unlock(&priv->reg_mutex);
 406
 407         return ret;
 408 }
 409
 410 static void
 411 qca8k_fdb_flush(struct qca8k_priv *priv)
 412 {
 413         mutex_lock(&priv->reg_mutex);
 414         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 415         mutex_unlock(&priv->reg_mutex);
 416 }
 417
 418 static void
 419 qca8k_mib_init(struct qca8k_priv *priv)
 420 {
 421         mutex_lock(&priv->reg_mutex);
 422         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 423         qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 424         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 425         qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 426         mutex_unlock(&priv->reg_mutex);
 427 }
 428
 429 static int
 430 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 431 {
 432         u32 reg;
 433
 434         switch (port) {
 435         case 0:
 436                 reg = QCA8K_REG_PORT0_PAD_CTRL;
 437                 break;
 438         case 6:
 439                 reg = QCA8K_REG_PORT6_PAD_CTRL;
 440                 break;
 441         default:
 442                 pr_err("Can't set PAD_CTRL on port %d\n", port);
 443                 return -EINVAL;
 444         }
 445
 446         /* Configure a port to be directly connected to an external
 447          * PHY or MAC.
 448          */
 449         switch (mode) {
 450         case PHY_INTERFACE_MODE_RGMII:
 451                 qca8k_write(priv, reg,
 452                             QCA8K_PORT_PAD_RGMII_EN |
 453                             QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
 454                             QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
 455
 456                 /* According to the datasheet, RGMII delay is enabled through
 457                  * PORT5_PAD_CTRL for all ports, rather than individual port
 458                  * registers
 459                  */
 460                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 461                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 462                 break;
 463         case PHY_INTERFACE_MODE_RGMII_ID:
 464                 /* RGMII_ID needs internal delay. This is enabled through
 465                  * PORT5_PAD_CTRL for all ports, rather than individual port
 466                  * registers
 467                  */
 468                 qca8k_write(priv, reg,
 469                             QCA8K_PORT_PAD_RGMII_EN |
 470                             QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
 471                             QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
 472                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 473                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 474                 break;
 475         case PHY_INTERFACE_MODE_SGMII:
 476                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 477                 break;
 478         default:
 479                 pr_err("xMII mode %d not supported\n", mode);
 480                 return -EINVAL;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static void
 487 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 488 {
 489         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 490
 491         /* Port 0 and 6 have no internal PHY */
 492         if ((port > 0) && (port < 6))
 493                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 494
 495         if (enable)
 496                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 497         else
 498                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 499 }
 500
 501 static int
 502 qca8k_setup(struct dsa_switch *ds)
 503 {
 504         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 505         int ret, i, phy_mode = -1;
 506         u32 mask;
 507
 508         /* Make sure that port 0 is the cpu port */
 509         if (!dsa_is_cpu_port(ds, 0)) {
 510                 pr_err("port 0 is not the CPU port\n");
 511                 return -EINVAL;
 512         }
 513
 514         mutex_init(&priv->reg_mutex);
 515
 516         /* Start by setting up the register mapping */
 517         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
 518                                         &qca8k_regmap_config);
 519         if (IS_ERR(priv->regmap))
 520                 pr_warn("regmap initialization failed");
 521
 522         /* Initialize CPU port pad mode (xMII type, delays...) */
 523         phy_mode = of_get_phy_mode(ds->ports[ds->dst->cpu_port].dn);
 524         if (phy_mode < 0) {
 525                 pr_err("Can't find phy-mode for master device\n");
 526                 return phy_mode;
 527         }
 528         ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
 529         if (ret < 0)
 530                 return ret;
 531
 532         /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
 533         mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
 534                QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
 535         qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
 536         qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 537                       QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 538         qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
 539         priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
 540
 541         /* Enable MIB counters */
 542         qca8k_mib_init(priv);
 543
 544         /* Enable QCA header mode on the cpu port */
 545         qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
 546                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 547                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 548
 549         /* Disable forwarding by default on all ports */
 550         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 551                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 552                           QCA8K_PORT_LOOKUP_MEMBER, 0);
 553
 554         /* Disable MAC by default on all user ports */
 555         for (i = 1; i < QCA8K_NUM_PORTS; i++)
 556                 if (ds->enabled_port_mask & BIT(i))
 557                         qca8k_port_set_status(priv, i, 0);
 558
 559         /* Forward all unknown frames to CPU port for Linux processing */
 560         qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
 561                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
 562                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
 563                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
 564                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
 565
 566         /* Setup connection between CPU port & user ports */
 567         for (i = 0; i < DSA_MAX_PORTS; i++) {
 568                 /* CPU port gets connected to all user ports of the switch */
 569                 if (dsa_is_cpu_port(ds, i)) {
 570                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
 571                                   QCA8K_PORT_LOOKUP_MEMBER,
 572                                   ds->enabled_port_mask);
 573                 }
 574
 575                 /* Invividual user ports get connected to CPU port only */
 576                 if (ds->enabled_port_mask & BIT(i)) {
 577                         int shift = 16 * (i % 2);
 578
 579                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 580                                   QCA8K_PORT_LOOKUP_MEMBER,
 581                                   BIT(QCA8K_CPU_PORT));
 582
 583                         /* Enable ARP Auto-learning by default */
 584                         qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 585                                       QCA8K_PORT_LOOKUP_LEARN);
 586
 587                         /* For port based vlans to work we need to set the
 588                          * default egress vid
 589                          */
 590                         qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
 591                                   0xffff << shift, 1 << shift);
 592                         qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
 593                                     QCA8K_PORT_VLAN_CVID(1) |
 594                                     QCA8K_PORT_VLAN_SVID(1));
 595                 }
 596         }
 597
 598         /* Flush the FDB table */
 599         qca8k_fdb_flush(priv);
 600
 601         return 0;
 602 }
 603
 604 static void
 605 qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
 606 {
 607         struct qca8k_priv *priv = ds->priv;
 608         u32 reg;
 609
 610         /* Force fixed-link setting for CPU port, skip others. */
 611         if (!phy_is_pseudo_fixed_link(phy))
 612                 return;
 613
 614         /* Set port speed */
 615         switch (phy->speed) {
 616         case 10:
 617                 reg = QCA8K_PORT_STATUS_SPEED_10;
 618                 break;
 619         case 100:
 620                 reg = QCA8K_PORT_STATUS_SPEED_100;
 621                 break;
 622         case 1000:
 623                 reg = QCA8K_PORT_STATUS_SPEED_1000;
 624                 break;
 625         default:
 626                 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
 627                         port, phy->speed);
 628                 return;
 629         }
 630
 631         /* Set duplex mode */
 632         if (phy->duplex == DUPLEX_FULL)
 633                 reg |= QCA8K_PORT_STATUS_DUPLEX;
 634
 635         /* Force flow control */
 636         if (dsa_is_cpu_port(ds, port))
 637                 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
 638
 639         /* Force link down before changing MAC options */
 640         qca8k_port_set_status(priv, port, 0);
 641         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
 642         qca8k_port_set_status(priv, port, 1);
 643 }
 644
 645 static void
 646 qca8k_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 647 {
 648         int i;
 649
 650         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
 651                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
 652                         ETH_GSTRING_LEN);
 653 }
 654
 655 static void
 656 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
 657                         uint64_t *data)
 658 {
 659         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 660         const struct qca8k_mib_desc *mib;
 661         u32 reg, i;
 662         u64 hi;
 663
 664         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
 665                 mib = &ar8327_mib[i];
 666                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
 667
 668                 data[i] = qca8k_read(priv, reg);
 669                 if (mib->size == 2) {
 670                         hi = qca8k_read(priv, reg + 4);
 671                         data[i] |= hi << 32;
 672                 }
 673         }
 674 }
 675
 676 static int
 677 qca8k_get_sset_count(struct dsa_switch *ds)
 678 {
 679         return ARRAY_SIZE(ar8327_mib);
 680 }
 681
 682 static void
 683 qca8k_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
 684 {
 685         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 686         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
 687         u32 reg;
 688
 689         mutex_lock(&priv->reg_mutex);
 690         reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
 691         if (enable)
 692                 reg |= lpi_en;
 693         else
 694                 reg &= ~lpi_en;
 695         qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
 696         mutex_unlock(&priv->reg_mutex);
 697 }
 698
 699 static int
 700 qca8k_eee_init(struct dsa_switch *ds, int port,
 701                struct phy_device *phy)
 702 {
 703         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 704         struct ethtool_eee *p = &priv->port_sts[port].eee;
 705         int ret;
 706
 707         p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
 708
 709         ret = phy_init_eee(phy, 0);
 710         if (ret)
 711                 return ret;
 712
 713         qca8k_eee_enable_set(ds, port, true);
 714
 715         return 0;
 716 }
 717
 718 static int
 719 qca8k_set_eee(struct dsa_switch *ds, int port,
 720               struct phy_device *phydev,
 721               struct ethtool_eee *e)
 722 {
 723         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 724         struct ethtool_eee *p = &priv->port_sts[port].eee;
 725         int ret = 0;
 726
 727         p->eee_enabled = e->eee_enabled;
 728
 729         if (e->eee_enabled) {
 730                 p->eee_enabled = qca8k_eee_init(ds, port, phydev);
 731                 if (!p->eee_enabled)
 732                         ret = -EOPNOTSUPP;
 733         }
 734         qca8k_eee_enable_set(ds, port, p->eee_enabled);
 735
 736         return ret;
 737 }
 738
 739 static int
 740 qca8k_get_eee(struct dsa_switch *ds, int port,
 741               struct ethtool_eee *e)
 742 {
 743         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 744         struct ethtool_eee *p = &priv->port_sts[port].eee;
 745         struct net_device *netdev = ds->ports[port].netdev;
 746         int ret;
 747
 748         ret = phy_ethtool_get_eee(netdev->phydev, p);
 749         if (!ret)
 750                 e->eee_active =
 751                         !!(p->supported & p->advertised & p->lp_advertised);
 752         else
 753                 e->eee_active = 0;
 754
 755         e->eee_enabled = p->eee_enabled;
 756
 757         return ret;
 758 }
 759
 760 static void
 761 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
 762 {
 763         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 764         u32 stp_state;
 765
 766         switch (state) {
 767         case BR_STATE_DISABLED:
 768                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
 769                 break;
 770         case BR_STATE_BLOCKING:
 771                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
 772                 break;
 773         case BR_STATE_LISTENING:
 774                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
 775                 break;
 776         case BR_STATE_LEARNING:
 777                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
 778                 break;
 779         case BR_STATE_FORWARDING:
 780         default:
 781                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
 782                 break;
 783         }
 784
 785         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 786                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
 787 }
 788
 789 static int
 790 qca8k_port_bridge_join(struct dsa_switch *ds, int port,
 791                        struct net_device *bridge)
 792 {
 793         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 794         int port_mask = BIT(QCA8K_CPU_PORT);
 795         int i;
 796
 797         priv->port_sts[port].bridge_dev = bridge;
 798
 799         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 800                 if (priv->port_sts[i].bridge_dev != bridge)
 801                         continue;
 802                 /* Add this port to the portvlan mask of the other ports
 803                  * in the bridge
 804                  */
 805                 qca8k_reg_set(priv,
 806                               QCA8K_PORT_LOOKUP_CTRL(i),
 807                               BIT(port));
 808                 if (i != port)
 809                         port_mask |= BIT(i);
 810         }
 811         /* Add all other ports to this ports portvlan mask */
 812         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 813                   QCA8K_PORT_LOOKUP_MEMBER, port_mask);
 814
 815         return 0;
 816 }
 817
 818 static void
 819 qca8k_port_bridge_leave(struct dsa_switch *ds, int port)
 820 {
 821         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 822         int i;
 823
 824         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 825                 if (priv->port_sts[i].bridge_dev !=
 826                     priv->port_sts[port].bridge_dev)
 827                         continue;
 828                 /* Remove this port to the portvlan mask of the other ports
 829                  * in the bridge
 830                  */
 831                 qca8k_reg_clear(priv,
 832                                 QCA8K_PORT_LOOKUP_CTRL(i),
 833                                 BIT(port));
 834         }
 835         priv->port_sts[port].bridge_dev = NULL;
 836         /* Set the cpu port to be the only one in the portvlan mask of
 837          * this port
 838          */
 839         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
 840                   QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
 841 }
 842
 843 static int
 844 qca8k_port_enable(struct dsa_switch *ds, int port,
 845                   struct phy_device *phy)
 846 {
 847         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 848
 849         qca8k_port_set_status(priv, port, 1);
 850         priv->port_sts[port].enabled = 1;
 851
 852         return 0;
 853 }
 854
 855 static void
 856 qca8k_port_disable(struct dsa_switch *ds, int port,
 857                    struct phy_device *phy)
 858 {
 859         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 860
 861         qca8k_port_set_status(priv, port, 0);
 862         priv->port_sts[port].enabled = 0;
 863 }
 864
 865 static int
 866 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
 867                       u16 port_mask, u16 vid)
 868 {
 869         /* Set the vid to the port vlan id if no vid is set */
 870         if (!vid)
 871                 vid = 1;
 872
 873         return qca8k_fdb_add(priv, addr, port_mask, vid,
 874                              QCA8K_ATU_STATUS_STATIC);
 875 }
 876
 877 static int
 878 qca8k_port_fdb_prepare(struct dsa_switch *ds, int port,
 879                        const struct switchdev_obj_port_fdb *fdb,
 880                        struct switchdev_trans *trans)
 881 {
 882         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 883
 884         /* The FDB table for static and auto learned entries is the same. We
 885          * need to reserve an entry with no port_mask set to make sure that
 886          * when port_fdb_add is called an entry is still available. Otherwise
 887          * the last free entry might have been used up by auto learning
 888          */
 889         return qca8k_port_fdb_insert(priv, fdb->addr, 0, fdb->vid);
 890 }
 891
 892 static void
 893 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
 894                    const struct switchdev_obj_port_fdb *fdb,
 895                    struct switchdev_trans *trans)
 896 {
 897         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 898         u16 port_mask = BIT(port);
 899
 900         /* Update the FDB entry adding the port_mask */
 901         qca8k_port_fdb_insert(priv, fdb->addr, port_mask, fdb->vid);
 902 }
 903
 904 static int
 905 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
 906                    const struct switchdev_obj_port_fdb *fdb)
 907 {
 908         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 909         u16 port_mask = BIT(port);
 910         u16 vid = fdb->vid;
 911
 912         if (!vid)
 913                 vid = 1;
 914
 915         return qca8k_fdb_del(priv, fdb->addr, port_mask, vid);
 916 }
 917
 918 static int
 919 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
 920                     struct switchdev_obj_port_fdb *fdb,
 921                     int (*cb)(struct switchdev_obj *obj))
 922 {
 923         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 924         struct qca8k_fdb _fdb = { 0 };
 925         int cnt = QCA8K_NUM_FDB_RECORDS;
 926         int ret = 0;
 927
 928         mutex_lock(&priv->reg_mutex);
 929         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
 930                 if (!_fdb.aging)
 931                         break;
 932
 933                 ether_addr_copy(fdb->addr, _fdb.mac);
 934                 fdb->vid = _fdb.vid;
 935                 if (_fdb.aging == QCA8K_ATU_STATUS_STATIC)
 936                         fdb->ndm_state = NUD_NOARP;
 937                 else
 938                         fdb->ndm_state = NUD_REACHABLE;
 939
 940                 ret = cb(&fdb->obj);
 941                 if (ret)
 942                         break;
 943         }
 944         mutex_unlock(&priv->reg_mutex);
 945
 946         return 0;
 947 }
 948
 949 static enum dsa_tag_protocol
 950 qca8k_get_tag_protocol(struct dsa_switch *ds)
 951 {
 952         return DSA_TAG_PROTO_QCA;
 953 }
 954
 955 static struct dsa_switch_ops qca8k_switch_ops = {
 956         .get_tag_protocol       = qca8k_get_tag_protocol,
 957         .setup                  = qca8k_setup,
 958         .adjust_link            = qca8k_adjust_link,
 959         .get_strings            = qca8k_get_strings,
 960         .get_ethtool_stats      = qca8k_get_ethtool_stats,
 961         .get_sset_count         = qca8k_get_sset_count,
 962         .get_eee                = qca8k_get_eee,
 963         .set_eee                = qca8k_set_eee,
 964         .port_enable            = qca8k_port_enable,
 965         .port_disable           = qca8k_port_disable,
 966         .port_stp_state_set     = qca8k_port_stp_state_set,
 967         .port_bridge_join       = qca8k_port_bridge_join,
 968         .port_bridge_leave      = qca8k_port_bridge_leave,
 969         .port_fdb_prepare       = qca8k_port_fdb_prepare,
 970         .port_fdb_add           = qca8k_port_fdb_add,
 971         .port_fdb_del           = qca8k_port_fdb_del,
 972         .port_fdb_dump          = qca8k_port_fdb_dump,
 973 };
 974
 975 static int
 976 qca8k_sw_probe(struct mdio_device *mdiodev)
 977 {
 978         struct qca8k_priv *priv;
 979         u32 id;
 980
 981         /* allocate the private data struct so that we can probe the switches
 982          * ID register
 983          */
 984         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
 985         if (!priv)
 986                 return -ENOMEM;
 987
 988         priv->bus = mdiodev->bus;
 989         priv->dev = &mdiodev->dev;
 990
 991         /* read the switches ID register */
 992         id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
 993         id >>= QCA8K_MASK_CTRL_ID_S;
 994         id &= QCA8K_MASK_CTRL_ID_M;
 995         if (id != QCA8K_ID_QCA8337)
 996                 return -ENODEV;
 997
 998         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
 999         if (!priv->ds)
1000                 return -ENOMEM;
1001
1002         priv->ds->priv = priv;
1003         priv->ds->dev = &mdiodev->dev;
1004         priv->ds->ops = &qca8k_switch_ops;
1005         mutex_init(&priv->reg_mutex);
1006         dev_set_drvdata(&mdiodev->dev, priv);
1007
1008         return dsa_register_switch(priv->ds, priv->ds->dev->of_node);
1009 }
1010
1011 static void
1012 qca8k_sw_remove(struct mdio_device *mdiodev)
1013 {
1014         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1015         int i;
1016
1017         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1018                 qca8k_port_set_status(priv, i, 0);
1019
1020         dsa_unregister_switch(priv->ds);
1021 }
1022
1023 #ifdef CONFIG_PM_SLEEP
1024 static void
1025 qca8k_set_pm(struct qca8k_priv *priv, int enable)
1026 {
1027         int i;
1028
1029         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1030                 if (!priv->port_sts[i].enabled)
1031                         continue;
1032
1033                 qca8k_port_set_status(priv, i, enable);
1034         }
1035 }
1036
1037 static int qca8k_suspend(struct device *dev)
1038 {
1039         struct platform_device *pdev = to_platform_device(dev);
1040         struct qca8k_priv *priv = platform_get_drvdata(pdev);
1041
1042         qca8k_set_pm(priv, 0);
1043
1044         return dsa_switch_suspend(priv->ds);
1045 }
1046
1047 static int qca8k_resume(struct device *dev)
1048 {
1049         struct platform_device *pdev = to_platform_device(dev);
1050         struct qca8k_priv *priv = platform_get_drvdata(pdev);
1051
1052         qca8k_set_pm(priv, 1);
1053
1054         return dsa_switch_resume(priv->ds);
1055 }
1056 #endif /* CONFIG_PM_SLEEP */
1057
1058 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1059                          qca8k_suspend, qca8k_resume);
1060
1061 static const struct of_device_id qca8k_of_match[] = {
1062         { .compatible = "qca,qca8334" },
1063         { .compatible = "qca,qca8337" },
1064         { /* sentinel */ },
1065 };
1066
1067 static struct mdio_driver qca8kmdio_driver = {
1068         .probe  = qca8k_sw_probe,
1069         .remove = qca8k_sw_remove,
1070         .mdiodrv.driver = {
1071                 .name = "qca8k",
1072                 .of_match_table = qca8k_of_match,
1073                 .pm = &qca8k_pm_ops,
1074         },
1075 };
1076
1077 mdio_module_driver(qca8kmdio_driver);
1078
1079 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1080 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1081 MODULE_LICENSE("GPL v2");
1082 MODULE_ALIAS("platform:qca8k");