1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
9 #include <linux/phylink.h>
15 /* Definitions from drivers/net/phy/marvell.c, which would be good to reuse. */
16 #define MII_M1011_PHY_STATUS 17
17 #define MII_M1011_IMASK 18
18 #define MII_M1011_IMASK_LINK_CHANGE BIT(10)
19 #define MII_M1011_IEVENT 19
20 #define MII_M1011_IEVENT_LINK_CHANGE BIT(10)
21 #define MII_MARVELL_PHY_PAGE 22
22 #define MII_MARVELL_FIBER_PAGE 1
24 struct marvell_c22_pcs {
25 struct mdio_device mdio;
26 struct phylink_pcs phylink_pcs;
29 bool (*link_check)(struct marvell_c22_pcs *mpcs);
30 struct mv88e6xxx_port *port;
33 static struct marvell_c22_pcs *pcs_to_marvell_c22_pcs(struct phylink_pcs *pcs)
35 return container_of(pcs, struct marvell_c22_pcs, phylink_pcs);
38 static int marvell_c22_pcs_set_fiber_page(struct marvell_c22_pcs *mpcs)
43 mutex_lock(&mpcs->mdio.bus->mdio_lock);
45 err = __mdiodev_read(&mpcs->mdio, MII_MARVELL_PHY_PAGE);
47 dev_err(mpcs->mdio.dev.parent,
48 "%s: can't read Serdes page register: %pe\n",
49 mpcs->name, ERR_PTR(err));
55 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE,
56 MII_MARVELL_FIBER_PAGE);
58 dev_err(mpcs->mdio.dev.parent,
59 "%s: can't set Serdes page register: %pe\n",
60 mpcs->name, ERR_PTR(err));
67 static int marvell_c22_pcs_restore_page(struct marvell_c22_pcs *mpcs,
73 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE,
76 dev_err(mpcs->mdio.dev.parent,
77 "%s: can't restore Serdes page register: %pe\n",
78 mpcs->name, ERR_PTR(err));
84 mutex_unlock(&mpcs->mdio.bus->mdio_lock);
89 static irqreturn_t marvell_c22_pcs_handle_irq(int irq, void *dev_id)
91 struct marvell_c22_pcs *mpcs = dev_id;
92 irqreturn_t status = IRQ_NONE;
95 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);
99 err = __mdiodev_read(&mpcs->mdio, MII_M1011_IEVENT);
100 if (err >= 0 && err & MII_M1011_IEVENT_LINK_CHANGE) {
101 phylink_pcs_change(&mpcs->phylink_pcs, true);
102 status = IRQ_HANDLED;
106 marvell_c22_pcs_restore_page(mpcs, oldpage, 0);
111 static int marvell_c22_pcs_modify(struct marvell_c22_pcs *mpcs, u8 reg,
114 int oldpage, err = 0;
116 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);
118 err = __mdiodev_modify(&mpcs->mdio, reg, mask, val);
120 return marvell_c22_pcs_restore_page(mpcs, oldpage, err);
123 static int marvell_c22_pcs_power(struct marvell_c22_pcs *mpcs,
126 u16 val = on ? 0 : BMCR_PDOWN;
128 return marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_PDOWN, val);
131 static int marvell_c22_pcs_control_irq(struct marvell_c22_pcs *mpcs,
134 u16 val = enable ? MII_M1011_IMASK_LINK_CHANGE : 0;
136 return marvell_c22_pcs_modify(mpcs, MII_M1011_IMASK,
137 MII_M1011_IMASK_LINK_CHANGE, val);
140 static int marvell_c22_pcs_enable(struct phylink_pcs *pcs)
142 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
145 err = marvell_c22_pcs_power(mpcs, true);
149 return marvell_c22_pcs_control_irq(mpcs, !!mpcs->irq);
152 static void marvell_c22_pcs_disable(struct phylink_pcs *pcs)
154 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
156 marvell_c22_pcs_control_irq(mpcs, false);
157 marvell_c22_pcs_power(mpcs, false);
160 static void marvell_c22_pcs_get_state(struct phylink_pcs *pcs,
161 struct phylink_link_state *state)
163 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
164 int oldpage, bmsr, lpa, status;
168 if (mpcs->link_check && !mpcs->link_check(mpcs))
171 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);
173 bmsr = __mdiodev_read(&mpcs->mdio, MII_BMSR);
174 lpa = __mdiodev_read(&mpcs->mdio, MII_LPA);
175 status = __mdiodev_read(&mpcs->mdio, MII_M1011_PHY_STATUS);
178 if (marvell_c22_pcs_restore_page(mpcs, oldpage, 0) >= 0 &&
179 bmsr >= 0 && lpa >= 0 && status >= 0)
180 mv88e6xxx_pcs_decode_state(mpcs->mdio.dev.parent, bmsr, lpa,
184 static int marvell_c22_pcs_config(struct phylink_pcs *pcs,
185 unsigned int neg_mode,
186 phy_interface_t interface,
187 const unsigned long *advertising,
188 bool permit_pause_to_mac)
190 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
191 int oldpage, adv, err, ret = 0;
194 adv = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);
198 bmcr = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : 0;
200 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);
204 err = __mdiodev_modify_changed(&mpcs->mdio, MII_ADVERTISE, 0xffff, adv);
209 err = __mdiodev_modify_changed(&mpcs->mdio, MII_BMCR, BMCR_ANENABLE,
216 /* If the ANENABLE bit was changed, the PHY will restart negotiation,
217 * so we don't need to flag a change to trigger its own restart.
223 return marvell_c22_pcs_restore_page(mpcs, oldpage, ret);
226 static void marvell_c22_pcs_an_restart(struct phylink_pcs *pcs)
228 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
230 marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART);
233 static void marvell_c22_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
234 phy_interface_t interface, int speed,
237 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);
241 if (phylink_autoneg_inband(mode))
244 bmcr = mii_bmcr_encode_fixed(speed, duplex);
246 err = marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_SPEED100 |
247 BMCR_FULLDPLX | BMCR_SPEED1000, bmcr);
249 dev_err(mpcs->mdio.dev.parent,
250 "%s: failed to configure mpcs: %pe\n", mpcs->name,
254 static const struct phylink_pcs_ops marvell_c22_pcs_ops = {
255 .pcs_enable = marvell_c22_pcs_enable,
256 .pcs_disable = marvell_c22_pcs_disable,
257 .pcs_get_state = marvell_c22_pcs_get_state,
258 .pcs_config = marvell_c22_pcs_config,
259 .pcs_an_restart = marvell_c22_pcs_an_restart,
260 .pcs_link_up = marvell_c22_pcs_link_up,
263 static struct marvell_c22_pcs *marvell_c22_pcs_alloc(struct device *dev,
267 struct marvell_c22_pcs *mpcs;
269 mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
273 mpcs->mdio.dev.parent = dev;
274 mpcs->mdio.bus = bus;
275 mpcs->mdio.addr = addr;
276 mpcs->phylink_pcs.ops = &marvell_c22_pcs_ops;
277 mpcs->phylink_pcs.neg_mode = true;
282 static int marvell_c22_pcs_setup_irq(struct marvell_c22_pcs *mpcs,
287 mpcs->phylink_pcs.poll = !irq;
291 err = request_threaded_irq(irq, NULL,
292 marvell_c22_pcs_handle_irq,
293 IRQF_ONESHOT, mpcs->name, mpcs);
301 /* mv88e6352 specifics */
303 static bool mv88e6352_pcs_link_check(struct marvell_c22_pcs *mpcs)
305 struct mv88e6xxx_port *port = mpcs->port;
306 struct mv88e6xxx_chip *chip = port->chip;
309 /* Port 4 can be in auto-media mode. Check that the port is
310 * associated with the mpcs.
312 mv88e6xxx_reg_lock(chip);
313 chip->info->ops->port_get_cmode(chip, port->port, &cmode);
314 mv88e6xxx_reg_unlock(chip);
316 return cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX ||
317 cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
318 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII;
321 static int mv88e6352_pcs_init(struct mv88e6xxx_chip *chip, int port)
323 struct marvell_c22_pcs *mpcs;
329 mv88e6xxx_reg_lock(chip);
330 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
331 mv88e6xxx_reg_unlock(chip);
335 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
336 bus = mv88e6xxx_default_mdio_bus(chip);
339 mpcs = marvell_c22_pcs_alloc(dev, bus, MV88E6352_ADDR_SERDES);
343 snprintf(mpcs->name, sizeof(mpcs->name),
344 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);
346 mpcs->link_check = mv88e6352_pcs_link_check;
347 mpcs->port = &chip->ports[port];
349 err = marvell_c22_pcs_setup_irq(mpcs, irq);
355 chip->ports[port].pcs_private = &mpcs->phylink_pcs;
360 static void mv88e6352_pcs_teardown(struct mv88e6xxx_chip *chip, int port)
362 struct marvell_c22_pcs *mpcs;
363 struct phylink_pcs *pcs;
365 pcs = chip->ports[port].pcs_private;
369 mpcs = pcs_to_marvell_c22_pcs(pcs);
372 free_irq(mpcs->irq, mpcs);
376 chip->ports[port].pcs_private = NULL;
379 static struct phylink_pcs *mv88e6352_pcs_select(struct mv88e6xxx_chip *chip,
381 phy_interface_t interface)
383 return chip->ports[port].pcs_private;
386 const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops = {
387 .pcs_init = mv88e6352_pcs_init,
388 .pcs_teardown = mv88e6352_pcs_teardown,
389 .pcs_select = mv88e6352_pcs_select,