2 * Marvell 88E6xxx Switch Global 2 Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqdomain.h>
20 #include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
23 static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
25 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
28 static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
30 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
33 static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
35 return mv88e6xxx_update(chip, chip->info->global2_addr, reg, update);
38 static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
40 return mv88e6xxx_wait(chip, chip->info->global2_addr, reg, mask);
43 /* Offset 0x00: Interrupt Source Register */
45 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
47 /* Read (and clear most of) the Interrupt Source bits */
48 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
51 /* Offset 0x01: Interrupt Mask Register */
53 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
55 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
58 /* Offset 0x02: Management Enable 2x */
60 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
62 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
65 /* Offset 0x03: Management Enable 0x */
67 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
69 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
72 /* Offset 0x05: Switch Management Register */
74 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
80 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
85 val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
87 val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
89 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
92 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
96 /* Consider the frames with reserved multicast destination
97 * addresses matching 01:80:c2:00:00:0x as MGMT.
99 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
103 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
106 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
110 /* Consider the frames with reserved multicast destination
111 * addresses matching 01:80:c2:00:00:2x as MGMT.
113 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
117 return mv88e6185_g2_mgmt_rsvd2cpu(chip);
120 /* Offset 0x06: Device Mapping Table register */
122 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
123 int target, int port)
125 u16 val = (target << 8) | (port & 0xf);
127 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val);
130 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
135 /* Initialize the routing port to the 32 possible target devices */
136 for (target = 0; target < 32; ++target) {
139 if (target < DSA_MAX_SWITCHES) {
140 port = chip->ds->rtable[target];
141 if (port == DSA_RTABLE_NONE)
145 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
153 /* Offset 0x07: Trunk Mask Table register */
155 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
158 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
161 val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
163 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val);
166 /* Offset 0x08: Trunk Mapping Table register */
168 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
171 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
172 u16 val = (id << 11) | (map & port_mask);
174 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val);
177 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
179 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
182 /* Clear all eight possible Trunk Mask vectors */
183 for (i = 0; i < 8; ++i) {
184 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
189 /* Clear all sixteen possible Trunk ID routing vectors */
190 for (i = 0; i < 16; ++i) {
191 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
199 /* Offset 0x09: Ingress Rate Command register
200 * Offset 0x0A: Ingress Rate Data register
203 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
205 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD,
206 MV88E6XXX_G2_IRL_CMD_BUSY);
209 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
214 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
215 MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
220 return mv88e6xxx_g2_irl_wait(chip);
223 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
225 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
229 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
231 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
235 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
236 * Offset 0x0C: Cross-chip Port VLAN Data Register
239 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
241 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR,
242 MV88E6XXX_G2_PVT_ADDR_BUSY);
245 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
246 int src_port, u16 op)
250 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
251 * cleared, source device is 5-bit, source port is 4-bit.
253 op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
254 op |= (src_dev & 0x1f) << 4;
255 op |= (src_port & 0xf);
257 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
261 return mv88e6xxx_g2_pvt_op_wait(chip);
264 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
265 int src_port, u16 data)
269 err = mv88e6xxx_g2_pvt_op_wait(chip);
273 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
277 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
278 MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
281 /* Offset 0x0D: Switch MAC/WoL/WoF register */
283 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
284 unsigned int pointer, u8 data)
286 u16 val = (pointer << 8) | data;
288 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val);
291 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
295 for (i = 0; i < 6; i++) {
296 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
304 /* Offset 0x0F: Priority Override Table */
306 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
309 u16 val = (pointer << 8) | (data & 0x7);
311 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
314 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
318 /* Clear all sixteen possible Priority Override entries */
319 for (i = 0; i < 16; i++) {
320 err = mv88e6xxx_g2_pot_write(chip, i, 0);
328 /* Offset 0x14: EEPROM Command
329 * Offset 0x15: EEPROM Data (for 16-bit data access)
330 * Offset 0x15: EEPROM Addr (for 8-bit data access)
333 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
335 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD,
336 MV88E6XXX_G2_EEPROM_CMD_BUSY |
337 MV88E6XXX_G2_EEPROM_CMD_RUNNING);
340 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
344 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
345 MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
349 return mv88e6xxx_g2_eeprom_wait(chip);
352 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
355 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
358 err = mv88e6xxx_g2_eeprom_wait(chip);
362 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
366 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
370 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
379 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
382 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
383 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
386 err = mv88e6xxx_g2_eeprom_wait(chip);
390 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
394 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
397 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
400 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
403 err = mv88e6xxx_g2_eeprom_wait(chip);
407 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
411 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
414 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
417 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
420 err = mv88e6xxx_g2_eeprom_wait(chip);
424 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
428 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
431 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
432 struct ethtool_eeprom *eeprom, u8 *data)
434 unsigned int offset = eeprom->offset;
435 unsigned int len = eeprom->len;
441 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
454 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
455 struct ethtool_eeprom *eeprom, u8 *data)
457 unsigned int offset = eeprom->offset;
458 unsigned int len = eeprom->len;
464 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
477 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
478 struct ethtool_eeprom *eeprom, u8 *data)
480 unsigned int offset = eeprom->offset;
481 unsigned int len = eeprom->len;
488 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
492 *data++ = (val >> 8) & 0xff;
500 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
504 *data++ = val & 0xff;
505 *data++ = (val >> 8) & 0xff;
513 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
517 *data++ = val & 0xff;
527 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
528 struct ethtool_eeprom *eeprom, u8 *data)
530 unsigned int offset = eeprom->offset;
531 unsigned int len = eeprom->len;
535 /* Ensure the RO WriteEn bit is set */
536 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
540 if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
546 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
550 val = (*data++ << 8) | (val & 0xff);
552 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
565 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
575 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
579 val = (val & 0xff00) | *data++;
581 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
593 /* Offset 0x18: SMI PHY Command Register
594 * Offset 0x19: SMI PHY Data Register
597 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
599 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD,
600 MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
603 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
607 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
608 MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
612 return mv88e6xxx_g2_smi_phy_wait(chip);
615 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
616 bool external, bool c45, u16 op, int dev,
622 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
624 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */
627 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */
629 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
631 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
632 cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
633 cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
635 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
638 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
639 bool external, u16 op, int dev,
642 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
645 /* IEEE 802.3 Clause 22 Read Data Register */
646 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
647 bool external, int dev, int reg,
650 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
653 err = mv88e6xxx_g2_smi_phy_wait(chip);
657 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
661 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
664 /* IEEE 802.3 Clause 22 Write Data Register */
665 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
666 bool external, int dev, int reg,
669 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
672 err = mv88e6xxx_g2_smi_phy_wait(chip);
676 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
680 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
683 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
684 bool external, u16 op, int port,
687 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
690 /* IEEE 802.3 Clause 45 Write Address Register */
691 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
692 bool external, int port, int dev,
695 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
698 err = mv88e6xxx_g2_smi_phy_wait(chip);
702 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
706 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
709 /* IEEE 802.3 Clause 45 Read Data Register */
710 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
711 bool external, int port, int dev,
714 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
717 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
721 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
724 static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
725 bool external, int port, int reg,
728 int dev = (reg >> 16) & 0x1f;
729 int addr = reg & 0xffff;
732 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
737 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
741 /* IEEE 802.3 Clause 45 Write Data Register */
742 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
743 bool external, int port, int dev,
746 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
749 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
753 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
756 static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
757 bool external, int port, int reg,
760 int dev = (reg >> 16) & 0x1f;
761 int addr = reg & 0xffff;
764 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
769 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
773 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
774 int addr, int reg, u16 *val)
776 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
777 bool external = mdio_bus->external;
779 if (reg & MII_ADDR_C45)
780 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
783 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
787 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
788 int addr, int reg, u16 val)
790 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
791 bool external = mdio_bus->external;
793 if (reg & MII_ADDR_C45)
794 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
797 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
801 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
805 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
807 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
812 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
816 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
818 reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
819 MV88E6352_G2_WDOG_CTL_QC_ENABLE);
821 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
824 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
826 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
827 MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
828 MV88E6352_G2_WDOG_CTL_QC_ENABLE |
829 MV88E6352_G2_WDOG_CTL_SWRESET);
832 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
833 .irq_action = mv88e6097_watchdog_action,
834 .irq_setup = mv88e6097_watchdog_setup,
835 .irq_free = mv88e6097_watchdog_free,
838 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
840 return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
841 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
842 MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
843 MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
844 MV88E6390_G2_WDOG_CTL_EGRESS |
845 MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
848 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
853 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
854 MV88E6390_G2_WDOG_CTL_PTR_EVENT);
855 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
857 dev_info(chip->dev, "Watchdog event: 0x%04x",
858 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
860 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
861 MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
862 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
864 dev_info(chip->dev, "Watchdog history: 0x%04x",
865 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
867 /* Trigger a software reset to try to recover the switch */
868 if (chip->info->ops->reset)
869 chip->info->ops->reset(chip);
871 mv88e6390_watchdog_setup(chip);
876 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
878 mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
879 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
882 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
883 .irq_action = mv88e6390_watchdog_action,
884 .irq_setup = mv88e6390_watchdog_setup,
885 .irq_free = mv88e6390_watchdog_free,
888 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
890 struct mv88e6xxx_chip *chip = dev_id;
891 irqreturn_t ret = IRQ_NONE;
893 mutex_lock(&chip->reg_lock);
894 if (chip->info->ops->watchdog_ops->irq_action)
895 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
896 mutex_unlock(&chip->reg_lock);
901 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
903 mutex_lock(&chip->reg_lock);
904 if (chip->info->ops->watchdog_ops->irq_free)
905 chip->info->ops->watchdog_ops->irq_free(chip);
906 mutex_unlock(&chip->reg_lock);
908 free_irq(chip->watchdog_irq, chip);
909 irq_dispose_mapping(chip->watchdog_irq);
912 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
916 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
917 MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
918 if (chip->watchdog_irq < 0)
919 return chip->watchdog_irq;
921 err = request_threaded_irq(chip->watchdog_irq, NULL,
922 mv88e6xxx_g2_watchdog_thread_fn,
923 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
924 "mv88e6xxx-watchdog", chip);
928 mutex_lock(&chip->reg_lock);
929 if (chip->info->ops->watchdog_ops->irq_setup)
930 err = chip->info->ops->watchdog_ops->irq_setup(chip);
931 mutex_unlock(&chip->reg_lock);
936 /* Offset 0x1D: Misc Register */
938 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
944 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
949 val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
951 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
953 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
956 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
958 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
961 static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
963 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
964 unsigned int n = d->hwirq;
966 chip->g2_irq.masked |= (1 << n);
969 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
971 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
972 unsigned int n = d->hwirq;
974 chip->g2_irq.masked &= ~(1 << n);
977 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
979 struct mv88e6xxx_chip *chip = dev_id;
980 unsigned int nhandled = 0;
981 unsigned int sub_irq;
986 mutex_lock(&chip->reg_lock);
987 err = mv88e6xxx_g2_int_source(chip, ®);
988 mutex_unlock(&chip->reg_lock);
992 for (n = 0; n < 16; ++n) {
993 if (reg & (1 << n)) {
994 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
995 handle_nested_irq(sub_irq);
1000 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1003 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
1005 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1007 mutex_lock(&chip->reg_lock);
1010 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
1012 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1015 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1017 dev_err(chip->dev, "failed to mask interrupts\n");
1019 mutex_unlock(&chip->reg_lock);
1022 static const struct irq_chip mv88e6xxx_g2_irq_chip = {
1023 .name = "mv88e6xxx-g2",
1024 .irq_mask = mv88e6xxx_g2_irq_mask,
1025 .irq_unmask = mv88e6xxx_g2_irq_unmask,
1026 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
1027 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
1030 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
1032 irq_hw_number_t hwirq)
1034 struct mv88e6xxx_chip *chip = d->host_data;
1036 irq_set_chip_data(irq, d->host_data);
1037 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1038 irq_set_noprobe(irq);
1043 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
1044 .map = mv88e6xxx_g2_irq_domain_map,
1045 .xlate = irq_domain_xlate_twocell,
1048 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1052 mv88e6xxx_g2_watchdog_free(chip);
1054 free_irq(chip->device_irq, chip);
1055 irq_dispose_mapping(chip->device_irq);
1057 for (irq = 0; irq < 16; irq++) {
1058 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1059 irq_dispose_mapping(virq);
1062 irq_domain_remove(chip->g2_irq.domain);
1065 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1069 if (!chip->dev->of_node)
1072 chip->g2_irq.domain = irq_domain_add_simple(
1073 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1074 if (!chip->g2_irq.domain)
1077 for (irq = 0; irq < 16; irq++)
1078 irq_create_mapping(chip->g2_irq.domain, irq);
1080 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1081 chip->g2_irq.masked = ~0;
1083 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1084 MV88E6XXX_G1_STS_IRQ_DEVICE);
1085 if (chip->device_irq < 0) {
1086 err = chip->device_irq;
1090 err = request_threaded_irq(chip->device_irq, NULL,
1091 mv88e6xxx_g2_irq_thread_fn,
1092 IRQF_ONESHOT, "mv88e6xxx-g1", chip);
1096 return mv88e6xxx_g2_watchdog_setup(chip);
1099 for (irq = 0; irq < 16; irq++) {
1100 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1101 irq_dispose_mapping(virq);
1104 irq_domain_remove(chip->g2_irq.domain);
1109 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
1114 /* Ignore removed tag data on doubly tagged packets, disable
1115 * flow control messages, force flow control priority to the
1116 * highest, and send all special multicast frames to the CPU
1117 * port at the highest priority.
1119 reg = MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI | (0x7 << 4);
1120 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, reg);
1124 /* Program the DSA routing table. */
1125 err = mv88e6xxx_g2_set_device_mapping(chip);
1129 /* Clear all trunk masks and mapping. */
1130 err = mv88e6xxx_g2_clear_trunk(chip);