2 * Marvell 88E6xxx Switch Global 2 Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqdomain.h>
20 #include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
23 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
25 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
28 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
30 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
33 int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
35 return mv88e6xxx_update(chip, chip->info->global2_addr, reg, update);
38 int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
40 return mv88e6xxx_wait(chip, chip->info->global2_addr, reg, mask);
43 /* Offset 0x00: Interrupt Source Register */
45 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
47 /* Read (and clear most of) the Interrupt Source bits */
48 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
51 /* Offset 0x01: Interrupt Mask Register */
53 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
55 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
58 /* Offset 0x02: Management Enable 2x */
60 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
62 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
65 /* Offset 0x03: Management Enable 0x */
67 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
69 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
72 /* Offset 0x05: Switch Management Register */
74 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
80 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
85 val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
87 val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
89 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
92 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
96 /* Consider the frames with reserved multicast destination
97 * addresses matching 01:80:c2:00:00:0x as MGMT.
99 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
103 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
106 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
110 /* Consider the frames with reserved multicast destination
111 * addresses matching 01:80:c2:00:00:2x as MGMT.
113 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
117 return mv88e6185_g2_mgmt_rsvd2cpu(chip);
120 /* Offset 0x06: Device Mapping Table register */
122 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
125 u16 val = (target << 8) | (port & 0x1f);
126 /* Modern chips use 5 bits to define a device mapping port,
127 * but bit 4 is reserved on older chips, so it is safe to use.
130 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val);
133 /* Offset 0x07: Trunk Mask Table register */
135 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
138 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
141 val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
143 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val);
146 /* Offset 0x08: Trunk Mapping Table register */
148 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
151 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
152 u16 val = (id << 11) | (map & port_mask);
154 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val);
157 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
159 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
162 /* Clear all eight possible Trunk Mask vectors */
163 for (i = 0; i < 8; ++i) {
164 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
169 /* Clear all sixteen possible Trunk ID routing vectors */
170 for (i = 0; i < 16; ++i) {
171 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
179 /* Offset 0x09: Ingress Rate Command register
180 * Offset 0x0A: Ingress Rate Data register
183 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
185 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD,
186 MV88E6XXX_G2_IRL_CMD_BUSY);
189 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
194 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
195 MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
200 return mv88e6xxx_g2_irl_wait(chip);
203 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
205 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
209 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
211 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
215 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
216 * Offset 0x0C: Cross-chip Port VLAN Data Register
219 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
221 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR,
222 MV88E6XXX_G2_PVT_ADDR_BUSY);
225 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
226 int src_port, u16 op)
230 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
231 * cleared, source device is 5-bit, source port is 4-bit.
233 op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
234 op |= (src_dev & 0x1f) << 4;
235 op |= (src_port & 0xf);
237 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
241 return mv88e6xxx_g2_pvt_op_wait(chip);
244 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
245 int src_port, u16 data)
249 err = mv88e6xxx_g2_pvt_op_wait(chip);
253 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
257 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
258 MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
261 /* Offset 0x0D: Switch MAC/WoL/WoF register */
263 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
264 unsigned int pointer, u8 data)
266 u16 val = (pointer << 8) | data;
268 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val);
271 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
275 for (i = 0; i < 6; i++) {
276 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
284 /* Offset 0x0F: Priority Override Table */
286 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
289 u16 val = (pointer << 8) | (data & 0x7);
291 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
294 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
298 /* Clear all sixteen possible Priority Override entries */
299 for (i = 0; i < 16; i++) {
300 err = mv88e6xxx_g2_pot_write(chip, i, 0);
308 /* Offset 0x14: EEPROM Command
309 * Offset 0x15: EEPROM Data (for 16-bit data access)
310 * Offset 0x15: EEPROM Addr (for 8-bit data access)
313 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
315 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD,
316 MV88E6XXX_G2_EEPROM_CMD_BUSY |
317 MV88E6XXX_G2_EEPROM_CMD_RUNNING);
320 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
324 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
325 MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
329 return mv88e6xxx_g2_eeprom_wait(chip);
332 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
335 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
338 err = mv88e6xxx_g2_eeprom_wait(chip);
342 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
346 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
350 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
359 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
362 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
363 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
366 err = mv88e6xxx_g2_eeprom_wait(chip);
370 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
374 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
377 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
380 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
383 err = mv88e6xxx_g2_eeprom_wait(chip);
387 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
391 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
394 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
397 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
400 err = mv88e6xxx_g2_eeprom_wait(chip);
404 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
408 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
411 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
412 struct ethtool_eeprom *eeprom, u8 *data)
414 unsigned int offset = eeprom->offset;
415 unsigned int len = eeprom->len;
421 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
434 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
435 struct ethtool_eeprom *eeprom, u8 *data)
437 unsigned int offset = eeprom->offset;
438 unsigned int len = eeprom->len;
444 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
457 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
458 struct ethtool_eeprom *eeprom, u8 *data)
460 unsigned int offset = eeprom->offset;
461 unsigned int len = eeprom->len;
468 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
472 *data++ = (val >> 8) & 0xff;
480 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
484 *data++ = val & 0xff;
485 *data++ = (val >> 8) & 0xff;
493 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
497 *data++ = val & 0xff;
507 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
508 struct ethtool_eeprom *eeprom, u8 *data)
510 unsigned int offset = eeprom->offset;
511 unsigned int len = eeprom->len;
515 /* Ensure the RO WriteEn bit is set */
516 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
520 if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
526 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
530 val = (*data++ << 8) | (val & 0xff);
532 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
545 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
555 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
559 val = (val & 0xff00) | *data++;
561 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
573 /* Offset 0x18: SMI PHY Command Register
574 * Offset 0x19: SMI PHY Data Register
577 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
579 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD,
580 MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
583 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
587 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
588 MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
592 return mv88e6xxx_g2_smi_phy_wait(chip);
595 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
596 bool external, bool c45, u16 op, int dev,
602 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
604 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */
607 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */
609 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
611 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
612 cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
613 cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
615 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
618 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
619 bool external, u16 op, int dev,
622 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
625 /* IEEE 802.3 Clause 22 Read Data Register */
626 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
627 bool external, int dev, int reg,
630 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
633 err = mv88e6xxx_g2_smi_phy_wait(chip);
637 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
641 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
644 /* IEEE 802.3 Clause 22 Write Data Register */
645 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
646 bool external, int dev, int reg,
649 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
652 err = mv88e6xxx_g2_smi_phy_wait(chip);
656 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
660 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
663 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
664 bool external, u16 op, int port,
667 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
670 /* IEEE 802.3 Clause 45 Write Address Register */
671 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
672 bool external, int port, int dev,
675 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
678 err = mv88e6xxx_g2_smi_phy_wait(chip);
682 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
686 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
689 /* IEEE 802.3 Clause 45 Read Data Register */
690 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
691 bool external, int port, int dev,
694 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
697 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
701 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
704 static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
705 bool external, int port, int reg,
708 int dev = (reg >> 16) & 0x1f;
709 int addr = reg & 0xffff;
712 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
717 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
721 /* IEEE 802.3 Clause 45 Write Data Register */
722 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
723 bool external, int port, int dev,
726 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
729 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
733 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
736 static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
737 bool external, int port, int reg,
740 int dev = (reg >> 16) & 0x1f;
741 int addr = reg & 0xffff;
744 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
749 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
753 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
754 int addr, int reg, u16 *val)
756 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
757 bool external = mdio_bus->external;
759 if (reg & MII_ADDR_C45)
760 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
763 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
767 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
768 int addr, int reg, u16 val)
770 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
771 bool external = mdio_bus->external;
773 if (reg & MII_ADDR_C45)
774 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
777 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
781 /* Offset 0x1B: Watchdog Control */
782 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
786 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
788 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
793 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
797 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
799 reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
800 MV88E6352_G2_WDOG_CTL_QC_ENABLE);
802 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
805 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
807 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
808 MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
809 MV88E6352_G2_WDOG_CTL_QC_ENABLE |
810 MV88E6352_G2_WDOG_CTL_SWRESET);
813 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
814 .irq_action = mv88e6097_watchdog_action,
815 .irq_setup = mv88e6097_watchdog_setup,
816 .irq_free = mv88e6097_watchdog_free,
819 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
821 return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
822 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
823 MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
824 MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
825 MV88E6390_G2_WDOG_CTL_EGRESS |
826 MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
829 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
834 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
835 MV88E6390_G2_WDOG_CTL_PTR_EVENT);
836 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
838 dev_info(chip->dev, "Watchdog event: 0x%04x",
839 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
841 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
842 MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
843 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
845 dev_info(chip->dev, "Watchdog history: 0x%04x",
846 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
848 /* Trigger a software reset to try to recover the switch */
849 if (chip->info->ops->reset)
850 chip->info->ops->reset(chip);
852 mv88e6390_watchdog_setup(chip);
857 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
859 mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
860 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
863 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
864 .irq_action = mv88e6390_watchdog_action,
865 .irq_setup = mv88e6390_watchdog_setup,
866 .irq_free = mv88e6390_watchdog_free,
869 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
871 struct mv88e6xxx_chip *chip = dev_id;
872 irqreturn_t ret = IRQ_NONE;
874 mutex_lock(&chip->reg_lock);
875 if (chip->info->ops->watchdog_ops->irq_action)
876 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
877 mutex_unlock(&chip->reg_lock);
882 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
884 mutex_lock(&chip->reg_lock);
885 if (chip->info->ops->watchdog_ops->irq_free)
886 chip->info->ops->watchdog_ops->irq_free(chip);
887 mutex_unlock(&chip->reg_lock);
889 free_irq(chip->watchdog_irq, chip);
890 irq_dispose_mapping(chip->watchdog_irq);
893 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
897 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
898 MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
899 if (chip->watchdog_irq < 0)
900 return chip->watchdog_irq;
902 err = request_threaded_irq(chip->watchdog_irq, NULL,
903 mv88e6xxx_g2_watchdog_thread_fn,
904 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
905 "mv88e6xxx-watchdog", chip);
909 mutex_lock(&chip->reg_lock);
910 if (chip->info->ops->watchdog_ops->irq_setup)
911 err = chip->info->ops->watchdog_ops->irq_setup(chip);
912 mutex_unlock(&chip->reg_lock);
917 /* Offset 0x1D: Misc Register */
919 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
925 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
930 val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
932 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
934 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
937 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
939 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
942 static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
944 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
945 unsigned int n = d->hwirq;
947 chip->g2_irq.masked |= (1 << n);
950 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
952 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
953 unsigned int n = d->hwirq;
955 chip->g2_irq.masked &= ~(1 << n);
958 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
960 struct mv88e6xxx_chip *chip = dev_id;
961 unsigned int nhandled = 0;
962 unsigned int sub_irq;
967 mutex_lock(&chip->reg_lock);
968 err = mv88e6xxx_g2_int_source(chip, ®);
969 mutex_unlock(&chip->reg_lock);
973 for (n = 0; n < 16; ++n) {
974 if (reg & (1 << n)) {
975 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
976 handle_nested_irq(sub_irq);
981 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
984 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
986 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
988 mutex_lock(&chip->reg_lock);
991 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
993 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
996 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
998 dev_err(chip->dev, "failed to mask interrupts\n");
1000 mutex_unlock(&chip->reg_lock);
1003 static const struct irq_chip mv88e6xxx_g2_irq_chip = {
1004 .name = "mv88e6xxx-g2",
1005 .irq_mask = mv88e6xxx_g2_irq_mask,
1006 .irq_unmask = mv88e6xxx_g2_irq_unmask,
1007 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
1008 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
1011 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
1013 irq_hw_number_t hwirq)
1015 struct mv88e6xxx_chip *chip = d->host_data;
1017 irq_set_chip_data(irq, d->host_data);
1018 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1019 irq_set_noprobe(irq);
1024 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
1025 .map = mv88e6xxx_g2_irq_domain_map,
1026 .xlate = irq_domain_xlate_twocell,
1029 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1033 mv88e6xxx_g2_watchdog_free(chip);
1035 free_irq(chip->device_irq, chip);
1036 irq_dispose_mapping(chip->device_irq);
1038 for (irq = 0; irq < 16; irq++) {
1039 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1040 irq_dispose_mapping(virq);
1043 irq_domain_remove(chip->g2_irq.domain);
1046 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1050 chip->g2_irq.domain = irq_domain_add_simple(
1051 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1052 if (!chip->g2_irq.domain)
1055 for (irq = 0; irq < 16; irq++)
1056 irq_create_mapping(chip->g2_irq.domain, irq);
1058 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1059 chip->g2_irq.masked = ~0;
1061 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1062 MV88E6XXX_G1_STS_IRQ_DEVICE);
1063 if (chip->device_irq < 0) {
1064 err = chip->device_irq;
1068 err = request_threaded_irq(chip->device_irq, NULL,
1069 mv88e6xxx_g2_irq_thread_fn,
1070 IRQF_ONESHOT, "mv88e6xxx-g2", chip);
1074 return mv88e6xxx_g2_watchdog_setup(chip);
1077 for (irq = 0; irq < 16; irq++) {
1078 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1079 irq_dispose_mapping(virq);
1082 irq_domain_remove(chip->g2_irq.domain);
1087 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
1088 struct mii_bus *bus)
1090 int phy, irq, err, err_phy;
1092 for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
1093 irq = irq_find_mapping(chip->g2_irq.domain, phy);
1098 bus->irq[chip->info->phy_base_addr + phy] = irq;
1104 for (phy = 0; phy < err_phy; phy++)
1105 irq_dispose_mapping(bus->irq[phy]);
1110 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
1111 struct mii_bus *bus)
1115 for (phy = 0; phy < chip->info->num_internal_phys; phy++)
1116 irq_dispose_mapping(bus->irq[phy]);