2 * Marvell 88E6xxx Switch Global (1) Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #ifndef _MV88E6XXX_GLOBAL1_H
16 #define _MV88E6XXX_GLOBAL1_H
20 /* Offset 0x00: Switch Global Status Register */
21 #define MV88E6XXX_G1_STS 0x00
22 #define MV88E6352_G1_STS_PPU_STATE 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
24 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
25 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
26 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
27 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
28 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
29 #define MV88E6XXX_G1_STS_IRQ_AVB 8
30 #define MV88E6XXX_G1_STS_IRQ_DEVICE 7
31 #define MV88E6XXX_G1_STS_IRQ_STATS 6
32 #define MV88E6XXX_G1_STS_IRQ_VTU_PROBLEM 5
33 #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
34 #define MV88E6XXX_G1_STS_IRQ_ATU_PROBLEM 3
35 #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
36 #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
37 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
39 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
40 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
41 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
43 #define MV88E6XXX_G1_MAC_01 0x01
44 #define MV88E6XXX_G1_MAC_23 0x02
45 #define MV88E6XXX_G1_MAC_45 0x03
47 /* Offset 0x01: ATU FID Register */
48 #define MV88E6352_G1_ATU_FID 0x01
50 /* Offset 0x02: VTU FID Register */
51 #define MV88E6352_G1_VTU_FID 0x02
52 #define MV88E6352_G1_VTU_FID_MASK 0x0fff
54 /* Offset 0x03: VTU SID Register */
55 #define MV88E6352_G1_VTU_SID 0x03
56 #define MV88E6352_G1_VTU_SID_MASK 0x3f
58 /* Offset 0x04: Switch Global Control Register */
59 #define MV88E6XXX_G1_CTL1 0x04
60 #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
61 #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
62 #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
63 #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
64 #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
65 #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
66 #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
67 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
68 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
69 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
70 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
71 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
72 #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
73 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
75 /* Offset 0x05: VTU Operation Register */
76 #define MV88E6XXX_G1_VTU_OP 0x05
77 #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
78 #define MV88E6XXX_G1_VTU_OP_MASK 0x7000
79 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
80 #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
81 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
82 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
83 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
84 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
86 /* Offset 0x06: VTU VID Register */
87 #define MV88E6XXX_G1_VTU_VID 0x06
88 #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
89 #define MV88E6390_G1_VTU_VID_PAGE 0x2000
90 #define MV88E6XXX_G1_VTU_VID_VALID 0x1000
92 /* Offset 0x07: VTU/STU Data Register 1
93 * Offset 0x08: VTU/STU Data Register 2
94 * Offset 0x09: VTU/STU Data Register 3
96 #define MV88E6XXX_G1_VTU_DATA1 0x07
97 #define MV88E6XXX_G1_VTU_DATA2 0x08
98 #define MV88E6XXX_G1_VTU_DATA3 0x09
99 #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
100 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
101 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
102 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
103 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
104 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
105 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
106 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
107 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
109 /* Offset 0x0A: ATU Control Register */
110 #define MV88E6XXX_G1_ATU_CTL 0x0a
111 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
113 /* Offset 0x0B: ATU Operation Register */
114 #define MV88E6XXX_G1_ATU_OP 0x0b
115 #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
116 #define MV88E6XXX_G1_ATU_OP_MASK 0x7000
117 #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
118 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
119 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
120 #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
121 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
124 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
126 /* Offset 0x0C: ATU Data Register */
127 #define MV88E6XXX_G1_ATU_DATA 0x0c
128 #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
129 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
130 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
131 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
132 #define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000
133 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d
134 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
135 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER 0x000f
136 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE 0x0005
137 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
138 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT 0x000e
139 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER 0x000f
141 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
142 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
143 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
145 #define MV88E6XXX_G1_ATU_MAC01 0x0d
146 #define MV88E6XXX_G1_ATU_MAC23 0x0e
147 #define MV88E6XXX_G1_ATU_MAC45 0x0f
149 /* Offset 0x10: IP-PRI Mapping Register 0
150 * Offset 0x11: IP-PRI Mapping Register 1
151 * Offset 0x12: IP-PRI Mapping Register 2
152 * Offset 0x13: IP-PRI Mapping Register 3
153 * Offset 0x14: IP-PRI Mapping Register 4
154 * Offset 0x15: IP-PRI Mapping Register 5
155 * Offset 0x16: IP-PRI Mapping Register 6
156 * Offset 0x17: IP-PRI Mapping Register 7
158 #define MV88E6XXX_G1_IP_PRI_0 0x10
159 #define MV88E6XXX_G1_IP_PRI_1 0x11
160 #define MV88E6XXX_G1_IP_PRI_2 0x12
161 #define MV88E6XXX_G1_IP_PRI_3 0x13
162 #define MV88E6XXX_G1_IP_PRI_4 0x14
163 #define MV88E6XXX_G1_IP_PRI_5 0x15
164 #define MV88E6XXX_G1_IP_PRI_6 0x16
165 #define MV88E6XXX_G1_IP_PRI_7 0x17
167 /* Offset 0x18: IEEE-PRI Register */
168 #define MV88E6XXX_G1_IEEE_PRI 0x18
170 /* Offset 0x19: Core Tag Type */
171 #define MV88E6185_G1_CORE_TAG_TYPE 0x19
173 /* Offset 0x1A: Monitor Control */
174 #define MV88E6185_G1_MONITOR_CTL 0x1a
175 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
176 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
177 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
178 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
179 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
181 /* Offset 0x1A: Monitor & MGMT Control Register */
182 #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
183 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
184 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
185 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
186 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
187 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO 0x0200
188 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI 0x0300
189 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
190 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
191 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
192 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0
193 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
195 /* Offset 0x1C: Global Control 2 */
196 #define MV88E6XXX_G1_CTL2 0x1c
197 #define MV88E6XXX_G1_CTL2_NO_CASCADE 0xe000
198 #define MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE 0xf000
199 #define MV88E6XXX_G1_CTL2_HIST_RX 0x0040
200 #define MV88E6XXX_G1_CTL2_HIST_TX 0x0080
201 #define MV88E6XXX_G1_CTL2_HIST_RX_TX 0x00c0
203 /* Offset 0x1D: Stats Operation Register */
204 #define MV88E6XXX_G1_STATS_OP 0x1d
205 #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
206 #define MV88E6XXX_G1_STATS_OP_NOP 0x0000
207 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
208 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
209 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
210 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
211 #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
212 #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
213 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
214 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
215 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
217 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
218 * Offset 0x1F: Stats Counter Register Bytes 1 & 0
220 #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
221 #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
223 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
224 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
225 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
227 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
229 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
230 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
232 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
233 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
235 int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
236 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
237 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
238 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
239 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
240 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
241 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
242 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
243 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
244 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
245 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
247 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
248 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
250 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
251 struct mv88e6xxx_atu_entry *entry);
252 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
253 struct mv88e6xxx_atu_entry *entry);
254 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
255 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
258 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
259 struct mv88e6xxx_vtu_entry *entry);
260 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
261 struct mv88e6xxx_vtu_entry *entry);
262 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
263 struct mv88e6xxx_vtu_entry *entry);
264 int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
265 struct mv88e6xxx_vtu_entry *entry);
266 int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
267 struct mv88e6xxx_vtu_entry *entry);
268 int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
269 struct mv88e6xxx_vtu_entry *entry);
270 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
272 #endif /* _MV88E6XXX_GLOBAL1_H */