1 // SPDX-License-Identifier: GPL-2.0-or-later
10 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
12 if (chip->info->ops->atu_get_hash)
13 return chip->info->ops->atu_get_hash(chip, hash);
18 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
20 if (chip->info->ops->atu_set_hash)
21 return chip->info->ops->atu_set_hash(chip, hash);
26 enum mv88e6xxx_devlink_param_id {
27 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
28 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
31 int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
32 struct devlink_param_gset_ctx *ctx)
34 struct mv88e6xxx_chip *chip = ds->priv;
37 mv88e6xxx_reg_lock(chip);
40 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
41 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
48 mv88e6xxx_reg_unlock(chip);
53 int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
54 struct devlink_param_gset_ctx *ctx)
56 struct mv88e6xxx_chip *chip = ds->priv;
59 mv88e6xxx_reg_lock(chip);
62 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
63 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
70 mv88e6xxx_reg_unlock(chip);
75 static const struct devlink_param mv88e6xxx_devlink_params[] = {
76 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
77 "ATU_hash", DEVLINK_PARAM_TYPE_U8,
78 BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
81 int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
83 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
84 ARRAY_SIZE(mv88e6xxx_devlink_params));
87 void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
89 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
90 ARRAY_SIZE(mv88e6xxx_devlink_params));
93 enum mv88e6xxx_devlink_resource_id {
94 MV88E6XXX_RESOURCE_ID_ATU,
95 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
96 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
97 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
98 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
101 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip,
107 mv88e6xxx_reg_lock(chip);
109 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL,
112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
116 err = mv88e6xxx_g1_atu_get_next(chip, 0);
118 dev_err(chip->dev, "failed to perform ATU get next\n");
122 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy);
124 dev_err(chip->dev, "failed to get ATU stats\n");
128 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK;
131 mv88e6xxx_reg_unlock(chip);
136 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv)
138 struct mv88e6xxx_chip *chip = priv;
140 return mv88e6xxx_devlink_atu_bin_get(chip,
141 MV88E6XXX_G2_ATU_STATS_BIN_0);
144 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv)
146 struct mv88e6xxx_chip *chip = priv;
148 return mv88e6xxx_devlink_atu_bin_get(chip,
149 MV88E6XXX_G2_ATU_STATS_BIN_1);
152 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv)
154 struct mv88e6xxx_chip *chip = priv;
156 return mv88e6xxx_devlink_atu_bin_get(chip,
157 MV88E6XXX_G2_ATU_STATS_BIN_2);
160 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv)
162 struct mv88e6xxx_chip *chip = priv;
164 return mv88e6xxx_devlink_atu_bin_get(chip,
165 MV88E6XXX_G2_ATU_STATS_BIN_3);
168 static u64 mv88e6xxx_devlink_atu_get(void *priv)
170 return mv88e6xxx_devlink_atu_bin_0_get(priv) +
171 mv88e6xxx_devlink_atu_bin_1_get(priv) +
172 mv88e6xxx_devlink_atu_bin_2_get(priv) +
173 mv88e6xxx_devlink_atu_bin_3_get(priv);
176 int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds)
178 struct devlink_resource_size_params size_params;
179 struct mv88e6xxx_chip *chip = ds->priv;
182 devlink_resource_size_params_init(&size_params,
183 mv88e6xxx_num_macs(chip),
184 mv88e6xxx_num_macs(chip),
185 1, DEVLINK_RESOURCE_UNIT_ENTRY);
187 err = dsa_devlink_resource_register(ds, "ATU",
188 mv88e6xxx_num_macs(chip),
189 MV88E6XXX_RESOURCE_ID_ATU,
190 DEVLINK_RESOURCE_ID_PARENT_TOP,
195 devlink_resource_size_params_init(&size_params,
196 mv88e6xxx_num_macs(chip) / 4,
197 mv88e6xxx_num_macs(chip) / 4,
198 1, DEVLINK_RESOURCE_UNIT_ENTRY);
200 err = dsa_devlink_resource_register(ds, "ATU_bin_0",
201 mv88e6xxx_num_macs(chip) / 4,
202 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
203 MV88E6XXX_RESOURCE_ID_ATU,
208 err = dsa_devlink_resource_register(ds, "ATU_bin_1",
209 mv88e6xxx_num_macs(chip) / 4,
210 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
211 MV88E6XXX_RESOURCE_ID_ATU,
216 err = dsa_devlink_resource_register(ds, "ATU_bin_2",
217 mv88e6xxx_num_macs(chip) / 4,
218 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
219 MV88E6XXX_RESOURCE_ID_ATU,
224 err = dsa_devlink_resource_register(ds, "ATU_bin_3",
225 mv88e6xxx_num_macs(chip) / 4,
226 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
227 MV88E6XXX_RESOURCE_ID_ATU,
232 dsa_devlink_resource_occ_get_register(ds,
233 MV88E6XXX_RESOURCE_ID_ATU,
234 mv88e6xxx_devlink_atu_get,
237 dsa_devlink_resource_occ_get_register(ds,
238 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
239 mv88e6xxx_devlink_atu_bin_0_get,
242 dsa_devlink_resource_occ_get_register(ds,
243 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
244 mv88e6xxx_devlink_atu_bin_1_get,
247 dsa_devlink_resource_occ_get_register(ds,
248 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
249 mv88e6xxx_devlink_atu_bin_2_get,
252 dsa_devlink_resource_occ_get_register(ds,
253 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
254 mv88e6xxx_devlink_atu_bin_3_get,
260 dsa_devlink_resources_unregister(ds);
264 static int mv88e6xxx_region_global_snapshot(struct devlink *dl,
265 const struct devlink_region_ops *ops,
266 struct netlink_ext_ack *extack,
269 struct mv88e6xxx_region_priv *region_priv = ops->priv;
270 struct dsa_switch *ds = dsa_devlink_to_ds(dl);
271 struct mv88e6xxx_chip *chip = ds->priv;
275 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL);
279 mv88e6xxx_reg_lock(chip);
280 for (i = 0; i < 32; i++) {
281 switch (region_priv->id) {
282 case MV88E6XXX_REGION_GLOBAL1:
283 err = mv88e6xxx_g1_read(chip, i, ®isters[i]);
285 case MV88E6XXX_REGION_GLOBAL2:
286 err = mv88e6xxx_g2_read(chip, i, ®isters[i]);
297 *data = (u8 *)registers;
299 mv88e6xxx_reg_unlock(chip);
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
305 * a generic format which covers all the current and hopefully future
306 * mv88e6xxx generations
309 struct mv88e6xxx_devlink_atu_entry {
310 /* The FID is scattered over multiple registers. */
319 static int mv88e6xxx_region_atu_snapshot_fid(struct mv88e6xxx_chip *chip,
321 struct mv88e6xxx_devlink_atu_entry *table,
324 u16 atu_op, atu_data, atu_01, atu_23, atu_45;
325 struct mv88e6xxx_atu_entry addr;
329 eth_broadcast_addr(addr.mac);
332 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
339 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &atu_op);
343 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &atu_data);
347 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01, &atu_01);
351 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC23, &atu_23);
355 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC45, &atu_45);
359 table[*count].fid = fid;
360 table[*count].atu_op = atu_op;
361 table[*count].atu_data = atu_data;
362 table[*count].atu_01 = atu_01;
363 table[*count].atu_23 = atu_23;
364 table[*count].atu_45 = atu_45;
366 } while (!is_broadcast_ether_addr(addr.mac));
371 static int mv88e6xxx_region_atu_snapshot(struct devlink *dl,
372 const struct devlink_region_ops *ops,
373 struct netlink_ext_ack *extack,
376 struct dsa_switch *ds = dsa_devlink_to_ds(dl);
377 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
378 struct mv88e6xxx_devlink_atu_entry *table;
379 struct mv88e6xxx_chip *chip = ds->priv;
380 int fid = -1, count, err;
382 table = kmalloc_array(mv88e6xxx_num_databases(chip),
383 sizeof(struct mv88e6xxx_devlink_atu_entry),
388 memset(table, 0, mv88e6xxx_num_databases(chip) *
389 sizeof(struct mv88e6xxx_devlink_atu_entry));
393 mv88e6xxx_reg_lock(chip);
395 err = mv88e6xxx_fid_map(chip, fid_bitmap);
402 fid = find_next_bit(fid_bitmap, MV88E6XXX_N_FID, fid + 1);
403 if (fid == MV88E6XXX_N_FID)
406 err = mv88e6xxx_region_atu_snapshot_fid(chip, fid, table,
415 mv88e6xxx_reg_unlock(chip);
420 static int mv88e6xxx_region_port_snapshot(struct devlink_port *devlink_port,
421 const struct devlink_port_region_ops *ops,
422 struct netlink_ext_ack *extack,
425 struct dsa_switch *ds = dsa_devlink_port_to_ds(devlink_port);
426 int port = dsa_devlink_port_to_port(devlink_port);
427 struct mv88e6xxx_chip *chip = ds->priv;
431 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL);
435 mv88e6xxx_reg_lock(chip);
436 for (i = 0; i < 32; i++) {
437 err = mv88e6xxx_port_read(chip, port, i, ®isters[i]);
443 *data = (u8 *)registers;
445 mv88e6xxx_reg_unlock(chip);
450 static struct mv88e6xxx_region_priv mv88e6xxx_region_global1_priv = {
451 .id = MV88E6XXX_REGION_GLOBAL1,
454 static struct devlink_region_ops mv88e6xxx_region_global1_ops = {
456 .snapshot = mv88e6xxx_region_global_snapshot,
458 .priv = &mv88e6xxx_region_global1_priv,
461 static struct mv88e6xxx_region_priv mv88e6xxx_region_global2_priv = {
462 .id = MV88E6XXX_REGION_GLOBAL2,
465 static struct devlink_region_ops mv88e6xxx_region_global2_ops = {
467 .snapshot = mv88e6xxx_region_global_snapshot,
469 .priv = &mv88e6xxx_region_global2_priv,
472 static struct devlink_region_ops mv88e6xxx_region_atu_ops = {
474 .snapshot = mv88e6xxx_region_atu_snapshot,
478 static const struct devlink_port_region_ops mv88e6xxx_region_port_ops = {
480 .snapshot = mv88e6xxx_region_port_snapshot,
484 struct mv88e6xxx_region {
485 struct devlink_region_ops *ops;
489 static struct mv88e6xxx_region mv88e6xxx_regions[] = {
490 [MV88E6XXX_REGION_GLOBAL1] = {
491 .ops = &mv88e6xxx_region_global1_ops,
492 .size = 32 * sizeof(u16)
494 [MV88E6XXX_REGION_GLOBAL2] = {
495 .ops = &mv88e6xxx_region_global2_ops,
496 .size = 32 * sizeof(u16) },
497 [MV88E6XXX_REGION_ATU] = {
498 .ops = &mv88e6xxx_region_atu_ops
499 /* calculated at runtime */
504 mv88e6xxx_teardown_devlink_regions_global(struct mv88e6xxx_chip *chip)
508 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_regions); i++)
509 dsa_devlink_region_destroy(chip->regions[i]);
513 mv88e6xxx_teardown_devlink_regions_port(struct mv88e6xxx_chip *chip,
516 dsa_devlink_region_destroy(chip->ports[port].region);
519 static int mv88e6xxx_setup_devlink_regions_port(struct dsa_switch *ds,
520 struct mv88e6xxx_chip *chip,
523 struct devlink_region *region;
525 region = dsa_devlink_port_region_create(ds,
527 &mv88e6xxx_region_port_ops, 1,
530 return PTR_ERR(region);
532 chip->ports[port].region = region;
538 mv88e6xxx_teardown_devlink_regions_ports(struct mv88e6xxx_chip *chip)
542 for (port = 0; port < mv88e6xxx_num_ports(chip); port++)
543 mv88e6xxx_teardown_devlink_regions_port(chip, port);
546 static int mv88e6xxx_setup_devlink_regions_ports(struct dsa_switch *ds,
547 struct mv88e6xxx_chip *chip)
552 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
553 err = mv88e6xxx_setup_devlink_regions_port(ds, chip, port);
562 mv88e6xxx_teardown_devlink_regions_port(chip, port);
567 static int mv88e6xxx_setup_devlink_regions_global(struct dsa_switch *ds,
568 struct mv88e6xxx_chip *chip)
570 struct devlink_region_ops *ops;
571 struct devlink_region *region;
575 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_regions); i++) {
576 ops = mv88e6xxx_regions[i].ops;
577 size = mv88e6xxx_regions[i].size;
579 if (i == MV88E6XXX_REGION_ATU)
580 size = mv88e6xxx_num_databases(chip) *
581 sizeof(struct mv88e6xxx_devlink_atu_entry);
583 region = dsa_devlink_region_create(ds, ops, 1, size);
586 chip->regions[i] = region;
591 for (j = 0; j < i; j++)
592 dsa_devlink_region_destroy(chip->regions[j]);
594 return PTR_ERR(region);
597 int mv88e6xxx_setup_devlink_regions(struct dsa_switch *ds)
599 struct mv88e6xxx_chip *chip = ds->priv;
602 err = mv88e6xxx_setup_devlink_regions_global(ds, chip);
606 err = mv88e6xxx_setup_devlink_regions_ports(ds, chip);
608 mv88e6xxx_teardown_devlink_regions_global(chip);
613 void mv88e6xxx_teardown_devlink_regions(struct dsa_switch *ds)
615 struct mv88e6xxx_chip *chip = ds->priv;
617 mv88e6xxx_teardown_devlink_regions_ports(chip);
618 mv88e6xxx_teardown_devlink_regions_global(chip);
621 int mv88e6xxx_devlink_info_get(struct dsa_switch *ds,
622 struct devlink_info_req *req,
623 struct netlink_ext_ack *extack)
625 struct mv88e6xxx_chip *chip = ds->priv;
628 err = devlink_info_driver_name_put(req, "mv88e6xxx");
632 return devlink_info_version_fixed_put(req,
633 DEVLINK_INFO_VERSION_GENERIC_ASIC_ID,