2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
31 #include <net/switchdev.h>
33 #include "mv88e6xxx.h"
37 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
39 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
40 dev_err(chip->dev, "Switch registers lock not held!\n");
45 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
46 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
48 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
49 * is the only device connected to the SMI master. In this mode it responds to
50 * all 32 possible SMI addresses, and thus maps directly the internal devices.
52 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
53 * multiple devices to share the SMI interface. In this mode it responds to only
54 * 2 registers, used to indirectly access the internal SMI devices.
57 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
58 int addr, int reg, u16 *val)
63 return chip->smi_ops->read(chip, addr, reg, val);
66 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
67 int addr, int reg, u16 val)
72 return chip->smi_ops->write(chip, addr, reg, val);
75 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
76 int addr, int reg, u16 *val)
80 ret = mdiobus_read_nested(chip->bus, addr, reg);
89 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
90 int addr, int reg, u16 val)
94 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
101 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
102 .read = mv88e6xxx_smi_single_chip_read,
103 .write = mv88e6xxx_smi_single_chip_write,
106 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
111 for (i = 0; i < 16; i++) {
112 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
116 if ((ret & SMI_CMD_BUSY) == 0)
123 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
124 int addr, int reg, u16 *val)
128 /* Wait for the bus to become free. */
129 ret = mv88e6xxx_smi_multi_chip_wait(chip);
133 /* Transmit the read command. */
134 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
135 SMI_CMD_OP_22_READ | (addr << 5) | reg);
139 /* Wait for the read command to complete. */
140 ret = mv88e6xxx_smi_multi_chip_wait(chip);
145 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
154 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
155 int addr, int reg, u16 val)
159 /* Wait for the bus to become free. */
160 ret = mv88e6xxx_smi_multi_chip_wait(chip);
164 /* Transmit the data to write. */
165 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
169 /* Transmit the write command. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
171 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
175 /* Wait for the write command to complete. */
176 ret = mv88e6xxx_smi_multi_chip_wait(chip);
183 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
184 .read = mv88e6xxx_smi_multi_chip_read,
185 .write = mv88e6xxx_smi_multi_chip_write,
188 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
192 assert_reg_lock(chip);
194 err = mv88e6xxx_smi_read(chip, addr, reg, val);
198 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
204 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
208 assert_reg_lock(chip);
210 err = mv88e6xxx_smi_write(chip, addr, reg, val);
214 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
220 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
223 int addr = chip->info->port_base_addr + port;
225 return mv88e6xxx_read(chip, addr, reg, val);
228 static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
231 int addr = chip->info->port_base_addr + port;
233 return mv88e6xxx_write(chip, addr, reg, val);
236 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
239 int addr = phy; /* PHY devices addresses start at 0x0 */
241 if (!chip->info->ops->phy_read)
244 return chip->info->ops->phy_read(chip, addr, reg, val);
247 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
250 int addr = phy; /* PHY devices addresses start at 0x0 */
252 if (!chip->info->ops->phy_write)
255 return chip->info->ops->phy_write(chip, addr, reg, val);
258 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
260 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
263 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
266 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
270 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
271 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
273 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
278 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
279 u8 page, int reg, u16 *val)
283 /* There is no paging for registers 22 */
287 err = mv88e6xxx_phy_page_get(chip, phy, page);
289 err = mv88e6xxx_phy_read(chip, phy, reg, val);
290 mv88e6xxx_phy_page_put(chip, phy);
296 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
297 u8 page, int reg, u16 val)
301 /* There is no paging for registers 22 */
305 err = mv88e6xxx_phy_page_get(chip, phy, page);
307 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
308 mv88e6xxx_phy_page_put(chip, phy);
314 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
316 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
320 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
322 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
326 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
330 for (i = 0; i < 16; i++) {
334 err = mv88e6xxx_read(chip, addr, reg, &val);
341 usleep_range(1000, 2000);
344 dev_err(chip->dev, "Timeout while waiting for switch\n");
348 /* Indirect write to single pointer-data register with an Update bit */
349 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
354 /* Wait until the previous operation is completed */
355 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
359 /* Set the Update bit to trigger a write operation */
360 val = BIT(15) | update;
362 return mv88e6xxx_write(chip, addr, reg, val);
365 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
370 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
374 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
375 val & ~GLOBAL_CONTROL_PPU_ENABLE);
379 for (i = 0; i < 16; i++) {
380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
384 usleep_range(1000, 2000);
385 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
392 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
397 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
401 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
402 val | GLOBAL_CONTROL_PPU_ENABLE);
406 for (i = 0; i < 16; i++) {
407 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
411 usleep_range(1000, 2000);
412 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
419 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
421 struct mv88e6xxx_chip *chip;
423 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
425 mutex_lock(&chip->reg_lock);
427 if (mutex_trylock(&chip->ppu_mutex)) {
428 if (mv88e6xxx_ppu_enable(chip) == 0)
429 chip->ppu_disabled = 0;
430 mutex_unlock(&chip->ppu_mutex);
433 mutex_unlock(&chip->reg_lock);
436 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
438 struct mv88e6xxx_chip *chip = (void *)_ps;
440 schedule_work(&chip->ppu_work);
443 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
447 mutex_lock(&chip->ppu_mutex);
449 /* If the PHY polling unit is enabled, disable it so that
450 * we can access the PHY registers. If it was already
451 * disabled, cancel the timer that is going to re-enable
454 if (!chip->ppu_disabled) {
455 ret = mv88e6xxx_ppu_disable(chip);
457 mutex_unlock(&chip->ppu_mutex);
460 chip->ppu_disabled = 1;
462 del_timer(&chip->ppu_timer);
469 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
471 /* Schedule a timer to re-enable the PHY polling unit. */
472 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
473 mutex_unlock(&chip->ppu_mutex);
476 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
478 mutex_init(&chip->ppu_mutex);
479 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
480 init_timer(&chip->ppu_timer);
481 chip->ppu_timer.data = (unsigned long)chip;
482 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
485 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
487 del_timer_sync(&chip->ppu_timer);
490 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
495 err = mv88e6xxx_ppu_access_get(chip);
497 err = mv88e6xxx_read(chip, addr, reg, val);
498 mv88e6xxx_ppu_access_put(chip);
504 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
509 err = mv88e6xxx_ppu_access_get(chip);
511 err = mv88e6xxx_write(chip, addr, reg, val);
512 mv88e6xxx_ppu_access_put(chip);
518 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
520 return chip->info->family == MV88E6XXX_FAMILY_6065;
523 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
525 return chip->info->family == MV88E6XXX_FAMILY_6095;
528 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
530 return chip->info->family == MV88E6XXX_FAMILY_6097;
533 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
535 return chip->info->family == MV88E6XXX_FAMILY_6165;
538 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
540 return chip->info->family == MV88E6XXX_FAMILY_6185;
543 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
545 return chip->info->family == MV88E6XXX_FAMILY_6320;
548 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
550 return chip->info->family == MV88E6XXX_FAMILY_6351;
553 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
555 return chip->info->family == MV88E6XXX_FAMILY_6352;
558 /* We expect the switch to perform auto negotiation if there is a real
559 * phy. However, in the case of a fixed link phy, we force the port
560 * settings from the fixed link settings.
562 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
563 struct phy_device *phydev)
565 struct mv88e6xxx_chip *chip = ds->priv;
569 if (!phy_is_pseudo_fixed_link(phydev))
572 mutex_lock(&chip->reg_lock);
574 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
578 reg &= ~(PORT_PCS_CTRL_LINK_UP |
579 PORT_PCS_CTRL_FORCE_LINK |
580 PORT_PCS_CTRL_DUPLEX_FULL |
581 PORT_PCS_CTRL_FORCE_DUPLEX |
582 PORT_PCS_CTRL_UNFORCED);
584 reg |= PORT_PCS_CTRL_FORCE_LINK;
586 reg |= PORT_PCS_CTRL_LINK_UP;
588 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
591 switch (phydev->speed) {
593 reg |= PORT_PCS_CTRL_1000;
596 reg |= PORT_PCS_CTRL_100;
599 reg |= PORT_PCS_CTRL_10;
602 pr_info("Unknown speed");
606 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
607 if (phydev->duplex == DUPLEX_FULL)
608 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
610 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
611 (port >= mv88e6xxx_num_ports(chip) - 2)) {
612 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
613 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
614 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
615 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
616 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
617 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
618 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
620 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
623 mutex_unlock(&chip->reg_lock);
626 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
631 for (i = 0; i < 10; i++) {
632 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
633 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
640 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
644 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
645 port = (port + 1) << 5;
647 /* Snapshot the hardware statistics counters for this port. */
648 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
649 GLOBAL_STATS_OP_CAPTURE_PORT |
650 GLOBAL_STATS_OP_HIST_RX_TX | port);
654 /* Wait for the snapshotting to complete. */
655 return _mv88e6xxx_stats_wait(chip);
658 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
667 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
668 GLOBAL_STATS_OP_READ_CAPTURED |
669 GLOBAL_STATS_OP_HIST_RX_TX | stat);
673 err = _mv88e6xxx_stats_wait(chip);
677 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®);
683 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®);
690 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
691 { "in_good_octets", 8, 0x00, BANK0, },
692 { "in_bad_octets", 4, 0x02, BANK0, },
693 { "in_unicast", 4, 0x04, BANK0, },
694 { "in_broadcasts", 4, 0x06, BANK0, },
695 { "in_multicasts", 4, 0x07, BANK0, },
696 { "in_pause", 4, 0x16, BANK0, },
697 { "in_undersize", 4, 0x18, BANK0, },
698 { "in_fragments", 4, 0x19, BANK0, },
699 { "in_oversize", 4, 0x1a, BANK0, },
700 { "in_jabber", 4, 0x1b, BANK0, },
701 { "in_rx_error", 4, 0x1c, BANK0, },
702 { "in_fcs_error", 4, 0x1d, BANK0, },
703 { "out_octets", 8, 0x0e, BANK0, },
704 { "out_unicast", 4, 0x10, BANK0, },
705 { "out_broadcasts", 4, 0x13, BANK0, },
706 { "out_multicasts", 4, 0x12, BANK0, },
707 { "out_pause", 4, 0x15, BANK0, },
708 { "excessive", 4, 0x11, BANK0, },
709 { "collisions", 4, 0x1e, BANK0, },
710 { "deferred", 4, 0x05, BANK0, },
711 { "single", 4, 0x14, BANK0, },
712 { "multiple", 4, 0x17, BANK0, },
713 { "out_fcs_error", 4, 0x03, BANK0, },
714 { "late", 4, 0x1f, BANK0, },
715 { "hist_64bytes", 4, 0x08, BANK0, },
716 { "hist_65_127bytes", 4, 0x09, BANK0, },
717 { "hist_128_255bytes", 4, 0x0a, BANK0, },
718 { "hist_256_511bytes", 4, 0x0b, BANK0, },
719 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
720 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
721 { "sw_in_discards", 4, 0x10, PORT, },
722 { "sw_in_filtered", 2, 0x12, PORT, },
723 { "sw_out_filtered", 2, 0x13, PORT, },
724 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
725 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
726 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
727 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
728 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
729 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
730 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
731 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
732 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
733 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
734 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
735 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
736 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
737 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
738 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
739 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
740 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
741 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
742 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
743 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
744 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
745 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
746 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
747 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
748 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
749 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
753 struct mv88e6xxx_hw_stat *stat)
755 switch (stat->type) {
759 return mv88e6xxx_6320_family(chip);
761 return mv88e6xxx_6095_family(chip) ||
762 mv88e6xxx_6185_family(chip) ||
763 mv88e6xxx_6097_family(chip) ||
764 mv88e6xxx_6165_family(chip) ||
765 mv88e6xxx_6351_family(chip) ||
766 mv88e6xxx_6352_family(chip);
771 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
772 struct mv88e6xxx_hw_stat *s,
783 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
788 if (s->sizeof_stat == 4) {
789 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
792 low |= ((u32)reg) << 16;
797 _mv88e6xxx_stats_read(chip, s->reg, &low);
798 if (s->sizeof_stat == 8)
799 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
801 value = (((u64)high) << 32) | low;
805 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
808 struct mv88e6xxx_chip *chip = ds->priv;
809 struct mv88e6xxx_hw_stat *stat;
812 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
813 stat = &mv88e6xxx_hw_stats[i];
814 if (mv88e6xxx_has_stat(chip, stat)) {
815 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
822 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
824 struct mv88e6xxx_chip *chip = ds->priv;
825 struct mv88e6xxx_hw_stat *stat;
828 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
829 stat = &mv88e6xxx_hw_stats[i];
830 if (mv88e6xxx_has_stat(chip, stat))
836 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
839 struct mv88e6xxx_chip *chip = ds->priv;
840 struct mv88e6xxx_hw_stat *stat;
844 mutex_lock(&chip->reg_lock);
846 ret = _mv88e6xxx_stats_snapshot(chip, port);
848 mutex_unlock(&chip->reg_lock);
851 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
852 stat = &mv88e6xxx_hw_stats[i];
853 if (mv88e6xxx_has_stat(chip, stat)) {
854 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
859 mutex_unlock(&chip->reg_lock);
862 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
864 return 32 * sizeof(u16);
867 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
868 struct ethtool_regs *regs, void *_p)
870 struct mv88e6xxx_chip *chip = ds->priv;
878 memset(p, 0xff, 32 * sizeof(u16));
880 mutex_lock(&chip->reg_lock);
882 for (i = 0; i < 32; i++) {
884 err = mv88e6xxx_port_read(chip, port, i, ®);
889 mutex_unlock(&chip->reg_lock);
892 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
894 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
897 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
898 struct ethtool_eee *e)
900 struct mv88e6xxx_chip *chip = ds->priv;
904 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
907 mutex_lock(&chip->reg_lock);
909 err = mv88e6xxx_phy_read(chip, port, 16, ®);
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
916 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
920 e->eee_active = !!(reg & PORT_STATUS_EEE);
922 mutex_unlock(&chip->reg_lock);
927 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
928 struct phy_device *phydev, struct ethtool_eee *e)
930 struct mv88e6xxx_chip *chip = ds->priv;
934 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
937 mutex_lock(&chip->reg_lock);
939 err = mv88e6xxx_phy_read(chip, port, 16, ®);
946 if (e->tx_lpi_enabled)
949 err = mv88e6xxx_phy_write(chip, port, 16, reg);
951 mutex_unlock(&chip->reg_lock);
956 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
961 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
962 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
965 } else if (mv88e6xxx_num_databases(chip) == 256) {
966 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
967 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
971 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
972 (val & 0xfff) | ((fid << 8) & 0xf000));
976 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
980 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
984 return _mv88e6xxx_atu_wait(chip);
987 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
988 struct mv88e6xxx_atu_entry *entry)
990 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
992 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
993 unsigned int mask, shift;
996 data |= GLOBAL_ATU_DATA_TRUNK;
997 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
998 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1000 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1001 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1004 data |= (entry->portv_trunkid << shift) & mask;
1007 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1010 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1011 struct mv88e6xxx_atu_entry *entry,
1017 err = _mv88e6xxx_atu_wait(chip);
1021 err = _mv88e6xxx_atu_data_write(chip, entry);
1026 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1027 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1029 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1030 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1033 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1036 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1037 u16 fid, bool static_too)
1039 struct mv88e6xxx_atu_entry entry = {
1041 .state = 0, /* EntryState bits must be 0 */
1044 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1047 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1048 int from_port, int to_port, bool static_too)
1050 struct mv88e6xxx_atu_entry entry = {
1055 /* EntryState bits must be 0xF */
1056 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1058 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1059 entry.portv_trunkid = (to_port & 0x0f) << 4;
1060 entry.portv_trunkid |= from_port & 0x0f;
1062 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1065 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1066 int port, bool static_too)
1068 /* Destination port 0xF means remove the entries */
1069 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1072 static const char * const mv88e6xxx_port_state_names[] = {
1073 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1074 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1075 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1076 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1079 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1082 struct dsa_switch *ds = chip->ds;
1087 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
1091 oldstate = reg & PORT_CONTROL_STATE_MASK;
1093 reg &= ~PORT_CONTROL_STATE_MASK;
1096 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1100 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1101 mv88e6xxx_port_state_names[state],
1102 mv88e6xxx_port_state_names[oldstate]);
1107 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1109 struct net_device *bridge = chip->ports[port].bridge_dev;
1110 const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1;
1111 struct dsa_switch *ds = chip->ds;
1112 u16 output_ports = 0;
1117 /* allow CPU port or DSA link(s) to send frames to every port */
1118 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1119 output_ports = mask;
1121 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1122 /* allow sending frames to every group member */
1123 if (bridge && chip->ports[i].bridge_dev == bridge)
1124 output_ports |= BIT(i);
1126 /* allow sending frames to CPU port and DSA link(s) */
1127 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1128 output_ports |= BIT(i);
1132 /* prevent frames from going back out of the port they came in on */
1133 output_ports &= ~BIT(port);
1135 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
1140 reg |= output_ports & mask;
1142 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1145 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1148 struct mv88e6xxx_chip *chip = ds->priv;
1153 case BR_STATE_DISABLED:
1154 stp_state = PORT_CONTROL_STATE_DISABLED;
1156 case BR_STATE_BLOCKING:
1157 case BR_STATE_LISTENING:
1158 stp_state = PORT_CONTROL_STATE_BLOCKING;
1160 case BR_STATE_LEARNING:
1161 stp_state = PORT_CONTROL_STATE_LEARNING;
1163 case BR_STATE_FORWARDING:
1165 stp_state = PORT_CONTROL_STATE_FORWARDING;
1169 mutex_lock(&chip->reg_lock);
1170 err = _mv88e6xxx_port_state(chip, port, stp_state);
1171 mutex_unlock(&chip->reg_lock);
1174 netdev_err(ds->ports[port].netdev,
1175 "failed to update state to %s\n",
1176 mv88e6xxx_port_state_names[stp_state]);
1179 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1181 struct mv88e6xxx_chip *chip = ds->priv;
1184 mutex_lock(&chip->reg_lock);
1185 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1186 mutex_unlock(&chip->reg_lock);
1189 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1192 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1195 struct dsa_switch *ds = chip->ds;
1199 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
1203 pvid = reg & PORT_DEFAULT_VLAN_MASK;
1206 reg &= ~PORT_DEFAULT_VLAN_MASK;
1207 reg |= *new & PORT_DEFAULT_VLAN_MASK;
1209 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1213 netdev_dbg(ds->ports[port].netdev,
1214 "DefaultVID %d (was %d)\n", *new, pvid);
1223 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1224 int port, u16 *pvid)
1226 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1229 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1232 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1235 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1237 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1240 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1244 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1248 return _mv88e6xxx_vtu_wait(chip);
1251 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1255 ret = _mv88e6xxx_vtu_wait(chip);
1259 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1262 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1263 struct mv88e6xxx_vtu_entry *entry,
1264 unsigned int nibble_offset)
1269 for (i = 0; i < 3; ++i) {
1270 u16 *reg = ®s[i];
1272 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1277 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1278 unsigned int shift = (i % 4) * 4 + nibble_offset;
1279 u16 reg = regs[i / 4];
1281 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1287 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1288 struct mv88e6xxx_vtu_entry *entry)
1290 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1293 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1294 struct mv88e6xxx_vtu_entry *entry)
1296 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1299 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1300 struct mv88e6xxx_vtu_entry *entry,
1301 unsigned int nibble_offset)
1303 u16 regs[3] = { 0 };
1306 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1307 unsigned int shift = (i % 4) * 4 + nibble_offset;
1308 u8 data = entry->data[i];
1310 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1313 for (i = 0; i < 3; ++i) {
1316 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1324 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1325 struct mv88e6xxx_vtu_entry *entry)
1327 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1330 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1331 struct mv88e6xxx_vtu_entry *entry)
1333 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1336 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1338 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1339 vid & GLOBAL_VTU_VID_MASK);
1342 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1343 struct mv88e6xxx_vtu_entry *entry)
1345 struct mv88e6xxx_vtu_entry next = { 0 };
1349 err = _mv88e6xxx_vtu_wait(chip);
1353 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1357 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1361 next.vid = val & GLOBAL_VTU_VID_MASK;
1362 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1365 err = mv88e6xxx_vtu_data_read(chip, &next);
1369 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1370 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1374 next.fid = val & GLOBAL_VTU_FID_MASK;
1375 } else if (mv88e6xxx_num_databases(chip) == 256) {
1376 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1377 * VTU DBNum[3:0] are located in VTU Operation 3:0
1379 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1383 next.fid = (val & 0xf00) >> 4;
1384 next.fid |= val & 0xf;
1387 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1388 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1392 next.sid = val & GLOBAL_VTU_SID_MASK;
1400 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1401 struct switchdev_obj_port_vlan *vlan,
1402 int (*cb)(struct switchdev_obj *obj))
1404 struct mv88e6xxx_chip *chip = ds->priv;
1405 struct mv88e6xxx_vtu_entry next;
1409 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1412 mutex_lock(&chip->reg_lock);
1414 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1418 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1423 err = _mv88e6xxx_vtu_getnext(chip, &next);
1430 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1433 /* reinit and dump this VLAN obj */
1434 vlan->vid_begin = next.vid;
1435 vlan->vid_end = next.vid;
1438 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1439 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1441 if (next.vid == pvid)
1442 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1444 err = cb(&vlan->obj);
1447 } while (next.vid < GLOBAL_VTU_VID_MASK);
1450 mutex_unlock(&chip->reg_lock);
1455 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1456 struct mv88e6xxx_vtu_entry *entry)
1458 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1462 err = _mv88e6xxx_vtu_wait(chip);
1469 /* Write port member tags */
1470 err = mv88e6xxx_vtu_data_write(chip, entry);
1474 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1475 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1476 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1481 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1482 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1483 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1486 } else if (mv88e6xxx_num_databases(chip) == 256) {
1487 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1488 * VTU DBNum[3:0] are located in VTU Operation 3:0
1490 op |= (entry->fid & 0xf0) << 8;
1491 op |= entry->fid & 0xf;
1494 reg = GLOBAL_VTU_VID_VALID;
1496 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1497 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1501 return _mv88e6xxx_vtu_cmd(chip, op);
1504 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1505 struct mv88e6xxx_vtu_entry *entry)
1507 struct mv88e6xxx_vtu_entry next = { 0 };
1511 err = _mv88e6xxx_vtu_wait(chip);
1515 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1516 sid & GLOBAL_VTU_SID_MASK);
1520 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1524 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1528 next.sid = val & GLOBAL_VTU_SID_MASK;
1530 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1534 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1537 err = mv88e6xxx_stu_data_read(chip, &next);
1546 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1547 struct mv88e6xxx_vtu_entry *entry)
1552 err = _mv88e6xxx_vtu_wait(chip);
1559 /* Write port states */
1560 err = mv88e6xxx_stu_data_write(chip, entry);
1564 reg = GLOBAL_VTU_VID_VALID;
1566 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1570 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1571 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1575 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1578 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1581 struct dsa_switch *ds = chip->ds;
1587 if (mv88e6xxx_num_databases(chip) == 4096)
1589 else if (mv88e6xxx_num_databases(chip) == 256)
1594 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1595 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
1599 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1602 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1603 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1605 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1610 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1611 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
1615 fid |= (reg & upper_mask) << 4;
1619 reg |= (*new >> 4) & upper_mask;
1621 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1625 netdev_dbg(ds->ports[port].netdev,
1626 "FID %d (was %d)\n", *new, fid);
1635 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1638 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1641 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1644 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1647 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1649 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1650 struct mv88e6xxx_vtu_entry vlan;
1653 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1655 /* Set every FID bit used by the (un)bridged ports */
1656 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1657 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1661 set_bit(*fid, fid_bitmap);
1664 /* Set every FID bit used by the VLAN entries */
1665 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1670 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1677 set_bit(vlan.fid, fid_bitmap);
1678 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1680 /* The reset value 0x000 is used to indicate that multiple address
1681 * databases are not needed. Return the next positive available.
1683 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1684 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1687 /* Clear the database */
1688 return _mv88e6xxx_atu_flush(chip, *fid, true);
1691 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1692 struct mv88e6xxx_vtu_entry *entry)
1694 struct dsa_switch *ds = chip->ds;
1695 struct mv88e6xxx_vtu_entry vlan = {
1701 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1705 /* exclude all ports except the CPU and DSA ports */
1706 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1707 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1708 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1709 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1711 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1712 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1713 struct mv88e6xxx_vtu_entry vstp;
1715 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1716 * implemented, only one STU entry is needed to cover all VTU
1717 * entries. Thus, validate the SID 0.
1720 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1724 if (vstp.sid != vlan.sid || !vstp.valid) {
1725 memset(&vstp, 0, sizeof(vstp));
1727 vstp.sid = vlan.sid;
1729 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1739 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1740 struct mv88e6xxx_vtu_entry *entry, bool creat)
1747 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1751 err = _mv88e6xxx_vtu_getnext(chip, entry);
1755 if (entry->vid != vid || !entry->valid) {
1758 /* -ENOENT would've been more appropriate, but switchdev expects
1759 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1762 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1768 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1769 u16 vid_begin, u16 vid_end)
1771 struct mv88e6xxx_chip *chip = ds->priv;
1772 struct mv88e6xxx_vtu_entry vlan;
1778 mutex_lock(&chip->reg_lock);
1780 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1785 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1792 if (vlan.vid > vid_end)
1795 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1796 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1800 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1803 if (chip->ports[i].bridge_dev ==
1804 chip->ports[port].bridge_dev)
1805 break; /* same bridge, check next VLAN */
1807 netdev_warn(ds->ports[port].netdev,
1808 "hardware VLAN %d already used by %s\n",
1810 netdev_name(chip->ports[i].bridge_dev));
1814 } while (vlan.vid < vid_end);
1817 mutex_unlock(&chip->reg_lock);
1822 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1823 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1824 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1825 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1826 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1829 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1830 bool vlan_filtering)
1832 struct mv88e6xxx_chip *chip = ds->priv;
1833 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1834 PORT_CONTROL_2_8021Q_DISABLED;
1838 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1841 mutex_lock(&chip->reg_lock);
1843 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
1847 old = reg & PORT_CONTROL_2_8021Q_MASK;
1850 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1851 reg |= new & PORT_CONTROL_2_8021Q_MASK;
1853 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1857 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1858 mv88e6xxx_port_8021q_mode_names[new],
1859 mv88e6xxx_port_8021q_mode_names[old]);
1864 mutex_unlock(&chip->reg_lock);
1870 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1871 const struct switchdev_obj_port_vlan *vlan,
1872 struct switchdev_trans *trans)
1874 struct mv88e6xxx_chip *chip = ds->priv;
1877 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1883 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1888 /* We don't need any dynamic resource from the kernel (yet),
1889 * so skip the prepare phase.
1894 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1895 u16 vid, bool untagged)
1897 struct mv88e6xxx_vtu_entry vlan;
1900 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1904 vlan.data[port] = untagged ?
1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1908 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1911 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912 const struct switchdev_obj_port_vlan *vlan,
1913 struct switchdev_trans *trans)
1915 struct mv88e6xxx_chip *chip = ds->priv;
1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1920 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1923 mutex_lock(&chip->reg_lock);
1925 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1926 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1927 netdev_err(ds->ports[port].netdev,
1928 "failed to add VLAN %d%c\n",
1929 vid, untagged ? 'u' : 't');
1931 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1932 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1935 mutex_unlock(&chip->reg_lock);
1938 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1941 struct dsa_switch *ds = chip->ds;
1942 struct mv88e6xxx_vtu_entry vlan;
1945 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1949 /* Tell switchdev if this VLAN is handled in software */
1950 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1953 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1955 /* keep the VLAN unless all ports are excluded */
1957 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1958 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1961 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1967 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1971 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1974 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1975 const struct switchdev_obj_port_vlan *vlan)
1977 struct mv88e6xxx_chip *chip = ds->priv;
1981 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1984 mutex_lock(&chip->reg_lock);
1986 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1990 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1991 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1996 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2003 mutex_unlock(&chip->reg_lock);
2008 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2009 const unsigned char *addr)
2013 for (i = 0; i < 3; i++) {
2014 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2015 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2023 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2024 unsigned char *addr)
2029 for (i = 0; i < 3; i++) {
2030 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2034 addr[i * 2] = val >> 8;
2035 addr[i * 2 + 1] = val & 0xff;
2041 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2042 struct mv88e6xxx_atu_entry *entry)
2046 ret = _mv88e6xxx_atu_wait(chip);
2050 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2054 ret = _mv88e6xxx_atu_data_write(chip, entry);
2058 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2061 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2062 struct mv88e6xxx_atu_entry *entry);
2064 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2065 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2067 struct mv88e6xxx_atu_entry next;
2070 eth_broadcast_addr(next.mac);
2072 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2077 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2081 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2084 if (ether_addr_equal(next.mac, addr)) {
2088 } while (!is_broadcast_ether_addr(next.mac));
2090 memset(entry, 0, sizeof(*entry));
2092 ether_addr_copy(entry->mac, addr);
2097 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2098 const unsigned char *addr, u16 vid,
2101 struct mv88e6xxx_vtu_entry vlan;
2102 struct mv88e6xxx_atu_entry entry;
2105 /* Null VLAN ID corresponds to the port private database */
2107 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2109 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2113 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2117 /* Purge the ATU entry only if no port is using it anymore */
2118 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2119 entry.portv_trunkid &= ~BIT(port);
2120 if (!entry.portv_trunkid)
2121 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2123 entry.portv_trunkid |= BIT(port);
2124 entry.state = state;
2127 return _mv88e6xxx_atu_load(chip, &entry);
2130 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2131 const struct switchdev_obj_port_fdb *fdb,
2132 struct switchdev_trans *trans)
2134 /* We don't need any dynamic resource from the kernel (yet),
2135 * so skip the prepare phase.
2140 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2141 const struct switchdev_obj_port_fdb *fdb,
2142 struct switchdev_trans *trans)
2144 struct mv88e6xxx_chip *chip = ds->priv;
2146 mutex_lock(&chip->reg_lock);
2147 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2148 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2149 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2150 mutex_unlock(&chip->reg_lock);
2153 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2154 const struct switchdev_obj_port_fdb *fdb)
2156 struct mv88e6xxx_chip *chip = ds->priv;
2159 mutex_lock(&chip->reg_lock);
2160 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2161 GLOBAL_ATU_DATA_STATE_UNUSED);
2162 mutex_unlock(&chip->reg_lock);
2167 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2168 struct mv88e6xxx_atu_entry *entry)
2170 struct mv88e6xxx_atu_entry next = { 0 };
2176 err = _mv88e6xxx_atu_wait(chip);
2180 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2184 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2188 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2192 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2193 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2194 unsigned int mask, shift;
2196 if (val & GLOBAL_ATU_DATA_TRUNK) {
2198 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2199 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2202 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2203 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2206 next.portv_trunkid = (val & mask) >> shift;
2213 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2214 u16 fid, u16 vid, int port,
2215 struct switchdev_obj *obj,
2216 int (*cb)(struct switchdev_obj *obj))
2218 struct mv88e6xxx_atu_entry addr = {
2219 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2223 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2228 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2232 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2235 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2238 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2239 struct switchdev_obj_port_fdb *fdb;
2241 if (!is_unicast_ether_addr(addr.mac))
2244 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2246 ether_addr_copy(fdb->addr, addr.mac);
2247 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2248 fdb->ndm_state = NUD_NOARP;
2250 fdb->ndm_state = NUD_REACHABLE;
2251 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2252 struct switchdev_obj_port_mdb *mdb;
2254 if (!is_multicast_ether_addr(addr.mac))
2257 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2259 ether_addr_copy(mdb->addr, addr.mac);
2267 } while (!is_broadcast_ether_addr(addr.mac));
2272 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2273 struct switchdev_obj *obj,
2274 int (*cb)(struct switchdev_obj *obj))
2276 struct mv88e6xxx_vtu_entry vlan = {
2277 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2282 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2283 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2287 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2291 /* Dump VLANs' Filtering Information Databases */
2292 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2297 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2304 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2308 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2313 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2314 struct switchdev_obj_port_fdb *fdb,
2315 int (*cb)(struct switchdev_obj *obj))
2317 struct mv88e6xxx_chip *chip = ds->priv;
2320 mutex_lock(&chip->reg_lock);
2321 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2322 mutex_unlock(&chip->reg_lock);
2327 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2328 struct net_device *bridge)
2330 struct mv88e6xxx_chip *chip = ds->priv;
2333 mutex_lock(&chip->reg_lock);
2335 /* Assign the bridge and remap each port's VLANTable */
2336 chip->ports[port].bridge_dev = bridge;
2338 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2339 if (chip->ports[i].bridge_dev == bridge) {
2340 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2346 mutex_unlock(&chip->reg_lock);
2351 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2353 struct mv88e6xxx_chip *chip = ds->priv;
2354 struct net_device *bridge = chip->ports[port].bridge_dev;
2357 mutex_lock(&chip->reg_lock);
2359 /* Unassign the bridge and remap each port's VLANTable */
2360 chip->ports[port].bridge_dev = NULL;
2362 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2363 if (i == port || chip->ports[i].bridge_dev == bridge)
2364 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2365 netdev_warn(ds->ports[i].netdev,
2366 "failed to remap\n");
2368 mutex_unlock(&chip->reg_lock);
2371 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2373 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2374 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2375 struct gpio_desc *gpiod = chip->reset;
2376 unsigned long timeout;
2381 /* Set all ports to the disabled state. */
2382 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2383 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, ®);
2387 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2393 /* Wait for transmit queues to drain. */
2394 usleep_range(2000, 4000);
2396 /* If there is a gpio connected to the reset pin, toggle it */
2398 gpiod_set_value_cansleep(gpiod, 1);
2399 usleep_range(10000, 20000);
2400 gpiod_set_value_cansleep(gpiod, 0);
2401 usleep_range(10000, 20000);
2404 /* Reset the switch. Keep the PPU active if requested. The PPU
2405 * needs to be active to support indirect phy register access
2406 * through global registers 0x18 and 0x19.
2409 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2411 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2415 /* Wait up to one second for reset to complete. */
2416 timeout = jiffies + 1 * HZ;
2417 while (time_before(jiffies, timeout)) {
2418 err = mv88e6xxx_g1_read(chip, 0x00, ®);
2422 if ((reg & is_reset) == is_reset)
2424 usleep_range(1000, 2000);
2426 if (time_after(jiffies, timeout))
2434 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2439 /* Clear Power Down bit */
2440 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2444 if (val & BMCR_PDOWN) {
2446 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2452 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2454 struct dsa_switch *ds = chip->ds;
2458 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2459 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2460 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2461 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2462 /* MAC Forcing register: don't force link, speed,
2463 * duplex or flow control state to any particular
2464 * values on physical ports, but force the CPU port
2465 * and all DSA ports to their maximum bandwidth and
2468 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
2469 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2470 reg &= ~PORT_PCS_CTRL_UNFORCED;
2471 reg |= PORT_PCS_CTRL_FORCE_LINK |
2472 PORT_PCS_CTRL_LINK_UP |
2473 PORT_PCS_CTRL_DUPLEX_FULL |
2474 PORT_PCS_CTRL_FORCE_DUPLEX;
2475 if (mv88e6xxx_6065_family(chip))
2476 reg |= PORT_PCS_CTRL_100;
2478 reg |= PORT_PCS_CTRL_1000;
2480 reg |= PORT_PCS_CTRL_UNFORCED;
2483 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2488 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2489 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2490 * tunneling, determine priority by looking at 802.1p and IP
2491 * priority fields (IP prio has precedence), and set STP state
2494 * If this is the CPU link, use DSA or EDSA tagging depending
2495 * on which tagging mode was configured.
2497 * If this is a link to another switch, use DSA tagging mode.
2499 * If this is the upstream port for this switch, enable
2500 * forwarding of unknown unicasts and multicasts.
2503 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2504 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2505 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2506 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2507 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2508 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2509 PORT_CONTROL_STATE_FORWARDING;
2510 if (dsa_is_cpu_port(ds, port)) {
2511 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2512 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2513 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2515 reg |= PORT_CONTROL_DSA_TAG;
2516 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2517 PORT_CONTROL_FORWARD_UNKNOWN;
2519 if (dsa_is_dsa_port(ds, port)) {
2520 if (mv88e6xxx_6095_family(chip) ||
2521 mv88e6xxx_6185_family(chip))
2522 reg |= PORT_CONTROL_DSA_TAG;
2523 if (mv88e6xxx_6352_family(chip) ||
2524 mv88e6xxx_6351_family(chip) ||
2525 mv88e6xxx_6165_family(chip) ||
2526 mv88e6xxx_6097_family(chip) ||
2527 mv88e6xxx_6320_family(chip)) {
2528 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2531 if (port == dsa_upstream_port(ds))
2532 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2533 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2536 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2541 /* If this port is connected to a SerDes, make sure the SerDes is not
2544 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2545 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
2548 reg &= PORT_STATUS_CMODE_MASK;
2549 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2550 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2551 (reg == PORT_STATUS_CMODE_SGMII)) {
2552 err = mv88e6xxx_serdes_power_on(chip);
2558 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2559 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2560 * untagged frames on this port, do a destination address lookup on all
2561 * received packets as usual, disable ARP mirroring and don't send a
2562 * copy of all transmitted/received frames on this port to the CPU.
2565 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2566 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2567 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2568 mv88e6xxx_6185_family(chip))
2569 reg = PORT_CONTROL_2_MAP_DA;
2571 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2572 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2573 reg |= PORT_CONTROL_2_JUMBO_10240;
2575 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2576 /* Set the upstream port this port should use */
2577 reg |= dsa_upstream_port(ds);
2578 /* enable forwarding of unknown multicast addresses to
2581 if (port == dsa_upstream_port(ds))
2582 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2585 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2588 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2593 /* Port Association Vector: when learning source addresses
2594 * of packets, add the address to the address database using
2595 * a port bitmap that has only the bit for this port set and
2596 * the other bits clear.
2599 /* Disable learning for CPU port */
2600 if (dsa_is_cpu_port(ds, port))
2603 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2607 /* Egress rate control 2: disable egress rate control. */
2608 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2612 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2613 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2614 mv88e6xxx_6320_family(chip)) {
2615 /* Do not limit the period of time that this port can
2616 * be paused for by the remote end or the period of
2617 * time that this port can pause the remote end.
2619 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2623 /* Port ATU control: disable limiting the number of
2624 * address database entries that this port is allowed
2627 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2629 /* Priority Override: disable DA, SA and VTU priority
2632 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2637 /* Port Ethertype: use the Ethertype DSA Ethertype
2640 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2641 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2647 /* Tag Remap: use an identity 802.1p prio -> switch
2650 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2655 /* Tag Remap 2: use an identity 802.1p prio -> switch
2658 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2664 /* Rate Control: disable ingress rate limiting. */
2665 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2666 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2667 mv88e6xxx_6320_family(chip)) {
2668 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2672 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2673 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2679 /* Port Control 1: disable trunking, disable sending
2680 * learning messages to this port.
2682 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2686 /* Port based VLAN map: give each port the same default address
2687 * database, and allow bidirectional communication between the
2688 * CPU and DSA port(s), and the other ports.
2690 err = _mv88e6xxx_port_fid_set(chip, port, 0);
2694 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2698 /* Default VLAN ID and priority: don't set a default VLAN
2699 * ID, and set the default packet priority to zero.
2701 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2704 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2708 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2712 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2716 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2723 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2726 const unsigned int coeff = chip->info->age_time_coeff;
2727 const unsigned int min = 0x01 * coeff;
2728 const unsigned int max = 0xff * coeff;
2733 if (msecs < min || msecs > max)
2736 /* Round to nearest multiple of coeff */
2737 age_time = (msecs + coeff / 2) / coeff;
2739 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2743 /* AgeTime is 11:4 bits */
2745 val |= age_time << 4;
2747 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2750 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2751 unsigned int ageing_time)
2753 struct mv88e6xxx_chip *chip = ds->priv;
2756 mutex_lock(&chip->reg_lock);
2757 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2758 mutex_unlock(&chip->reg_lock);
2763 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2765 struct dsa_switch *ds = chip->ds;
2766 u32 upstream_port = dsa_upstream_port(ds);
2770 /* Enable the PHY Polling Unit if present, don't discard any packets,
2771 * and mask all interrupt sources.
2774 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2775 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2776 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2778 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2782 /* Configure the upstream port, and configure it as the port to which
2783 * ingress and egress and ARP monitor frames are to be sent.
2785 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2786 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2787 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2788 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2792 /* Disable remote management, and set the switch's DSA device number. */
2793 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2794 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2795 (ds->index & 0x1f));
2799 /* Clear all the VTU and STU entries */
2800 err = _mv88e6xxx_vtu_stu_flush(chip);
2804 /* Set the default address aging time to 5 minutes, and
2805 * enable address learn messages to be sent to all message
2808 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2809 GLOBAL_ATU_CONTROL_LEARN2ALL);
2813 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2817 /* Clear all ATU entries */
2818 err = _mv88e6xxx_atu_flush(chip, 0, true);
2822 /* Configure the IP ToS mapping registers. */
2823 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2826 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2829 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2835 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2838 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2841 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2844 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2848 /* Configure the IEEE 802.1p priority mapping register. */
2849 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2853 /* Clear the statistics counters for all ports */
2854 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2855 GLOBAL_STATS_OP_FLUSH_ALL);
2859 /* Wait for the flush to complete. */
2860 err = _mv88e6xxx_stats_wait(chip);
2867 static int mv88e6xxx_setup(struct dsa_switch *ds)
2869 struct mv88e6xxx_chip *chip = ds->priv;
2874 ds->slave_mii_bus = chip->mdio_bus;
2876 mutex_lock(&chip->reg_lock);
2878 err = mv88e6xxx_switch_reset(chip);
2882 /* Setup Switch Port Registers */
2883 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2884 err = mv88e6xxx_setup_port(chip, i);
2889 /* Setup Switch Global 1 Registers */
2890 err = mv88e6xxx_g1_setup(chip);
2894 /* Setup Switch Global 2 Registers */
2895 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2896 err = mv88e6xxx_g2_setup(chip);
2902 mutex_unlock(&chip->reg_lock);
2907 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2909 struct mv88e6xxx_chip *chip = ds->priv;
2912 if (!chip->info->ops->set_switch_mac)
2915 mutex_lock(&chip->reg_lock);
2916 err = chip->info->ops->set_switch_mac(chip, addr);
2917 mutex_unlock(&chip->reg_lock);
2922 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2924 struct mv88e6xxx_chip *chip = bus->priv;
2928 if (phy >= mv88e6xxx_num_ports(chip))
2931 mutex_lock(&chip->reg_lock);
2932 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2933 mutex_unlock(&chip->reg_lock);
2935 return err ? err : val;
2938 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2940 struct mv88e6xxx_chip *chip = bus->priv;
2943 if (phy >= mv88e6xxx_num_ports(chip))
2946 mutex_lock(&chip->reg_lock);
2947 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2948 mutex_unlock(&chip->reg_lock);
2953 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2954 struct device_node *np)
2957 struct mii_bus *bus;
2961 chip->mdio_np = of_get_child_by_name(np, "mdio");
2963 bus = devm_mdiobus_alloc(chip->dev);
2967 bus->priv = (void *)chip;
2969 bus->name = np->full_name;
2970 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2972 bus->name = "mv88e6xxx SMI";
2973 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2976 bus->read = mv88e6xxx_mdio_read;
2977 bus->write = mv88e6xxx_mdio_write;
2978 bus->parent = chip->dev;
2981 err = of_mdiobus_register(bus, chip->mdio_np);
2983 err = mdiobus_register(bus);
2985 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2988 chip->mdio_bus = bus;
2994 of_node_put(chip->mdio_np);
2999 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3002 struct mii_bus *bus = chip->mdio_bus;
3004 mdiobus_unregister(bus);
3007 of_node_put(chip->mdio_np);
3010 #ifdef CONFIG_NET_DSA_HWMON
3012 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3014 struct mv88e6xxx_chip *chip = ds->priv;
3020 mutex_lock(&chip->reg_lock);
3022 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3026 /* Enable temperature sensor */
3027 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3031 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3035 /* Wait for temperature to stabilize */
3036 usleep_range(10000, 12000);
3038 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3042 /* Disable temperature sensor */
3043 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3047 *temp = ((val & 0x1f) - 5) * 5;
3050 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3051 mutex_unlock(&chip->reg_lock);
3055 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3057 struct mv88e6xxx_chip *chip = ds->priv;
3058 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3064 mutex_lock(&chip->reg_lock);
3065 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3066 mutex_unlock(&chip->reg_lock);
3070 *temp = (val & 0xff) - 25;
3075 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3077 struct mv88e6xxx_chip *chip = ds->priv;
3079 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3082 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3083 return mv88e63xx_get_temp(ds, temp);
3085 return mv88e61xx_get_temp(ds, temp);
3088 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3090 struct mv88e6xxx_chip *chip = ds->priv;
3091 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3095 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3100 mutex_lock(&chip->reg_lock);
3101 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3102 mutex_unlock(&chip->reg_lock);
3106 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3111 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3113 struct mv88e6xxx_chip *chip = ds->priv;
3114 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3118 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3121 mutex_lock(&chip->reg_lock);
3122 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3125 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3126 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3127 (val & 0xe0ff) | (temp << 8));
3129 mutex_unlock(&chip->reg_lock);
3134 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3136 struct mv88e6xxx_chip *chip = ds->priv;
3137 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3141 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3146 mutex_lock(&chip->reg_lock);
3147 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3148 mutex_unlock(&chip->reg_lock);
3152 *alarm = !!(val & 0x40);
3156 #endif /* CONFIG_NET_DSA_HWMON */
3158 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3160 struct mv88e6xxx_chip *chip = ds->priv;
3162 return chip->eeprom_len;
3165 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3166 struct ethtool_eeprom *eeprom, u8 *data)
3168 struct mv88e6xxx_chip *chip = ds->priv;
3171 if (!chip->info->ops->get_eeprom)
3174 mutex_lock(&chip->reg_lock);
3175 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3176 mutex_unlock(&chip->reg_lock);
3181 eeprom->magic = 0xc3ec4951;
3186 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3187 struct ethtool_eeprom *eeprom, u8 *data)
3189 struct mv88e6xxx_chip *chip = ds->priv;
3192 if (!chip->info->ops->set_eeprom)
3195 if (eeprom->magic != 0xc3ec4951)
3198 mutex_lock(&chip->reg_lock);
3199 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3200 mutex_unlock(&chip->reg_lock);
3205 static const struct mv88e6xxx_ops mv88e6085_ops = {
3206 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3207 .phy_read = mv88e6xxx_phy_ppu_read,
3208 .phy_write = mv88e6xxx_phy_ppu_write,
3211 static const struct mv88e6xxx_ops mv88e6095_ops = {
3212 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3213 .phy_read = mv88e6xxx_phy_ppu_read,
3214 .phy_write = mv88e6xxx_phy_ppu_write,
3217 static const struct mv88e6xxx_ops mv88e6123_ops = {
3218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3219 .phy_read = mv88e6xxx_read,
3220 .phy_write = mv88e6xxx_write,
3223 static const struct mv88e6xxx_ops mv88e6131_ops = {
3224 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3225 .phy_read = mv88e6xxx_phy_ppu_read,
3226 .phy_write = mv88e6xxx_phy_ppu_write,
3229 static const struct mv88e6xxx_ops mv88e6161_ops = {
3230 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3231 .phy_read = mv88e6xxx_read,
3232 .phy_write = mv88e6xxx_write,
3235 static const struct mv88e6xxx_ops mv88e6165_ops = {
3236 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3237 .phy_read = mv88e6xxx_read,
3238 .phy_write = mv88e6xxx_write,
3241 static const struct mv88e6xxx_ops mv88e6171_ops = {
3242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3243 .phy_read = mv88e6xxx_g2_smi_phy_read,
3244 .phy_write = mv88e6xxx_g2_smi_phy_write,
3247 static const struct mv88e6xxx_ops mv88e6172_ops = {
3248 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3249 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3250 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3251 .phy_read = mv88e6xxx_g2_smi_phy_read,
3252 .phy_write = mv88e6xxx_g2_smi_phy_write,
3255 static const struct mv88e6xxx_ops mv88e6175_ops = {
3256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3257 .phy_read = mv88e6xxx_g2_smi_phy_read,
3258 .phy_write = mv88e6xxx_g2_smi_phy_write,
3261 static const struct mv88e6xxx_ops mv88e6176_ops = {
3262 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3263 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3265 .phy_read = mv88e6xxx_g2_smi_phy_read,
3266 .phy_write = mv88e6xxx_g2_smi_phy_write,
3269 static const struct mv88e6xxx_ops mv88e6185_ops = {
3270 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3271 .phy_read = mv88e6xxx_phy_ppu_read,
3272 .phy_write = mv88e6xxx_phy_ppu_write,
3275 static const struct mv88e6xxx_ops mv88e6240_ops = {
3276 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3277 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3279 .phy_read = mv88e6xxx_g2_smi_phy_read,
3280 .phy_write = mv88e6xxx_g2_smi_phy_write,
3283 static const struct mv88e6xxx_ops mv88e6320_ops = {
3284 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3285 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3286 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3287 .phy_read = mv88e6xxx_g2_smi_phy_read,
3288 .phy_write = mv88e6xxx_g2_smi_phy_write,
3291 static const struct mv88e6xxx_ops mv88e6321_ops = {
3292 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3293 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3295 .phy_read = mv88e6xxx_g2_smi_phy_read,
3296 .phy_write = mv88e6xxx_g2_smi_phy_write,
3299 static const struct mv88e6xxx_ops mv88e6350_ops = {
3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3301 .phy_read = mv88e6xxx_g2_smi_phy_read,
3302 .phy_write = mv88e6xxx_g2_smi_phy_write,
3305 static const struct mv88e6xxx_ops mv88e6351_ops = {
3306 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3307 .phy_read = mv88e6xxx_g2_smi_phy_read,
3308 .phy_write = mv88e6xxx_g2_smi_phy_write,
3311 static const struct mv88e6xxx_ops mv88e6352_ops = {
3312 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3313 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3315 .phy_read = mv88e6xxx_g2_smi_phy_read,
3316 .phy_write = mv88e6xxx_g2_smi_phy_write,
3319 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3321 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3322 .family = MV88E6XXX_FAMILY_6097,
3323 .name = "Marvell 88E6085",
3324 .num_databases = 4096,
3326 .port_base_addr = 0x10,
3327 .global1_addr = 0x1b,
3328 .age_time_coeff = 15000,
3329 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3330 .ops = &mv88e6085_ops,
3334 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3335 .family = MV88E6XXX_FAMILY_6095,
3336 .name = "Marvell 88E6095/88E6095F",
3337 .num_databases = 256,
3339 .port_base_addr = 0x10,
3340 .global1_addr = 0x1b,
3341 .age_time_coeff = 15000,
3342 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3343 .ops = &mv88e6095_ops,
3347 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3348 .family = MV88E6XXX_FAMILY_6165,
3349 .name = "Marvell 88E6123",
3350 .num_databases = 4096,
3352 .port_base_addr = 0x10,
3353 .global1_addr = 0x1b,
3354 .age_time_coeff = 15000,
3355 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3356 .ops = &mv88e6123_ops,
3360 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3361 .family = MV88E6XXX_FAMILY_6185,
3362 .name = "Marvell 88E6131",
3363 .num_databases = 256,
3365 .port_base_addr = 0x10,
3366 .global1_addr = 0x1b,
3367 .age_time_coeff = 15000,
3368 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3369 .ops = &mv88e6131_ops,
3373 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3374 .family = MV88E6XXX_FAMILY_6165,
3375 .name = "Marvell 88E6161",
3376 .num_databases = 4096,
3378 .port_base_addr = 0x10,
3379 .global1_addr = 0x1b,
3380 .age_time_coeff = 15000,
3381 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3382 .ops = &mv88e6161_ops,
3386 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3387 .family = MV88E6XXX_FAMILY_6165,
3388 .name = "Marvell 88E6165",
3389 .num_databases = 4096,
3391 .port_base_addr = 0x10,
3392 .global1_addr = 0x1b,
3393 .age_time_coeff = 15000,
3394 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3395 .ops = &mv88e6165_ops,
3399 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3400 .family = MV88E6XXX_FAMILY_6351,
3401 .name = "Marvell 88E6171",
3402 .num_databases = 4096,
3404 .port_base_addr = 0x10,
3405 .global1_addr = 0x1b,
3406 .age_time_coeff = 15000,
3407 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3408 .ops = &mv88e6171_ops,
3412 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3413 .family = MV88E6XXX_FAMILY_6352,
3414 .name = "Marvell 88E6172",
3415 .num_databases = 4096,
3417 .port_base_addr = 0x10,
3418 .global1_addr = 0x1b,
3419 .age_time_coeff = 15000,
3420 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3421 .ops = &mv88e6172_ops,
3425 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3426 .family = MV88E6XXX_FAMILY_6351,
3427 .name = "Marvell 88E6175",
3428 .num_databases = 4096,
3430 .port_base_addr = 0x10,
3431 .global1_addr = 0x1b,
3432 .age_time_coeff = 15000,
3433 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3434 .ops = &mv88e6175_ops,
3438 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3439 .family = MV88E6XXX_FAMILY_6352,
3440 .name = "Marvell 88E6176",
3441 .num_databases = 4096,
3443 .port_base_addr = 0x10,
3444 .global1_addr = 0x1b,
3445 .age_time_coeff = 15000,
3446 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3447 .ops = &mv88e6176_ops,
3451 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3452 .family = MV88E6XXX_FAMILY_6185,
3453 .name = "Marvell 88E6185",
3454 .num_databases = 256,
3456 .port_base_addr = 0x10,
3457 .global1_addr = 0x1b,
3458 .age_time_coeff = 15000,
3459 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3460 .ops = &mv88e6185_ops,
3464 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3465 .family = MV88E6XXX_FAMILY_6352,
3466 .name = "Marvell 88E6240",
3467 .num_databases = 4096,
3469 .port_base_addr = 0x10,
3470 .global1_addr = 0x1b,
3471 .age_time_coeff = 15000,
3472 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3473 .ops = &mv88e6240_ops,
3477 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3478 .family = MV88E6XXX_FAMILY_6320,
3479 .name = "Marvell 88E6320",
3480 .num_databases = 4096,
3482 .port_base_addr = 0x10,
3483 .global1_addr = 0x1b,
3484 .age_time_coeff = 15000,
3485 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3486 .ops = &mv88e6320_ops,
3490 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3491 .family = MV88E6XXX_FAMILY_6320,
3492 .name = "Marvell 88E6321",
3493 .num_databases = 4096,
3495 .port_base_addr = 0x10,
3496 .global1_addr = 0x1b,
3497 .age_time_coeff = 15000,
3498 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3499 .ops = &mv88e6321_ops,
3503 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3504 .family = MV88E6XXX_FAMILY_6351,
3505 .name = "Marvell 88E6350",
3506 .num_databases = 4096,
3508 .port_base_addr = 0x10,
3509 .global1_addr = 0x1b,
3510 .age_time_coeff = 15000,
3511 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3512 .ops = &mv88e6350_ops,
3516 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3517 .family = MV88E6XXX_FAMILY_6351,
3518 .name = "Marvell 88E6351",
3519 .num_databases = 4096,
3521 .port_base_addr = 0x10,
3522 .global1_addr = 0x1b,
3523 .age_time_coeff = 15000,
3524 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3525 .ops = &mv88e6351_ops,
3529 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3530 .family = MV88E6XXX_FAMILY_6352,
3531 .name = "Marvell 88E6352",
3532 .num_databases = 4096,
3534 .port_base_addr = 0x10,
3535 .global1_addr = 0x1b,
3536 .age_time_coeff = 15000,
3537 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3538 .ops = &mv88e6352_ops,
3542 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3546 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3547 if (mv88e6xxx_table[i].prod_num == prod_num)
3548 return &mv88e6xxx_table[i];
3553 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3555 const struct mv88e6xxx_info *info;
3556 unsigned int prod_num, rev;
3560 mutex_lock(&chip->reg_lock);
3561 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3562 mutex_unlock(&chip->reg_lock);
3566 prod_num = (id & 0xfff0) >> 4;
3569 info = mv88e6xxx_lookup_info(prod_num);
3573 /* Update the compatible info with the probed one */
3576 err = mv88e6xxx_g2_require(chip);
3580 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3581 chip->info->prod_num, chip->info->name, rev);
3586 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3588 struct mv88e6xxx_chip *chip;
3590 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3596 mutex_init(&chip->reg_lock);
3601 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3603 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3604 mv88e6xxx_ppu_state_init(chip);
3607 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3609 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3610 mv88e6xxx_ppu_state_destroy(chip);
3613 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3614 struct mii_bus *bus, int sw_addr)
3616 /* ADDR[0] pin is unavailable externally and considered zero */
3621 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3622 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3623 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3628 chip->sw_addr = sw_addr;
3633 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3635 struct mv88e6xxx_chip *chip = ds->priv;
3637 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3638 return DSA_TAG_PROTO_EDSA;
3640 return DSA_TAG_PROTO_DSA;
3643 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3644 struct device *host_dev, int sw_addr,
3647 struct mv88e6xxx_chip *chip;
3648 struct mii_bus *bus;
3651 bus = dsa_host_dev_to_mii_bus(host_dev);
3655 chip = mv88e6xxx_alloc_chip(dsa_dev);
3659 /* Legacy SMI probing will only support chips similar to 88E6085 */
3660 chip->info = &mv88e6xxx_table[MV88E6085];
3662 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3666 err = mv88e6xxx_detect(chip);
3670 mv88e6xxx_phy_init(chip);
3672 err = mv88e6xxx_mdio_register(chip, NULL);
3678 return chip->info->name;
3680 devm_kfree(dsa_dev, chip);
3685 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3686 const struct switchdev_obj_port_mdb *mdb,
3687 struct switchdev_trans *trans)
3689 /* We don't need any dynamic resource from the kernel (yet),
3690 * so skip the prepare phase.
3696 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3697 const struct switchdev_obj_port_mdb *mdb,
3698 struct switchdev_trans *trans)
3700 struct mv88e6xxx_chip *chip = ds->priv;
3702 mutex_lock(&chip->reg_lock);
3703 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3704 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3705 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3706 mutex_unlock(&chip->reg_lock);
3709 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3710 const struct switchdev_obj_port_mdb *mdb)
3712 struct mv88e6xxx_chip *chip = ds->priv;
3715 mutex_lock(&chip->reg_lock);
3716 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3717 GLOBAL_ATU_DATA_STATE_UNUSED);
3718 mutex_unlock(&chip->reg_lock);
3723 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3724 struct switchdev_obj_port_mdb *mdb,
3725 int (*cb)(struct switchdev_obj *obj))
3727 struct mv88e6xxx_chip *chip = ds->priv;
3730 mutex_lock(&chip->reg_lock);
3731 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3732 mutex_unlock(&chip->reg_lock);
3737 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3738 .probe = mv88e6xxx_drv_probe,
3739 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3740 .setup = mv88e6xxx_setup,
3741 .set_addr = mv88e6xxx_set_addr,
3742 .adjust_link = mv88e6xxx_adjust_link,
3743 .get_strings = mv88e6xxx_get_strings,
3744 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3745 .get_sset_count = mv88e6xxx_get_sset_count,
3746 .set_eee = mv88e6xxx_set_eee,
3747 .get_eee = mv88e6xxx_get_eee,
3748 #ifdef CONFIG_NET_DSA_HWMON
3749 .get_temp = mv88e6xxx_get_temp,
3750 .get_temp_limit = mv88e6xxx_get_temp_limit,
3751 .set_temp_limit = mv88e6xxx_set_temp_limit,
3752 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3754 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3755 .get_eeprom = mv88e6xxx_get_eeprom,
3756 .set_eeprom = mv88e6xxx_set_eeprom,
3757 .get_regs_len = mv88e6xxx_get_regs_len,
3758 .get_regs = mv88e6xxx_get_regs,
3759 .set_ageing_time = mv88e6xxx_set_ageing_time,
3760 .port_bridge_join = mv88e6xxx_port_bridge_join,
3761 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3762 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3763 .port_fast_age = mv88e6xxx_port_fast_age,
3764 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3765 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3766 .port_vlan_add = mv88e6xxx_port_vlan_add,
3767 .port_vlan_del = mv88e6xxx_port_vlan_del,
3768 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3769 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3770 .port_fdb_add = mv88e6xxx_port_fdb_add,
3771 .port_fdb_del = mv88e6xxx_port_fdb_del,
3772 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3773 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3774 .port_mdb_add = mv88e6xxx_port_mdb_add,
3775 .port_mdb_del = mv88e6xxx_port_mdb_del,
3776 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3779 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3780 struct device_node *np)
3782 struct device *dev = chip->dev;
3783 struct dsa_switch *ds;
3785 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3791 ds->ops = &mv88e6xxx_switch_ops;
3793 dev_set_drvdata(dev, ds);
3795 return dsa_register_switch(ds, np);
3798 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3800 dsa_unregister_switch(chip->ds);
3803 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3805 struct device *dev = &mdiodev->dev;
3806 struct device_node *np = dev->of_node;
3807 const struct mv88e6xxx_info *compat_info;
3808 struct mv88e6xxx_chip *chip;
3812 compat_info = of_device_get_match_data(dev);
3816 chip = mv88e6xxx_alloc_chip(dev);
3820 chip->info = compat_info;
3822 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3826 err = mv88e6xxx_detect(chip);
3830 mv88e6xxx_phy_init(chip);
3832 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3833 if (IS_ERR(chip->reset))
3834 return PTR_ERR(chip->reset);
3836 if (chip->info->ops->get_eeprom &&
3837 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3838 chip->eeprom_len = eeprom_len;
3840 err = mv88e6xxx_mdio_register(chip, np);
3844 err = mv88e6xxx_register_switch(chip, np);
3846 mv88e6xxx_mdio_unregister(chip);
3850 usleep_range(1000, 2000);
3855 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3857 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3858 struct mv88e6xxx_chip *chip = ds->priv;
3860 mv88e6xxx_phy_destroy(chip);
3861 mv88e6xxx_unregister_switch(chip);
3862 mv88e6xxx_mdio_unregister(chip);
3865 static const struct of_device_id mv88e6xxx_of_match[] = {
3867 .compatible = "marvell,mv88e6085",
3868 .data = &mv88e6xxx_table[MV88E6085],
3873 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3875 static struct mdio_driver mv88e6xxx_driver = {
3876 .probe = mv88e6xxx_probe,
3877 .remove = mv88e6xxx_remove,
3879 .name = "mv88e6085",
3880 .of_match_table = mv88e6xxx_of_match,
3884 static int __init mv88e6xxx_init(void)
3886 register_switch_driver(&mv88e6xxx_switch_ops);
3887 return mdio_driver_register(&mv88e6xxx_driver);
3889 module_init(mv88e6xxx_init);
3891 static void __exit mv88e6xxx_cleanup(void)
3893 mdio_driver_unregister(&mv88e6xxx_driver);
3894 unregister_switch_driver(&mv88e6xxx_switch_ops);
3896 module_exit(mv88e6xxx_cleanup);
3898 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3899 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3900 MODULE_LICENSE("GPL");