2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
43 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 *val)
69 return chip->smi_ops->read(chip, addr, reg, val);
72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 val)
78 return chip->smi_ops->write(chip, addr, reg, val);
81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
82 int addr, int reg, u16 *val)
86 ret = mdiobus_read_nested(chip->bus, addr, reg);
95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
96 int addr, int reg, u16 val)
100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 for (i = 0; i < 16; i++) {
118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
122 if ((ret & SMI_CMD_BUSY) == 0)
129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
130 int addr, int reg, u16 *val)
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
139 /* Transmit the read command. */
140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
145 /* Wait for the read command to complete. */
146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161 int addr, int reg, u16 val)
165 /* Wait for the bus to become free. */
166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
170 /* Transmit the data to write. */
171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
175 /* Transmit the write command. */
176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
181 /* Wait for the write command to complete. */
182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
198 assert_reg_lock(chip);
200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
214 assert_reg_lock(chip);
216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
228 struct mv88e6xxx_mdio_bus *mdio_bus;
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 return mdio_bus->bus;
238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
243 chip->g1_irq.masked |= (1 << n);
246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
251 chip->g1_irq.masked &= ~(1 << n);
254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
264 mutex_lock(&chip->reg_lock);
265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
266 mutex_unlock(&chip->reg_lock);
272 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
273 if (reg & (1 << n)) {
274 sub_irq = irq_find_mapping(chip->g1_irq.domain,
276 handle_nested_irq(sub_irq);
281 mutex_lock(&chip->reg_lock);
282 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
287 mutex_unlock(&chip->reg_lock);
290 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
291 } while (reg & ctl1);
294 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
297 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
299 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
301 mutex_lock(&chip->reg_lock);
304 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
306 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
307 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
316 reg |= (~chip->g1_irq.masked & mask);
318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
323 mutex_unlock(&chip->reg_lock);
326 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
327 .name = "mv88e6xxx-g1",
328 .irq_mask = mv88e6xxx_g1_irq_mask,
329 .irq_unmask = mv88e6xxx_g1_irq_unmask,
330 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
331 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
334 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
336 irq_hw_number_t hwirq)
338 struct mv88e6xxx_chip *chip = d->host_data;
340 irq_set_chip_data(irq, d->host_data);
341 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
342 irq_set_noprobe(irq);
347 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
348 .map = mv88e6xxx_g1_irq_domain_map,
349 .xlate = irq_domain_xlate_twocell,
352 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
357 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
358 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
359 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
361 free_irq(chip->irq, chip);
363 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
364 virq = irq_find_mapping(chip->g1_irq.domain, irq);
365 irq_dispose_mapping(virq);
368 irq_domain_remove(chip->g1_irq.domain);
371 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
376 chip->g1_irq.nirqs = chip->info->g1_irqs;
377 chip->g1_irq.domain = irq_domain_add_simple(
378 NULL, chip->g1_irq.nirqs, 0,
379 &mv88e6xxx_g1_irq_domain_ops, chip);
380 if (!chip->g1_irq.domain)
383 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
384 irq_create_mapping(chip->g1_irq.domain, irq);
386 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
387 chip->g1_irq.masked = ~0;
389 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
393 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
395 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
399 /* Reading the interrupt status clears (most of) them */
400 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
404 err = request_threaded_irq(chip->irq, NULL,
405 mv88e6xxx_g1_irq_thread_fn,
406 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
407 dev_name(chip->dev), chip);
414 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
415 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
418 for (irq = 0; irq < 16; irq++) {
419 virq = irq_find_mapping(chip->g1_irq.domain, irq);
420 irq_dispose_mapping(virq);
423 irq_domain_remove(chip->g1_irq.domain);
428 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
432 for (i = 0; i < 16; i++) {
436 err = mv88e6xxx_read(chip, addr, reg, &val);
443 usleep_range(1000, 2000);
446 dev_err(chip->dev, "Timeout while waiting for switch\n");
450 /* Indirect write to single pointer-data register with an Update bit */
451 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
456 /* Wait until the previous operation is completed */
457 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
461 /* Set the Update bit to trigger a write operation */
462 val = BIT(15) | update;
464 return mv88e6xxx_write(chip, addr, reg, val);
467 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
468 int link, int speed, int duplex,
469 phy_interface_t mode)
473 if (!chip->info->ops->port_set_link)
476 /* Port's MAC control must not be changed unless the link is down */
477 err = chip->info->ops->port_set_link(chip, port, 0);
481 if (chip->info->ops->port_set_speed) {
482 err = chip->info->ops->port_set_speed(chip, port, speed);
483 if (err && err != -EOPNOTSUPP)
487 if (chip->info->ops->port_set_duplex) {
488 err = chip->info->ops->port_set_duplex(chip, port, duplex);
489 if (err && err != -EOPNOTSUPP)
493 if (chip->info->ops->port_set_rgmii_delay) {
494 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
495 if (err && err != -EOPNOTSUPP)
499 if (chip->info->ops->port_set_cmode) {
500 err = chip->info->ops->port_set_cmode(chip, port, mode);
501 if (err && err != -EOPNOTSUPP)
507 if (chip->info->ops->port_set_link(chip, port, link))
508 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
513 /* We expect the switch to perform auto negotiation if there is a real
514 * phy. However, in the case of a fixed link phy, we force the port
515 * settings from the fixed link settings.
517 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
518 struct phy_device *phydev)
520 struct mv88e6xxx_chip *chip = ds->priv;
523 if (!phy_is_pseudo_fixed_link(phydev))
526 mutex_lock(&chip->reg_lock);
527 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
528 phydev->duplex, phydev->interface);
529 mutex_unlock(&chip->reg_lock);
531 if (err && err != -EOPNOTSUPP)
532 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
535 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
537 if (!chip->info->ops->stats_snapshot)
540 return chip->info->ops->stats_snapshot(chip, port);
543 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
544 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
545 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
546 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
547 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
548 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
549 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
550 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
551 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
552 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
553 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
554 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
555 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
556 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
557 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
558 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
559 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
560 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
561 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
562 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
563 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
564 { "single", 4, 0x14, STATS_TYPE_BANK0, },
565 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
566 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
567 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
568 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
569 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
570 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
571 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
572 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
573 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
574 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
575 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
576 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
577 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
578 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
579 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
580 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
581 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
582 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
583 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
584 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
585 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
586 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
587 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
588 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
589 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
590 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
591 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
592 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
593 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
594 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
595 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
596 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
597 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
598 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
599 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
600 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
601 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
602 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
605 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
606 struct mv88e6xxx_hw_stat *s,
607 int port, u16 bank1_select,
617 case STATS_TYPE_PORT:
618 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
623 if (s->sizeof_stat == 4) {
624 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
627 low |= ((u32)reg) << 16;
630 case STATS_TYPE_BANK1:
633 case STATS_TYPE_BANK0:
634 reg |= s->reg | histogram;
635 mv88e6xxx_g1_stats_read(chip, reg, &low);
636 if (s->sizeof_stat == 8)
637 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
642 value = (((u64)high) << 32) | low;
646 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data, int types)
649 struct mv88e6xxx_hw_stat *stat;
652 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
653 stat = &mv88e6xxx_hw_stats[i];
654 if (stat->type & types) {
655 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
662 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
665 mv88e6xxx_stats_get_strings(chip, data,
666 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
669 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
672 mv88e6xxx_stats_get_strings(chip, data,
673 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
676 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
679 struct mv88e6xxx_chip *chip = ds->priv;
681 if (chip->info->ops->stats_get_strings)
682 chip->info->ops->stats_get_strings(chip, data);
685 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
688 struct mv88e6xxx_hw_stat *stat;
691 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
692 stat = &mv88e6xxx_hw_stats[i];
693 if (stat->type & types)
699 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
701 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
705 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
707 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
711 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
713 struct mv88e6xxx_chip *chip = ds->priv;
715 if (chip->info->ops->stats_get_sset_count)
716 return chip->info->ops->stats_get_sset_count(chip);
721 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
722 uint64_t *data, int types,
723 u16 bank1_select, u16 histogram)
725 struct mv88e6xxx_hw_stat *stat;
728 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
729 stat = &mv88e6xxx_hw_stats[i];
730 if (stat->type & types) {
731 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
739 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
742 return mv88e6xxx_stats_get_stats(chip, port, data,
743 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
744 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
747 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
750 return mv88e6xxx_stats_get_stats(chip, port, data,
751 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
752 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
753 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
756 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
759 return mv88e6xxx_stats_get_stats(chip, port, data,
760 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
761 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
765 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
768 if (chip->info->ops->stats_get_stats)
769 chip->info->ops->stats_get_stats(chip, port, data);
772 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
775 struct mv88e6xxx_chip *chip = ds->priv;
778 mutex_lock(&chip->reg_lock);
780 ret = mv88e6xxx_stats_snapshot(chip, port);
782 mutex_unlock(&chip->reg_lock);
786 mv88e6xxx_get_stats(chip, port, data);
788 mutex_unlock(&chip->reg_lock);
791 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
793 if (chip->info->ops->stats_set_histogram)
794 return chip->info->ops->stats_set_histogram(chip);
799 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
801 return 32 * sizeof(u16);
804 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
805 struct ethtool_regs *regs, void *_p)
807 struct mv88e6xxx_chip *chip = ds->priv;
815 memset(p, 0xff, 32 * sizeof(u16));
817 mutex_lock(&chip->reg_lock);
819 for (i = 0; i < 32; i++) {
821 err = mv88e6xxx_port_read(chip, port, i, ®);
826 mutex_unlock(&chip->reg_lock);
829 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
830 struct ethtool_eee *e)
832 /* Nothing to do on the port's MAC */
836 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
837 struct ethtool_eee *e)
839 /* Nothing to do on the port's MAC */
843 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
845 struct dsa_switch *ds = NULL;
846 struct net_device *br;
850 if (dev < DSA_MAX_SWITCHES)
851 ds = chip->ds->dst->ds[dev];
853 /* Prevent frames from unknown switch or port */
854 if (!ds || port >= ds->num_ports)
857 /* Frames from DSA links and CPU ports can egress any local port */
858 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
859 return mv88e6xxx_port_mask(chip);
861 br = ds->ports[port].bridge_dev;
864 /* Frames from user ports can egress any local DSA links and CPU ports,
865 * as well as any local member of their bridge group.
867 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
868 if (dsa_is_cpu_port(chip->ds, i) ||
869 dsa_is_dsa_port(chip->ds, i) ||
870 (br && chip->ds->ports[i].bridge_dev == br))
876 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
878 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
880 /* prevent frames from going back out of the port they came in on */
881 output_ports &= ~BIT(port);
883 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
886 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
889 struct mv88e6xxx_chip *chip = ds->priv;
892 mutex_lock(&chip->reg_lock);
893 err = mv88e6xxx_port_set_state(chip, port, state);
894 mutex_unlock(&chip->reg_lock);
897 dev_err(ds->dev, "p%d: failed to update state\n", port);
900 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
902 if (chip->info->ops->pot_clear)
903 return chip->info->ops->pot_clear(chip);
908 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
910 if (chip->info->ops->mgmt_rsvd2cpu)
911 return chip->info->ops->mgmt_rsvd2cpu(chip);
916 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
920 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
924 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
928 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
931 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
936 if (!chip->info->ops->irl_init_all)
939 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
940 /* Disable ingress rate limiting by resetting all per port
941 * ingress rate limit resources to their initial state.
943 err = chip->info->ops->irl_init_all(chip, port);
951 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
955 if (!mv88e6xxx_has_pvt(chip))
958 /* Skip the local source device, which uses in-chip port VLAN */
959 if (dev != chip->ds->index)
960 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
962 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
965 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
970 if (!mv88e6xxx_has_pvt(chip))
973 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
974 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
976 err = mv88e6xxx_g2_misc_4_bit_port(chip);
980 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
981 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
982 err = mv88e6xxx_pvt_map(chip, dev, port);
991 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
993 struct mv88e6xxx_chip *chip = ds->priv;
996 mutex_lock(&chip->reg_lock);
997 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
998 mutex_unlock(&chip->reg_lock);
1001 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1004 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1006 if (!chip->info->max_vid)
1009 return mv88e6xxx_g1_vtu_flush(chip);
1012 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1013 struct mv88e6xxx_vtu_entry *entry)
1015 if (!chip->info->ops->vtu_getnext)
1018 return chip->info->ops->vtu_getnext(chip, entry);
1021 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1022 struct mv88e6xxx_vtu_entry *entry)
1024 if (!chip->info->ops->vtu_loadpurge)
1027 return chip->info->ops->vtu_loadpurge(chip, entry);
1030 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1032 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1033 struct mv88e6xxx_vtu_entry vlan = {
1034 .vid = chip->info->max_vid,
1038 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1040 /* Set every FID bit used by the (un)bridged ports */
1041 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1042 err = mv88e6xxx_port_get_fid(chip, i, fid);
1046 set_bit(*fid, fid_bitmap);
1049 /* Set every FID bit used by the VLAN entries */
1051 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1058 set_bit(vlan.fid, fid_bitmap);
1059 } while (vlan.vid < chip->info->max_vid);
1061 /* The reset value 0x000 is used to indicate that multiple address
1062 * databases are not needed. Return the next positive available.
1064 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1065 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1068 /* Clear the database */
1069 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1072 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1073 struct mv88e6xxx_vtu_entry *entry, bool new)
1080 entry->vid = vid - 1;
1081 entry->valid = false;
1083 err = mv88e6xxx_vtu_getnext(chip, entry);
1087 if (entry->vid == vid && entry->valid)
1093 /* Initialize a fresh VLAN entry */
1094 memset(entry, 0, sizeof(*entry));
1095 entry->valid = true;
1098 /* Exclude all ports */
1099 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1101 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1103 return mv88e6xxx_atu_new(chip, &entry->fid);
1106 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1110 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1111 u16 vid_begin, u16 vid_end)
1113 struct mv88e6xxx_chip *chip = ds->priv;
1114 struct mv88e6xxx_vtu_entry vlan = {
1115 .vid = vid_begin - 1,
1119 /* DSA and CPU ports have to be members of multiple vlans */
1120 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1126 mutex_lock(&chip->reg_lock);
1129 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1136 if (vlan.vid > vid_end)
1139 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1140 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1143 if (!ds->ports[port].netdev)
1146 if (vlan.member[i] ==
1147 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1150 if (ds->ports[i].bridge_dev ==
1151 ds->ports[port].bridge_dev)
1152 break; /* same bridge, check next VLAN */
1154 if (!ds->ports[i].bridge_dev)
1157 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1159 netdev_name(ds->ports[i].bridge_dev));
1163 } while (vlan.vid < vid_end);
1166 mutex_unlock(&chip->reg_lock);
1171 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1172 bool vlan_filtering)
1174 struct mv88e6xxx_chip *chip = ds->priv;
1175 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1176 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1179 if (!chip->info->max_vid)
1182 mutex_lock(&chip->reg_lock);
1183 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1184 mutex_unlock(&chip->reg_lock);
1190 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1191 const struct switchdev_obj_port_vlan *vlan,
1192 struct switchdev_trans *trans)
1194 struct mv88e6xxx_chip *chip = ds->priv;
1197 if (!chip->info->max_vid)
1200 /* If the requested port doesn't belong to the same bridge as the VLAN
1201 * members, do not support it (yet) and fallback to software VLAN.
1203 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1208 /* We don't need any dynamic resource from the kernel (yet),
1209 * so skip the prepare phase.
1214 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1217 struct mv88e6xxx_vtu_entry vlan;
1220 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1224 vlan.member[port] = member;
1226 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1229 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1230 const struct switchdev_obj_port_vlan *vlan,
1231 struct switchdev_trans *trans)
1233 struct mv88e6xxx_chip *chip = ds->priv;
1234 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1235 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1239 if (!chip->info->max_vid)
1242 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1243 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1245 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1247 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1249 mutex_lock(&chip->reg_lock);
1251 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1252 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1253 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1254 vid, untagged ? 'u' : 't');
1256 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1257 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1260 mutex_unlock(&chip->reg_lock);
1263 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1266 struct mv88e6xxx_vtu_entry vlan;
1269 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1273 /* Tell switchdev if this VLAN is handled in software */
1274 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1277 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1279 /* keep the VLAN unless all ports are excluded */
1281 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1282 if (vlan.member[i] !=
1283 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1289 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1293 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1296 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1297 const struct switchdev_obj_port_vlan *vlan)
1299 struct mv88e6xxx_chip *chip = ds->priv;
1303 if (!chip->info->max_vid)
1306 mutex_lock(&chip->reg_lock);
1308 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1312 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1313 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1318 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1325 mutex_unlock(&chip->reg_lock);
1330 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1331 const unsigned char *addr, u16 vid,
1334 struct mv88e6xxx_vtu_entry vlan;
1335 struct mv88e6xxx_atu_entry entry;
1338 /* Null VLAN ID corresponds to the port private database */
1340 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1342 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1346 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1347 ether_addr_copy(entry.mac, addr);
1348 eth_addr_dec(entry.mac);
1350 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1354 /* Initialize a fresh ATU entry if it isn't found */
1355 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1356 !ether_addr_equal(entry.mac, addr)) {
1357 memset(&entry, 0, sizeof(entry));
1358 ether_addr_copy(entry.mac, addr);
1361 /* Purge the ATU entry only if no port is using it anymore */
1362 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1363 entry.portvec &= ~BIT(port);
1365 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1367 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1368 entry.portvec = BIT(port);
1370 entry.portvec |= BIT(port);
1372 entry.state = state;
1375 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1378 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1379 const unsigned char *addr, u16 vid)
1381 struct mv88e6xxx_chip *chip = ds->priv;
1384 mutex_lock(&chip->reg_lock);
1385 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1386 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1387 mutex_unlock(&chip->reg_lock);
1392 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1393 const unsigned char *addr, u16 vid)
1395 struct mv88e6xxx_chip *chip = ds->priv;
1398 mutex_lock(&chip->reg_lock);
1399 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1400 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1401 mutex_unlock(&chip->reg_lock);
1406 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1407 u16 fid, u16 vid, int port,
1408 dsa_fdb_dump_cb_t *cb, void *data)
1410 struct mv88e6xxx_atu_entry addr;
1414 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1415 eth_broadcast_addr(addr.mac);
1418 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1422 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1425 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1428 if (!is_unicast_ether_addr(addr.mac))
1431 is_static = (addr.state ==
1432 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1433 err = cb(addr.mac, vid, is_static, data);
1436 } while (!is_broadcast_ether_addr(addr.mac));
1441 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1442 dsa_fdb_dump_cb_t *cb, void *data)
1444 struct mv88e6xxx_vtu_entry vlan = {
1445 .vid = chip->info->max_vid,
1450 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1451 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1455 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1459 /* Dump VLANs' Filtering Information Databases */
1461 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1468 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1472 } while (vlan.vid < chip->info->max_vid);
1477 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1478 dsa_fdb_dump_cb_t *cb, void *data)
1480 struct mv88e6xxx_chip *chip = ds->priv;
1483 mutex_lock(&chip->reg_lock);
1484 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1485 mutex_unlock(&chip->reg_lock);
1490 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1491 struct net_device *br)
1493 struct dsa_switch *ds;
1498 /* Remap the Port VLAN of each local bridge group member */
1499 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1500 if (chip->ds->ports[port].bridge_dev == br) {
1501 err = mv88e6xxx_port_vlan_map(chip, port);
1507 if (!mv88e6xxx_has_pvt(chip))
1510 /* Remap the Port VLAN of each cross-chip bridge group member */
1511 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1512 ds = chip->ds->dst->ds[dev];
1516 for (port = 0; port < ds->num_ports; ++port) {
1517 if (ds->ports[port].bridge_dev == br) {
1518 err = mv88e6xxx_pvt_map(chip, dev, port);
1528 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1529 struct net_device *br)
1531 struct mv88e6xxx_chip *chip = ds->priv;
1534 mutex_lock(&chip->reg_lock);
1535 err = mv88e6xxx_bridge_map(chip, br);
1536 mutex_unlock(&chip->reg_lock);
1541 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1542 struct net_device *br)
1544 struct mv88e6xxx_chip *chip = ds->priv;
1546 mutex_lock(&chip->reg_lock);
1547 if (mv88e6xxx_bridge_map(chip, br) ||
1548 mv88e6xxx_port_vlan_map(chip, port))
1549 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1550 mutex_unlock(&chip->reg_lock);
1553 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1554 int port, struct net_device *br)
1556 struct mv88e6xxx_chip *chip = ds->priv;
1559 if (!mv88e6xxx_has_pvt(chip))
1562 mutex_lock(&chip->reg_lock);
1563 err = mv88e6xxx_pvt_map(chip, dev, port);
1564 mutex_unlock(&chip->reg_lock);
1569 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1570 int port, struct net_device *br)
1572 struct mv88e6xxx_chip *chip = ds->priv;
1574 if (!mv88e6xxx_has_pvt(chip))
1577 mutex_lock(&chip->reg_lock);
1578 if (mv88e6xxx_pvt_map(chip, dev, port))
1579 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1580 mutex_unlock(&chip->reg_lock);
1583 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1585 if (chip->info->ops->reset)
1586 return chip->info->ops->reset(chip);
1591 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1593 struct gpio_desc *gpiod = chip->reset;
1595 /* If there is a GPIO connected to the reset pin, toggle it */
1597 gpiod_set_value_cansleep(gpiod, 1);
1598 usleep_range(10000, 20000);
1599 gpiod_set_value_cansleep(gpiod, 0);
1600 usleep_range(10000, 20000);
1604 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1608 /* Set all ports to the Disabled state */
1609 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1610 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1615 /* Wait for transmit queues to drain,
1616 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1618 usleep_range(2000, 4000);
1623 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1627 err = mv88e6xxx_disable_ports(chip);
1631 mv88e6xxx_hardware_reset(chip);
1633 return mv88e6xxx_software_reset(chip);
1636 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1637 enum mv88e6xxx_frame_mode frame,
1638 enum mv88e6xxx_egress_mode egress, u16 etype)
1642 if (!chip->info->ops->port_set_frame_mode)
1645 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1649 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1653 if (chip->info->ops->port_set_ether_type)
1654 return chip->info->ops->port_set_ether_type(chip, port, etype);
1659 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1661 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1662 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1663 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1666 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1668 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1669 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1670 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1673 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1675 return mv88e6xxx_set_port_mode(chip, port,
1676 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1677 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1681 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1683 if (dsa_is_dsa_port(chip->ds, port))
1684 return mv88e6xxx_set_port_mode_dsa(chip, port);
1686 if (dsa_is_normal_port(chip->ds, port))
1687 return mv88e6xxx_set_port_mode_normal(chip, port);
1689 /* Setup CPU port mode depending on its supported tag format */
1690 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1691 return mv88e6xxx_set_port_mode_dsa(chip, port);
1693 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1694 return mv88e6xxx_set_port_mode_edsa(chip, port);
1699 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1701 bool message = dsa_is_dsa_port(chip->ds, port);
1703 return mv88e6xxx_port_set_message_port(chip, port, message);
1706 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1708 bool flood = port == dsa_upstream_port(chip->ds);
1710 /* Upstream ports flood frames with unknown unicast or multicast DA */
1711 if (chip->info->ops->port_set_egress_floods)
1712 return chip->info->ops->port_set_egress_floods(chip, port,
1718 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1721 if (chip->info->ops->serdes_power)
1722 return chip->info->ops->serdes_power(chip, port, on);
1727 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1729 struct dsa_switch *ds = chip->ds;
1733 /* MAC Forcing register: don't force link, speed, duplex or flow control
1734 * state to any particular values on physical ports, but force the CPU
1735 * port and all DSA ports to their maximum bandwidth and full duplex.
1737 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1738 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1739 SPEED_MAX, DUPLEX_FULL,
1740 PHY_INTERFACE_MODE_NA);
1742 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1743 SPEED_UNFORCED, DUPLEX_UNFORCED,
1744 PHY_INTERFACE_MODE_NA);
1748 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1749 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1750 * tunneling, determine priority by looking at 802.1p and IP
1751 * priority fields (IP prio has precedence), and set STP state
1754 * If this is the CPU link, use DSA or EDSA tagging depending
1755 * on which tagging mode was configured.
1757 * If this is a link to another switch, use DSA tagging mode.
1759 * If this is the upstream port for this switch, enable
1760 * forwarding of unknown unicasts and multicasts.
1762 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1763 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1764 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1765 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1769 err = mv88e6xxx_setup_port_mode(chip, port);
1773 err = mv88e6xxx_setup_egress_floods(chip, port);
1777 /* Enable the SERDES interface for DSA and CPU ports. Normal
1778 * ports SERDES are enabled when the port is enabled, thus
1779 * saving a bit of power.
1781 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1782 err = mv88e6xxx_serdes_power(chip, port, true);
1787 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1788 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1789 * untagged frames on this port, do a destination address lookup on all
1790 * received packets as usual, disable ARP mirroring and don't send a
1791 * copy of all transmitted/received frames on this port to the CPU.
1793 err = mv88e6xxx_port_set_map_da(chip, port);
1798 if (chip->info->ops->port_set_upstream_port) {
1799 err = chip->info->ops->port_set_upstream_port(
1800 chip, port, dsa_upstream_port(ds));
1805 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1806 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1810 if (chip->info->ops->port_set_jumbo_size) {
1811 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1816 /* Port Association Vector: when learning source addresses
1817 * of packets, add the address to the address database using
1818 * a port bitmap that has only the bit for this port set and
1819 * the other bits clear.
1822 /* Disable learning for CPU port */
1823 if (dsa_is_cpu_port(ds, port))
1826 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1831 /* Egress rate control 2: disable egress rate control. */
1832 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1837 if (chip->info->ops->port_pause_limit) {
1838 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1843 if (chip->info->ops->port_disable_learn_limit) {
1844 err = chip->info->ops->port_disable_learn_limit(chip, port);
1849 if (chip->info->ops->port_disable_pri_override) {
1850 err = chip->info->ops->port_disable_pri_override(chip, port);
1855 if (chip->info->ops->port_tag_remap) {
1856 err = chip->info->ops->port_tag_remap(chip, port);
1861 if (chip->info->ops->port_egress_rate_limiting) {
1862 err = chip->info->ops->port_egress_rate_limiting(chip, port);
1867 err = mv88e6xxx_setup_message_port(chip, port);
1871 /* Port based VLAN map: give each port the same default address
1872 * database, and allow bidirectional communication between the
1873 * CPU and DSA port(s), and the other ports.
1875 err = mv88e6xxx_port_set_fid(chip, port, 0);
1879 err = mv88e6xxx_port_vlan_map(chip, port);
1883 /* Default VLAN ID and priority: don't set a default VLAN
1884 * ID, and set the default packet priority to zero.
1886 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1889 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1890 struct phy_device *phydev)
1892 struct mv88e6xxx_chip *chip = ds->priv;
1895 mutex_lock(&chip->reg_lock);
1896 err = mv88e6xxx_serdes_power(chip, port, true);
1897 mutex_unlock(&chip->reg_lock);
1902 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1903 struct phy_device *phydev)
1905 struct mv88e6xxx_chip *chip = ds->priv;
1907 mutex_lock(&chip->reg_lock);
1908 if (mv88e6xxx_serdes_power(chip, port, false))
1909 dev_err(chip->dev, "failed to power off SERDES\n");
1910 mutex_unlock(&chip->reg_lock);
1913 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1914 unsigned int ageing_time)
1916 struct mv88e6xxx_chip *chip = ds->priv;
1919 mutex_lock(&chip->reg_lock);
1920 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1921 mutex_unlock(&chip->reg_lock);
1926 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1928 struct dsa_switch *ds = chip->ds;
1929 u32 upstream_port = dsa_upstream_port(ds);
1932 if (chip->info->ops->set_cpu_port) {
1933 err = chip->info->ops->set_cpu_port(chip, upstream_port);
1938 if (chip->info->ops->set_egress_port) {
1939 err = chip->info->ops->set_egress_port(chip, upstream_port);
1944 /* Disable remote management, and set the switch's DSA device number. */
1945 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
1946 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
1947 (ds->index & 0x1f));
1951 /* Configure the IP ToS mapping registers. */
1952 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
1955 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
1958 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
1961 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
1964 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
1967 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
1970 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
1973 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
1977 /* Configure the IEEE 802.1p priority mapping register. */
1978 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
1982 /* Initialize the statistics unit */
1983 err = mv88e6xxx_stats_set_histogram(chip);
1987 /* Clear the statistics counters for all ports */
1988 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
1989 MV88E6XXX_G1_STATS_OP_BUSY |
1990 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
1994 /* Wait for the flush to complete. */
1995 err = mv88e6xxx_g1_stats_wait(chip);
2002 /* The mv88e6390 has some hidden registers used for debug and
2003 * development. The errata also makes use of them.
2005 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2011 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2012 PORT_RESERVED_1A, val);
2016 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2017 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2020 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2021 PORT_RESERVED_1A, ctrl);
2024 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2026 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2027 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2031 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2037 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2038 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2041 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2042 PORT_RESERVED_1A, ctrl);
2046 err = mv88e6390_hidden_wait(chip);
2050 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2051 PORT_RESERVED_1A, val);
2054 /* Check if the errata has already been applied. */
2055 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2061 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2062 err = mv88e6390_hidden_read(chip, port, 0, &val);
2065 "Error reading hidden register: %d\n", err);
2075 /* The 6390 copper ports have an errata which require poking magic
2076 * values into undocumented hidden registers and then performing a
2079 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2084 if (mv88e6390_setup_errata_applied(chip))
2087 /* Set the ports into blocking mode */
2088 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2089 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2094 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2095 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2100 return mv88e6xxx_software_reset(chip);
2103 static int mv88e6xxx_setup(struct dsa_switch *ds)
2105 struct mv88e6xxx_chip *chip = ds->priv;
2110 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2112 mutex_lock(&chip->reg_lock);
2114 if (chip->info->ops->setup_errata) {
2115 err = chip->info->ops->setup_errata(chip);
2120 /* Setup Switch Port Registers */
2121 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2122 err = mv88e6xxx_setup_port(chip, i);
2127 /* Setup Switch Global 1 Registers */
2128 err = mv88e6xxx_g1_setup(chip);
2132 /* Setup Switch Global 2 Registers */
2133 if (chip->info->global2_addr) {
2134 err = mv88e6xxx_g2_setup(chip);
2139 err = mv88e6xxx_irl_setup(chip);
2143 err = mv88e6xxx_phy_setup(chip);
2147 err = mv88e6xxx_vtu_setup(chip);
2151 err = mv88e6xxx_pvt_setup(chip);
2155 err = mv88e6xxx_atu_setup(chip);
2159 err = mv88e6xxx_pot_setup(chip);
2163 err = mv88e6xxx_rsvd2cpu_setup(chip);
2168 mutex_unlock(&chip->reg_lock);
2173 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2175 struct mv88e6xxx_chip *chip = ds->priv;
2178 if (!chip->info->ops->set_switch_mac)
2181 mutex_lock(&chip->reg_lock);
2182 err = chip->info->ops->set_switch_mac(chip, addr);
2183 mutex_unlock(&chip->reg_lock);
2188 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2190 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2191 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2195 if (!chip->info->ops->phy_read)
2198 mutex_lock(&chip->reg_lock);
2199 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2200 mutex_unlock(&chip->reg_lock);
2202 if (reg == MII_PHYSID2) {
2203 /* Some internal PHYs don't have a model number. */
2204 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2205 /* Then there is the 6165 family. It gets is
2206 * PHYs correct. But it can also have two
2207 * SERDES interfaces in the PHY address
2208 * space. And these don't have a model
2209 * number. But they are not PHYs, so we don't
2210 * want to give them something a PHY driver
2213 * Use the mv88e6390 family model number
2214 * instead, for anything which really could be
2218 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2221 return err ? err : val;
2224 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2226 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2227 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2230 if (!chip->info->ops->phy_write)
2233 mutex_lock(&chip->reg_lock);
2234 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2235 mutex_unlock(&chip->reg_lock);
2240 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2241 struct device_node *np,
2245 struct mv88e6xxx_mdio_bus *mdio_bus;
2246 struct mii_bus *bus;
2249 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2253 mdio_bus = bus->priv;
2254 mdio_bus->bus = bus;
2255 mdio_bus->chip = chip;
2256 INIT_LIST_HEAD(&mdio_bus->list);
2257 mdio_bus->external = external;
2260 bus->name = np->full_name;
2261 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2263 bus->name = "mv88e6xxx SMI";
2264 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2267 bus->read = mv88e6xxx_mdio_read;
2268 bus->write = mv88e6xxx_mdio_write;
2269 bus->parent = chip->dev;
2272 err = of_mdiobus_register(bus, np);
2274 err = mdiobus_register(bus);
2276 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2281 list_add_tail(&mdio_bus->list, &chip->mdios);
2283 list_add(&mdio_bus->list, &chip->mdios);
2288 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2289 { .compatible = "marvell,mv88e6xxx-mdio-external",
2290 .data = (void *)true },
2294 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2297 struct mv88e6xxx_mdio_bus *mdio_bus;
2298 struct mii_bus *bus;
2300 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2301 bus = mdio_bus->bus;
2303 mdiobus_unregister(bus);
2307 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2308 struct device_node *np)
2310 const struct of_device_id *match;
2311 struct device_node *child;
2314 /* Always register one mdio bus for the internal/default mdio
2315 * bus. This maybe represented in the device tree, but is
2318 child = of_get_child_by_name(np, "mdio");
2319 err = mv88e6xxx_mdio_register(chip, child, false);
2324 /* Walk the device tree, and see if there are any other nodes
2325 * which say they are compatible with the external mdio
2328 for_each_available_child_of_node(np, child) {
2329 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2331 err = mv88e6xxx_mdio_register(chip, child, true);
2333 mv88e6xxx_mdios_unregister(chip);
2342 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2344 struct mv88e6xxx_chip *chip = ds->priv;
2346 return chip->eeprom_len;
2349 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2350 struct ethtool_eeprom *eeprom, u8 *data)
2352 struct mv88e6xxx_chip *chip = ds->priv;
2355 if (!chip->info->ops->get_eeprom)
2358 mutex_lock(&chip->reg_lock);
2359 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2360 mutex_unlock(&chip->reg_lock);
2365 eeprom->magic = 0xc3ec4951;
2370 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2371 struct ethtool_eeprom *eeprom, u8 *data)
2373 struct mv88e6xxx_chip *chip = ds->priv;
2376 if (!chip->info->ops->set_eeprom)
2379 if (eeprom->magic != 0xc3ec4951)
2382 mutex_lock(&chip->reg_lock);
2383 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2384 mutex_unlock(&chip->reg_lock);
2389 static const struct mv88e6xxx_ops mv88e6085_ops = {
2390 /* MV88E6XXX_FAMILY_6097 */
2391 .irl_init_all = mv88e6352_g2_irl_init_all,
2392 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2393 .phy_read = mv88e6185_phy_ppu_read,
2394 .phy_write = mv88e6185_phy_ppu_write,
2395 .port_set_link = mv88e6xxx_port_set_link,
2396 .port_set_duplex = mv88e6xxx_port_set_duplex,
2397 .port_set_speed = mv88e6185_port_set_speed,
2398 .port_tag_remap = mv88e6095_port_tag_remap,
2399 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2400 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2401 .port_set_ether_type = mv88e6351_port_set_ether_type,
2402 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2403 .port_pause_limit = mv88e6097_port_pause_limit,
2404 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2405 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2406 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2407 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2408 .stats_get_strings = mv88e6095_stats_get_strings,
2409 .stats_get_stats = mv88e6095_stats_get_stats,
2410 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2411 .set_egress_port = mv88e6095_g1_set_egress_port,
2412 .watchdog_ops = &mv88e6097_watchdog_ops,
2413 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2414 .pot_clear = mv88e6xxx_g2_pot_clear,
2415 .ppu_enable = mv88e6185_g1_ppu_enable,
2416 .ppu_disable = mv88e6185_g1_ppu_disable,
2417 .reset = mv88e6185_g1_reset,
2418 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2419 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2422 static const struct mv88e6xxx_ops mv88e6095_ops = {
2423 /* MV88E6XXX_FAMILY_6095 */
2424 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2425 .phy_read = mv88e6185_phy_ppu_read,
2426 .phy_write = mv88e6185_phy_ppu_write,
2427 .port_set_link = mv88e6xxx_port_set_link,
2428 .port_set_duplex = mv88e6xxx_port_set_duplex,
2429 .port_set_speed = mv88e6185_port_set_speed,
2430 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2431 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2432 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2433 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2434 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2435 .stats_get_strings = mv88e6095_stats_get_strings,
2436 .stats_get_stats = mv88e6095_stats_get_stats,
2437 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2438 .ppu_enable = mv88e6185_g1_ppu_enable,
2439 .ppu_disable = mv88e6185_g1_ppu_disable,
2440 .reset = mv88e6185_g1_reset,
2441 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2442 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2445 static const struct mv88e6xxx_ops mv88e6097_ops = {
2446 /* MV88E6XXX_FAMILY_6097 */
2447 .irl_init_all = mv88e6352_g2_irl_init_all,
2448 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2449 .phy_read = mv88e6xxx_g2_smi_phy_read,
2450 .phy_write = mv88e6xxx_g2_smi_phy_write,
2451 .port_set_link = mv88e6xxx_port_set_link,
2452 .port_set_duplex = mv88e6xxx_port_set_duplex,
2453 .port_set_speed = mv88e6185_port_set_speed,
2454 .port_tag_remap = mv88e6095_port_tag_remap,
2455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2456 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2457 .port_set_ether_type = mv88e6351_port_set_ether_type,
2458 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2459 .port_pause_limit = mv88e6097_port_pause_limit,
2460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2462 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2463 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2464 .stats_get_strings = mv88e6095_stats_get_strings,
2465 .stats_get_stats = mv88e6095_stats_get_stats,
2466 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2467 .set_egress_port = mv88e6095_g1_set_egress_port,
2468 .watchdog_ops = &mv88e6097_watchdog_ops,
2469 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2470 .pot_clear = mv88e6xxx_g2_pot_clear,
2471 .reset = mv88e6352_g1_reset,
2472 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2473 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2476 static const struct mv88e6xxx_ops mv88e6123_ops = {
2477 /* MV88E6XXX_FAMILY_6165 */
2478 .irl_init_all = mv88e6352_g2_irl_init_all,
2479 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2480 .phy_read = mv88e6xxx_g2_smi_phy_read,
2481 .phy_write = mv88e6xxx_g2_smi_phy_write,
2482 .port_set_link = mv88e6xxx_port_set_link,
2483 .port_set_duplex = mv88e6xxx_port_set_duplex,
2484 .port_set_speed = mv88e6185_port_set_speed,
2485 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2486 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2489 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2490 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2491 .stats_get_strings = mv88e6095_stats_get_strings,
2492 .stats_get_stats = mv88e6095_stats_get_stats,
2493 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2494 .set_egress_port = mv88e6095_g1_set_egress_port,
2495 .watchdog_ops = &mv88e6097_watchdog_ops,
2496 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2497 .pot_clear = mv88e6xxx_g2_pot_clear,
2498 .reset = mv88e6352_g1_reset,
2499 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2500 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2503 static const struct mv88e6xxx_ops mv88e6131_ops = {
2504 /* MV88E6XXX_FAMILY_6185 */
2505 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2506 .phy_read = mv88e6185_phy_ppu_read,
2507 .phy_write = mv88e6185_phy_ppu_write,
2508 .port_set_link = mv88e6xxx_port_set_link,
2509 .port_set_duplex = mv88e6xxx_port_set_duplex,
2510 .port_set_speed = mv88e6185_port_set_speed,
2511 .port_tag_remap = mv88e6095_port_tag_remap,
2512 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2513 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2514 .port_set_ether_type = mv88e6351_port_set_ether_type,
2515 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2516 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2517 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2518 .port_pause_limit = mv88e6097_port_pause_limit,
2519 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2520 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2521 .stats_get_strings = mv88e6095_stats_get_strings,
2522 .stats_get_stats = mv88e6095_stats_get_stats,
2523 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2524 .set_egress_port = mv88e6095_g1_set_egress_port,
2525 .watchdog_ops = &mv88e6097_watchdog_ops,
2526 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2527 .ppu_enable = mv88e6185_g1_ppu_enable,
2528 .ppu_disable = mv88e6185_g1_ppu_disable,
2529 .reset = mv88e6185_g1_reset,
2530 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2531 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2534 static const struct mv88e6xxx_ops mv88e6141_ops = {
2535 /* MV88E6XXX_FAMILY_6341 */
2536 .irl_init_all = mv88e6352_g2_irl_init_all,
2537 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2538 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2540 .phy_read = mv88e6xxx_g2_smi_phy_read,
2541 .phy_write = mv88e6xxx_g2_smi_phy_write,
2542 .port_set_link = mv88e6xxx_port_set_link,
2543 .port_set_duplex = mv88e6xxx_port_set_duplex,
2544 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2545 .port_set_speed = mv88e6341_port_set_speed,
2546 .port_tag_remap = mv88e6095_port_tag_remap,
2547 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2548 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2549 .port_set_ether_type = mv88e6351_port_set_ether_type,
2550 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2552 .port_pause_limit = mv88e6097_port_pause_limit,
2553 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2554 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2555 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2556 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2557 .stats_get_strings = mv88e6320_stats_get_strings,
2558 .stats_get_stats = mv88e6390_stats_get_stats,
2559 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2560 .set_egress_port = mv88e6390_g1_set_egress_port,
2561 .watchdog_ops = &mv88e6390_watchdog_ops,
2562 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2563 .pot_clear = mv88e6xxx_g2_pot_clear,
2564 .reset = mv88e6352_g1_reset,
2565 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2566 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2569 static const struct mv88e6xxx_ops mv88e6161_ops = {
2570 /* MV88E6XXX_FAMILY_6165 */
2571 .irl_init_all = mv88e6352_g2_irl_init_all,
2572 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2573 .phy_read = mv88e6xxx_g2_smi_phy_read,
2574 .phy_write = mv88e6xxx_g2_smi_phy_write,
2575 .port_set_link = mv88e6xxx_port_set_link,
2576 .port_set_duplex = mv88e6xxx_port_set_duplex,
2577 .port_set_speed = mv88e6185_port_set_speed,
2578 .port_tag_remap = mv88e6095_port_tag_remap,
2579 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2580 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2581 .port_set_ether_type = mv88e6351_port_set_ether_type,
2582 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2583 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2584 .port_pause_limit = mv88e6097_port_pause_limit,
2585 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2586 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2587 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2588 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2589 .stats_get_strings = mv88e6095_stats_get_strings,
2590 .stats_get_stats = mv88e6095_stats_get_stats,
2591 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2592 .set_egress_port = mv88e6095_g1_set_egress_port,
2593 .watchdog_ops = &mv88e6097_watchdog_ops,
2594 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2595 .pot_clear = mv88e6xxx_g2_pot_clear,
2596 .reset = mv88e6352_g1_reset,
2597 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2598 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2601 static const struct mv88e6xxx_ops mv88e6165_ops = {
2602 /* MV88E6XXX_FAMILY_6165 */
2603 .irl_init_all = mv88e6352_g2_irl_init_all,
2604 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2605 .phy_read = mv88e6165_phy_read,
2606 .phy_write = mv88e6165_phy_write,
2607 .port_set_link = mv88e6xxx_port_set_link,
2608 .port_set_duplex = mv88e6xxx_port_set_duplex,
2609 .port_set_speed = mv88e6185_port_set_speed,
2610 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2611 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2612 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2613 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2614 .stats_get_strings = mv88e6095_stats_get_strings,
2615 .stats_get_stats = mv88e6095_stats_get_stats,
2616 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2617 .set_egress_port = mv88e6095_g1_set_egress_port,
2618 .watchdog_ops = &mv88e6097_watchdog_ops,
2619 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2620 .pot_clear = mv88e6xxx_g2_pot_clear,
2621 .reset = mv88e6352_g1_reset,
2622 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2623 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2626 static const struct mv88e6xxx_ops mv88e6171_ops = {
2627 /* MV88E6XXX_FAMILY_6351 */
2628 .irl_init_all = mv88e6352_g2_irl_init_all,
2629 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2630 .phy_read = mv88e6xxx_g2_smi_phy_read,
2631 .phy_write = mv88e6xxx_g2_smi_phy_write,
2632 .port_set_link = mv88e6xxx_port_set_link,
2633 .port_set_duplex = mv88e6xxx_port_set_duplex,
2634 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2635 .port_set_speed = mv88e6185_port_set_speed,
2636 .port_tag_remap = mv88e6095_port_tag_remap,
2637 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2638 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2639 .port_set_ether_type = mv88e6351_port_set_ether_type,
2640 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2641 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2642 .port_pause_limit = mv88e6097_port_pause_limit,
2643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2645 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2646 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2647 .stats_get_strings = mv88e6095_stats_get_strings,
2648 .stats_get_stats = mv88e6095_stats_get_stats,
2649 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2650 .set_egress_port = mv88e6095_g1_set_egress_port,
2651 .watchdog_ops = &mv88e6097_watchdog_ops,
2652 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2653 .pot_clear = mv88e6xxx_g2_pot_clear,
2654 .reset = mv88e6352_g1_reset,
2655 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2656 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2659 static const struct mv88e6xxx_ops mv88e6172_ops = {
2660 /* MV88E6XXX_FAMILY_6352 */
2661 .irl_init_all = mv88e6352_g2_irl_init_all,
2662 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2663 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2664 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2665 .phy_read = mv88e6xxx_g2_smi_phy_read,
2666 .phy_write = mv88e6xxx_g2_smi_phy_write,
2667 .port_set_link = mv88e6xxx_port_set_link,
2668 .port_set_duplex = mv88e6xxx_port_set_duplex,
2669 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2670 .port_set_speed = mv88e6352_port_set_speed,
2671 .port_tag_remap = mv88e6095_port_tag_remap,
2672 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2673 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2674 .port_set_ether_type = mv88e6351_port_set_ether_type,
2675 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2676 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2677 .port_pause_limit = mv88e6097_port_pause_limit,
2678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2680 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2681 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2682 .stats_get_strings = mv88e6095_stats_get_strings,
2683 .stats_get_stats = mv88e6095_stats_get_stats,
2684 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2685 .set_egress_port = mv88e6095_g1_set_egress_port,
2686 .watchdog_ops = &mv88e6097_watchdog_ops,
2687 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2688 .pot_clear = mv88e6xxx_g2_pot_clear,
2689 .reset = mv88e6352_g1_reset,
2690 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2691 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2692 .serdes_power = mv88e6352_serdes_power,
2695 static const struct mv88e6xxx_ops mv88e6175_ops = {
2696 /* MV88E6XXX_FAMILY_6351 */
2697 .irl_init_all = mv88e6352_g2_irl_init_all,
2698 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2699 .phy_read = mv88e6xxx_g2_smi_phy_read,
2700 .phy_write = mv88e6xxx_g2_smi_phy_write,
2701 .port_set_link = mv88e6xxx_port_set_link,
2702 .port_set_duplex = mv88e6xxx_port_set_duplex,
2703 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2704 .port_set_speed = mv88e6185_port_set_speed,
2705 .port_tag_remap = mv88e6095_port_tag_remap,
2706 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2707 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2708 .port_set_ether_type = mv88e6351_port_set_ether_type,
2709 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2710 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2711 .port_pause_limit = mv88e6097_port_pause_limit,
2712 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2713 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2714 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2715 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2716 .stats_get_strings = mv88e6095_stats_get_strings,
2717 .stats_get_stats = mv88e6095_stats_get_stats,
2718 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2719 .set_egress_port = mv88e6095_g1_set_egress_port,
2720 .watchdog_ops = &mv88e6097_watchdog_ops,
2721 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2722 .pot_clear = mv88e6xxx_g2_pot_clear,
2723 .reset = mv88e6352_g1_reset,
2724 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2725 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2728 static const struct mv88e6xxx_ops mv88e6176_ops = {
2729 /* MV88E6XXX_FAMILY_6352 */
2730 .irl_init_all = mv88e6352_g2_irl_init_all,
2731 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2732 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2733 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2734 .phy_read = mv88e6xxx_g2_smi_phy_read,
2735 .phy_write = mv88e6xxx_g2_smi_phy_write,
2736 .port_set_link = mv88e6xxx_port_set_link,
2737 .port_set_duplex = mv88e6xxx_port_set_duplex,
2738 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2739 .port_set_speed = mv88e6352_port_set_speed,
2740 .port_tag_remap = mv88e6095_port_tag_remap,
2741 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2742 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2743 .port_set_ether_type = mv88e6351_port_set_ether_type,
2744 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2745 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2746 .port_pause_limit = mv88e6097_port_pause_limit,
2747 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2748 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2749 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2750 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2751 .stats_get_strings = mv88e6095_stats_get_strings,
2752 .stats_get_stats = mv88e6095_stats_get_stats,
2753 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2754 .set_egress_port = mv88e6095_g1_set_egress_port,
2755 .watchdog_ops = &mv88e6097_watchdog_ops,
2756 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2757 .pot_clear = mv88e6xxx_g2_pot_clear,
2758 .reset = mv88e6352_g1_reset,
2759 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2760 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2761 .serdes_power = mv88e6352_serdes_power,
2764 static const struct mv88e6xxx_ops mv88e6185_ops = {
2765 /* MV88E6XXX_FAMILY_6185 */
2766 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2767 .phy_read = mv88e6185_phy_ppu_read,
2768 .phy_write = mv88e6185_phy_ppu_write,
2769 .port_set_link = mv88e6xxx_port_set_link,
2770 .port_set_duplex = mv88e6xxx_port_set_duplex,
2771 .port_set_speed = mv88e6185_port_set_speed,
2772 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2773 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2774 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2775 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2776 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2777 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2778 .stats_get_strings = mv88e6095_stats_get_strings,
2779 .stats_get_stats = mv88e6095_stats_get_stats,
2780 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2781 .set_egress_port = mv88e6095_g1_set_egress_port,
2782 .watchdog_ops = &mv88e6097_watchdog_ops,
2783 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2784 .ppu_enable = mv88e6185_g1_ppu_enable,
2785 .ppu_disable = mv88e6185_g1_ppu_disable,
2786 .reset = mv88e6185_g1_reset,
2787 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2788 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2791 static const struct mv88e6xxx_ops mv88e6190_ops = {
2792 /* MV88E6XXX_FAMILY_6390 */
2793 .setup_errata = mv88e6390_setup_errata,
2794 .irl_init_all = mv88e6390_g2_irl_init_all,
2795 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2796 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2797 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2798 .phy_read = mv88e6xxx_g2_smi_phy_read,
2799 .phy_write = mv88e6xxx_g2_smi_phy_write,
2800 .port_set_link = mv88e6xxx_port_set_link,
2801 .port_set_duplex = mv88e6xxx_port_set_duplex,
2802 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2803 .port_set_speed = mv88e6390_port_set_speed,
2804 .port_tag_remap = mv88e6390_port_tag_remap,
2805 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2806 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2807 .port_set_ether_type = mv88e6351_port_set_ether_type,
2808 .port_pause_limit = mv88e6390_port_pause_limit,
2809 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2810 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2811 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2812 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2813 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2814 .stats_get_strings = mv88e6320_stats_get_strings,
2815 .stats_get_stats = mv88e6390_stats_get_stats,
2816 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2817 .set_egress_port = mv88e6390_g1_set_egress_port,
2818 .watchdog_ops = &mv88e6390_watchdog_ops,
2819 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2820 .pot_clear = mv88e6xxx_g2_pot_clear,
2821 .reset = mv88e6352_g1_reset,
2822 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2823 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2824 .serdes_power = mv88e6390_serdes_power,
2827 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2828 /* MV88E6XXX_FAMILY_6390 */
2829 .setup_errata = mv88e6390_setup_errata,
2830 .irl_init_all = mv88e6390_g2_irl_init_all,
2831 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2832 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2833 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2834 .phy_read = mv88e6xxx_g2_smi_phy_read,
2835 .phy_write = mv88e6xxx_g2_smi_phy_write,
2836 .port_set_link = mv88e6xxx_port_set_link,
2837 .port_set_duplex = mv88e6xxx_port_set_duplex,
2838 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2839 .port_set_speed = mv88e6390x_port_set_speed,
2840 .port_tag_remap = mv88e6390_port_tag_remap,
2841 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2842 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2843 .port_set_ether_type = mv88e6351_port_set_ether_type,
2844 .port_pause_limit = mv88e6390_port_pause_limit,
2845 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2846 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2847 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2848 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2849 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2850 .stats_get_strings = mv88e6320_stats_get_strings,
2851 .stats_get_stats = mv88e6390_stats_get_stats,
2852 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2853 .set_egress_port = mv88e6390_g1_set_egress_port,
2854 .watchdog_ops = &mv88e6390_watchdog_ops,
2855 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2856 .pot_clear = mv88e6xxx_g2_pot_clear,
2857 .reset = mv88e6352_g1_reset,
2858 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2859 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2860 .serdes_power = mv88e6390_serdes_power,
2863 static const struct mv88e6xxx_ops mv88e6191_ops = {
2864 /* MV88E6XXX_FAMILY_6390 */
2865 .setup_errata = mv88e6390_setup_errata,
2866 .irl_init_all = mv88e6390_g2_irl_init_all,
2867 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2868 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2869 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2870 .phy_read = mv88e6xxx_g2_smi_phy_read,
2871 .phy_write = mv88e6xxx_g2_smi_phy_write,
2872 .port_set_link = mv88e6xxx_port_set_link,
2873 .port_set_duplex = mv88e6xxx_port_set_duplex,
2874 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2875 .port_set_speed = mv88e6390_port_set_speed,
2876 .port_tag_remap = mv88e6390_port_tag_remap,
2877 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2878 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2879 .port_set_ether_type = mv88e6351_port_set_ether_type,
2880 .port_pause_limit = mv88e6390_port_pause_limit,
2881 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2882 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2883 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2884 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2885 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2886 .stats_get_strings = mv88e6320_stats_get_strings,
2887 .stats_get_stats = mv88e6390_stats_get_stats,
2888 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2889 .set_egress_port = mv88e6390_g1_set_egress_port,
2890 .watchdog_ops = &mv88e6390_watchdog_ops,
2891 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2892 .pot_clear = mv88e6xxx_g2_pot_clear,
2893 .reset = mv88e6352_g1_reset,
2894 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2895 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2896 .serdes_power = mv88e6390_serdes_power,
2899 static const struct mv88e6xxx_ops mv88e6240_ops = {
2900 /* MV88E6XXX_FAMILY_6352 */
2901 .irl_init_all = mv88e6352_g2_irl_init_all,
2902 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2903 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2904 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2905 .phy_read = mv88e6xxx_g2_smi_phy_read,
2906 .phy_write = mv88e6xxx_g2_smi_phy_write,
2907 .port_set_link = mv88e6xxx_port_set_link,
2908 .port_set_duplex = mv88e6xxx_port_set_duplex,
2909 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2910 .port_set_speed = mv88e6352_port_set_speed,
2911 .port_tag_remap = mv88e6095_port_tag_remap,
2912 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2913 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2914 .port_set_ether_type = mv88e6351_port_set_ether_type,
2915 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2916 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2917 .port_pause_limit = mv88e6097_port_pause_limit,
2918 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2919 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2920 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2921 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2922 .stats_get_strings = mv88e6095_stats_get_strings,
2923 .stats_get_stats = mv88e6095_stats_get_stats,
2924 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2925 .set_egress_port = mv88e6095_g1_set_egress_port,
2926 .watchdog_ops = &mv88e6097_watchdog_ops,
2927 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2928 .pot_clear = mv88e6xxx_g2_pot_clear,
2929 .reset = mv88e6352_g1_reset,
2930 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2931 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2932 .serdes_power = mv88e6352_serdes_power,
2935 static const struct mv88e6xxx_ops mv88e6290_ops = {
2936 /* MV88E6XXX_FAMILY_6390 */
2937 .setup_errata = mv88e6390_setup_errata,
2938 .irl_init_all = mv88e6390_g2_irl_init_all,
2939 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2940 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2941 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2942 .phy_read = mv88e6xxx_g2_smi_phy_read,
2943 .phy_write = mv88e6xxx_g2_smi_phy_write,
2944 .port_set_link = mv88e6xxx_port_set_link,
2945 .port_set_duplex = mv88e6xxx_port_set_duplex,
2946 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2947 .port_set_speed = mv88e6390_port_set_speed,
2948 .port_tag_remap = mv88e6390_port_tag_remap,
2949 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2950 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2951 .port_set_ether_type = mv88e6351_port_set_ether_type,
2952 .port_pause_limit = mv88e6390_port_pause_limit,
2953 .port_set_cmode = mv88e6390x_port_set_cmode,
2954 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2955 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2956 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2957 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2958 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2959 .stats_get_strings = mv88e6320_stats_get_strings,
2960 .stats_get_stats = mv88e6390_stats_get_stats,
2961 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2962 .set_egress_port = mv88e6390_g1_set_egress_port,
2963 .watchdog_ops = &mv88e6390_watchdog_ops,
2964 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2965 .pot_clear = mv88e6xxx_g2_pot_clear,
2966 .reset = mv88e6352_g1_reset,
2967 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2968 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2969 .serdes_power = mv88e6390_serdes_power,
2972 static const struct mv88e6xxx_ops mv88e6320_ops = {
2973 /* MV88E6XXX_FAMILY_6320 */
2974 .irl_init_all = mv88e6352_g2_irl_init_all,
2975 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2976 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2977 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2978 .phy_read = mv88e6xxx_g2_smi_phy_read,
2979 .phy_write = mv88e6xxx_g2_smi_phy_write,
2980 .port_set_link = mv88e6xxx_port_set_link,
2981 .port_set_duplex = mv88e6xxx_port_set_duplex,
2982 .port_set_speed = mv88e6185_port_set_speed,
2983 .port_tag_remap = mv88e6095_port_tag_remap,
2984 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2985 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2986 .port_set_ether_type = mv88e6351_port_set_ether_type,
2987 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2988 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2989 .port_pause_limit = mv88e6097_port_pause_limit,
2990 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2991 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2992 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2993 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2994 .stats_get_strings = mv88e6320_stats_get_strings,
2995 .stats_get_stats = mv88e6320_stats_get_stats,
2996 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2997 .set_egress_port = mv88e6095_g1_set_egress_port,
2998 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2999 .pot_clear = mv88e6xxx_g2_pot_clear,
3000 .reset = mv88e6352_g1_reset,
3001 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3002 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3005 static const struct mv88e6xxx_ops mv88e6321_ops = {
3006 /* MV88E6XXX_FAMILY_6320 */
3007 .irl_init_all = mv88e6352_g2_irl_init_all,
3008 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3009 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3010 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3011 .phy_read = mv88e6xxx_g2_smi_phy_read,
3012 .phy_write = mv88e6xxx_g2_smi_phy_write,
3013 .port_set_link = mv88e6xxx_port_set_link,
3014 .port_set_duplex = mv88e6xxx_port_set_duplex,
3015 .port_set_speed = mv88e6185_port_set_speed,
3016 .port_tag_remap = mv88e6095_port_tag_remap,
3017 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3018 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3019 .port_set_ether_type = mv88e6351_port_set_ether_type,
3020 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3021 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3022 .port_pause_limit = mv88e6097_port_pause_limit,
3023 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3024 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3025 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3026 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3027 .stats_get_strings = mv88e6320_stats_get_strings,
3028 .stats_get_stats = mv88e6320_stats_get_stats,
3029 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3030 .set_egress_port = mv88e6095_g1_set_egress_port,
3031 .reset = mv88e6352_g1_reset,
3032 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3033 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3036 static const struct mv88e6xxx_ops mv88e6341_ops = {
3037 /* MV88E6XXX_FAMILY_6341 */
3038 .irl_init_all = mv88e6352_g2_irl_init_all,
3039 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3040 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3042 .phy_read = mv88e6xxx_g2_smi_phy_read,
3043 .phy_write = mv88e6xxx_g2_smi_phy_write,
3044 .port_set_link = mv88e6xxx_port_set_link,
3045 .port_set_duplex = mv88e6xxx_port_set_duplex,
3046 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3047 .port_set_speed = mv88e6341_port_set_speed,
3048 .port_tag_remap = mv88e6095_port_tag_remap,
3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051 .port_set_ether_type = mv88e6351_port_set_ether_type,
3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3054 .port_pause_limit = mv88e6097_port_pause_limit,
3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3059 .stats_get_strings = mv88e6320_stats_get_strings,
3060 .stats_get_stats = mv88e6390_stats_get_stats,
3061 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3062 .set_egress_port = mv88e6390_g1_set_egress_port,
3063 .watchdog_ops = &mv88e6390_watchdog_ops,
3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3065 .pot_clear = mv88e6xxx_g2_pot_clear,
3066 .reset = mv88e6352_g1_reset,
3067 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3068 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3071 static const struct mv88e6xxx_ops mv88e6350_ops = {
3072 /* MV88E6XXX_FAMILY_6351 */
3073 .irl_init_all = mv88e6352_g2_irl_init_all,
3074 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3075 .phy_read = mv88e6xxx_g2_smi_phy_read,
3076 .phy_write = mv88e6xxx_g2_smi_phy_write,
3077 .port_set_link = mv88e6xxx_port_set_link,
3078 .port_set_duplex = mv88e6xxx_port_set_duplex,
3079 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3080 .port_set_speed = mv88e6185_port_set_speed,
3081 .port_tag_remap = mv88e6095_port_tag_remap,
3082 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3083 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3084 .port_set_ether_type = mv88e6351_port_set_ether_type,
3085 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3086 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3087 .port_pause_limit = mv88e6097_port_pause_limit,
3088 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3089 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3090 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3091 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3092 .stats_get_strings = mv88e6095_stats_get_strings,
3093 .stats_get_stats = mv88e6095_stats_get_stats,
3094 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3095 .set_egress_port = mv88e6095_g1_set_egress_port,
3096 .watchdog_ops = &mv88e6097_watchdog_ops,
3097 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3098 .pot_clear = mv88e6xxx_g2_pot_clear,
3099 .reset = mv88e6352_g1_reset,
3100 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3101 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3104 static const struct mv88e6xxx_ops mv88e6351_ops = {
3105 /* MV88E6XXX_FAMILY_6351 */
3106 .irl_init_all = mv88e6352_g2_irl_init_all,
3107 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3108 .phy_read = mv88e6xxx_g2_smi_phy_read,
3109 .phy_write = mv88e6xxx_g2_smi_phy_write,
3110 .port_set_link = mv88e6xxx_port_set_link,
3111 .port_set_duplex = mv88e6xxx_port_set_duplex,
3112 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3113 .port_set_speed = mv88e6185_port_set_speed,
3114 .port_tag_remap = mv88e6095_port_tag_remap,
3115 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3116 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3117 .port_set_ether_type = mv88e6351_port_set_ether_type,
3118 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3119 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3120 .port_pause_limit = mv88e6097_port_pause_limit,
3121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3123 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3124 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3125 .stats_get_strings = mv88e6095_stats_get_strings,
3126 .stats_get_stats = mv88e6095_stats_get_stats,
3127 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3128 .set_egress_port = mv88e6095_g1_set_egress_port,
3129 .watchdog_ops = &mv88e6097_watchdog_ops,
3130 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3131 .pot_clear = mv88e6xxx_g2_pot_clear,
3132 .reset = mv88e6352_g1_reset,
3133 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3134 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3137 static const struct mv88e6xxx_ops mv88e6352_ops = {
3138 /* MV88E6XXX_FAMILY_6352 */
3139 .irl_init_all = mv88e6352_g2_irl_init_all,
3140 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3141 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3142 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3143 .phy_read = mv88e6xxx_g2_smi_phy_read,
3144 .phy_write = mv88e6xxx_g2_smi_phy_write,
3145 .port_set_link = mv88e6xxx_port_set_link,
3146 .port_set_duplex = mv88e6xxx_port_set_duplex,
3147 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3148 .port_set_speed = mv88e6352_port_set_speed,
3149 .port_tag_remap = mv88e6095_port_tag_remap,
3150 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3151 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3152 .port_set_ether_type = mv88e6351_port_set_ether_type,
3153 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3154 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3155 .port_pause_limit = mv88e6097_port_pause_limit,
3156 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3157 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3158 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3159 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3160 .stats_get_strings = mv88e6095_stats_get_strings,
3161 .stats_get_stats = mv88e6095_stats_get_stats,
3162 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3163 .set_egress_port = mv88e6095_g1_set_egress_port,
3164 .watchdog_ops = &mv88e6097_watchdog_ops,
3165 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3166 .pot_clear = mv88e6xxx_g2_pot_clear,
3167 .reset = mv88e6352_g1_reset,
3168 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3169 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3170 .serdes_power = mv88e6352_serdes_power,
3173 static const struct mv88e6xxx_ops mv88e6390_ops = {
3174 /* MV88E6XXX_FAMILY_6390 */
3175 .setup_errata = mv88e6390_setup_errata,
3176 .irl_init_all = mv88e6390_g2_irl_init_all,
3177 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3178 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3179 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3180 .phy_read = mv88e6xxx_g2_smi_phy_read,
3181 .phy_write = mv88e6xxx_g2_smi_phy_write,
3182 .port_set_link = mv88e6xxx_port_set_link,
3183 .port_set_duplex = mv88e6xxx_port_set_duplex,
3184 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3185 .port_set_speed = mv88e6390_port_set_speed,
3186 .port_tag_remap = mv88e6390_port_tag_remap,
3187 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3188 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3189 .port_set_ether_type = mv88e6351_port_set_ether_type,
3190 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3191 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3192 .port_pause_limit = mv88e6390_port_pause_limit,
3193 .port_set_cmode = mv88e6390x_port_set_cmode,
3194 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3196 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3197 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3198 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3199 .stats_get_strings = mv88e6320_stats_get_strings,
3200 .stats_get_stats = mv88e6390_stats_get_stats,
3201 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3202 .set_egress_port = mv88e6390_g1_set_egress_port,
3203 .watchdog_ops = &mv88e6390_watchdog_ops,
3204 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3205 .pot_clear = mv88e6xxx_g2_pot_clear,
3206 .reset = mv88e6352_g1_reset,
3207 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3208 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3209 .serdes_power = mv88e6390_serdes_power,
3212 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3213 /* MV88E6XXX_FAMILY_6390 */
3214 .setup_errata = mv88e6390_setup_errata,
3215 .irl_init_all = mv88e6390_g2_irl_init_all,
3216 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3217 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3219 .phy_read = mv88e6xxx_g2_smi_phy_read,
3220 .phy_write = mv88e6xxx_g2_smi_phy_write,
3221 .port_set_link = mv88e6xxx_port_set_link,
3222 .port_set_duplex = mv88e6xxx_port_set_duplex,
3223 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3224 .port_set_speed = mv88e6390x_port_set_speed,
3225 .port_tag_remap = mv88e6390_port_tag_remap,
3226 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3227 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3228 .port_set_ether_type = mv88e6351_port_set_ether_type,
3229 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3230 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3231 .port_pause_limit = mv88e6390_port_pause_limit,
3232 .port_set_cmode = mv88e6390x_port_set_cmode,
3233 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3235 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3236 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3237 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3238 .stats_get_strings = mv88e6320_stats_get_strings,
3239 .stats_get_stats = mv88e6390_stats_get_stats,
3240 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3241 .set_egress_port = mv88e6390_g1_set_egress_port,
3242 .watchdog_ops = &mv88e6390_watchdog_ops,
3243 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3244 .pot_clear = mv88e6xxx_g2_pot_clear,
3245 .reset = mv88e6352_g1_reset,
3246 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3247 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3248 .serdes_power = mv88e6390_serdes_power,
3251 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3253 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3254 .family = MV88E6XXX_FAMILY_6097,
3255 .name = "Marvell 88E6085",
3256 .num_databases = 4096,
3259 .port_base_addr = 0x10,
3260 .global1_addr = 0x1b,
3261 .global2_addr = 0x1c,
3262 .age_time_coeff = 15000,
3265 .atu_move_port_mask = 0xf,
3268 .tag_protocol = DSA_TAG_PROTO_DSA,
3269 .ops = &mv88e6085_ops,
3273 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3274 .family = MV88E6XXX_FAMILY_6095,
3275 .name = "Marvell 88E6095/88E6095F",
3276 .num_databases = 256,
3279 .port_base_addr = 0x10,
3280 .global1_addr = 0x1b,
3281 .global2_addr = 0x1c,
3282 .age_time_coeff = 15000,
3284 .atu_move_port_mask = 0xf,
3286 .tag_protocol = DSA_TAG_PROTO_DSA,
3287 .ops = &mv88e6095_ops,
3291 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3292 .family = MV88E6XXX_FAMILY_6097,
3293 .name = "Marvell 88E6097/88E6097F",
3294 .num_databases = 4096,
3297 .port_base_addr = 0x10,
3298 .global1_addr = 0x1b,
3299 .global2_addr = 0x1c,
3300 .age_time_coeff = 15000,
3303 .atu_move_port_mask = 0xf,
3306 .tag_protocol = DSA_TAG_PROTO_EDSA,
3307 .ops = &mv88e6097_ops,
3311 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3312 .family = MV88E6XXX_FAMILY_6165,
3313 .name = "Marvell 88E6123",
3314 .num_databases = 4096,
3317 .port_base_addr = 0x10,
3318 .global1_addr = 0x1b,
3319 .global2_addr = 0x1c,
3320 .age_time_coeff = 15000,
3323 .atu_move_port_mask = 0xf,
3326 .tag_protocol = DSA_TAG_PROTO_EDSA,
3327 .ops = &mv88e6123_ops,
3331 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3332 .family = MV88E6XXX_FAMILY_6185,
3333 .name = "Marvell 88E6131",
3334 .num_databases = 256,
3337 .port_base_addr = 0x10,
3338 .global1_addr = 0x1b,
3339 .global2_addr = 0x1c,
3340 .age_time_coeff = 15000,
3342 .atu_move_port_mask = 0xf,
3344 .tag_protocol = DSA_TAG_PROTO_DSA,
3345 .ops = &mv88e6131_ops,
3349 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3350 .family = MV88E6XXX_FAMILY_6341,
3351 .name = "Marvell 88E6341",
3352 .num_databases = 4096,
3355 .port_base_addr = 0x10,
3356 .global1_addr = 0x1b,
3357 .global2_addr = 0x1c,
3358 .age_time_coeff = 3750,
3359 .atu_move_port_mask = 0x1f,
3363 .tag_protocol = DSA_TAG_PROTO_EDSA,
3364 .ops = &mv88e6141_ops,
3368 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3369 .family = MV88E6XXX_FAMILY_6165,
3370 .name = "Marvell 88E6161",
3371 .num_databases = 4096,
3374 .port_base_addr = 0x10,
3375 .global1_addr = 0x1b,
3376 .global2_addr = 0x1c,
3377 .age_time_coeff = 15000,
3380 .atu_move_port_mask = 0xf,
3383 .tag_protocol = DSA_TAG_PROTO_EDSA,
3384 .ops = &mv88e6161_ops,
3388 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3389 .family = MV88E6XXX_FAMILY_6165,
3390 .name = "Marvell 88E6165",
3391 .num_databases = 4096,
3394 .port_base_addr = 0x10,
3395 .global1_addr = 0x1b,
3396 .global2_addr = 0x1c,
3397 .age_time_coeff = 15000,
3400 .atu_move_port_mask = 0xf,
3403 .tag_protocol = DSA_TAG_PROTO_DSA,
3404 .ops = &mv88e6165_ops,
3408 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3409 .family = MV88E6XXX_FAMILY_6351,
3410 .name = "Marvell 88E6171",
3411 .num_databases = 4096,
3414 .port_base_addr = 0x10,
3415 .global1_addr = 0x1b,
3416 .global2_addr = 0x1c,
3417 .age_time_coeff = 15000,
3420 .atu_move_port_mask = 0xf,
3423 .tag_protocol = DSA_TAG_PROTO_EDSA,
3424 .ops = &mv88e6171_ops,
3428 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3429 .family = MV88E6XXX_FAMILY_6352,
3430 .name = "Marvell 88E6172",
3431 .num_databases = 4096,
3434 .port_base_addr = 0x10,
3435 .global1_addr = 0x1b,
3436 .global2_addr = 0x1c,
3437 .age_time_coeff = 15000,
3440 .atu_move_port_mask = 0xf,
3443 .tag_protocol = DSA_TAG_PROTO_EDSA,
3444 .ops = &mv88e6172_ops,
3448 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3449 .family = MV88E6XXX_FAMILY_6351,
3450 .name = "Marvell 88E6175",
3451 .num_databases = 4096,
3454 .port_base_addr = 0x10,
3455 .global1_addr = 0x1b,
3456 .global2_addr = 0x1c,
3457 .age_time_coeff = 15000,
3460 .atu_move_port_mask = 0xf,
3463 .tag_protocol = DSA_TAG_PROTO_EDSA,
3464 .ops = &mv88e6175_ops,
3468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3469 .family = MV88E6XXX_FAMILY_6352,
3470 .name = "Marvell 88E6176",
3471 .num_databases = 4096,
3474 .port_base_addr = 0x10,
3475 .global1_addr = 0x1b,
3476 .global2_addr = 0x1c,
3477 .age_time_coeff = 15000,
3480 .atu_move_port_mask = 0xf,
3483 .tag_protocol = DSA_TAG_PROTO_EDSA,
3484 .ops = &mv88e6176_ops,
3488 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3489 .family = MV88E6XXX_FAMILY_6185,
3490 .name = "Marvell 88E6185",
3491 .num_databases = 256,
3494 .port_base_addr = 0x10,
3495 .global1_addr = 0x1b,
3496 .global2_addr = 0x1c,
3497 .age_time_coeff = 15000,
3499 .atu_move_port_mask = 0xf,
3501 .tag_protocol = DSA_TAG_PROTO_EDSA,
3502 .ops = &mv88e6185_ops,
3506 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3507 .family = MV88E6XXX_FAMILY_6390,
3508 .name = "Marvell 88E6190",
3509 .num_databases = 4096,
3510 .num_ports = 11, /* 10 + Z80 */
3512 .port_base_addr = 0x0,
3513 .global1_addr = 0x1b,
3514 .global2_addr = 0x1c,
3515 .tag_protocol = DSA_TAG_PROTO_DSA,
3516 .age_time_coeff = 3750,
3521 .atu_move_port_mask = 0x1f,
3522 .ops = &mv88e6190_ops,
3526 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3527 .family = MV88E6XXX_FAMILY_6390,
3528 .name = "Marvell 88E6190X",
3529 .num_databases = 4096,
3530 .num_ports = 11, /* 10 + Z80 */
3532 .port_base_addr = 0x0,
3533 .global1_addr = 0x1b,
3534 .global2_addr = 0x1c,
3535 .age_time_coeff = 3750,
3538 .atu_move_port_mask = 0x1f,
3541 .tag_protocol = DSA_TAG_PROTO_DSA,
3542 .ops = &mv88e6190x_ops,
3546 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3547 .family = MV88E6XXX_FAMILY_6390,
3548 .name = "Marvell 88E6191",
3549 .num_databases = 4096,
3550 .num_ports = 11, /* 10 + Z80 */
3552 .port_base_addr = 0x0,
3553 .global1_addr = 0x1b,
3554 .global2_addr = 0x1c,
3555 .age_time_coeff = 3750,
3558 .atu_move_port_mask = 0x1f,
3561 .tag_protocol = DSA_TAG_PROTO_DSA,
3562 .ops = &mv88e6191_ops,
3566 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3567 .family = MV88E6XXX_FAMILY_6352,
3568 .name = "Marvell 88E6240",
3569 .num_databases = 4096,
3572 .port_base_addr = 0x10,
3573 .global1_addr = 0x1b,
3574 .global2_addr = 0x1c,
3575 .age_time_coeff = 15000,
3578 .atu_move_port_mask = 0xf,
3581 .tag_protocol = DSA_TAG_PROTO_EDSA,
3582 .ops = &mv88e6240_ops,
3586 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3587 .family = MV88E6XXX_FAMILY_6390,
3588 .name = "Marvell 88E6290",
3589 .num_databases = 4096,
3590 .num_ports = 11, /* 10 + Z80 */
3592 .port_base_addr = 0x0,
3593 .global1_addr = 0x1b,
3594 .global2_addr = 0x1c,
3595 .age_time_coeff = 3750,
3598 .atu_move_port_mask = 0x1f,
3601 .tag_protocol = DSA_TAG_PROTO_DSA,
3602 .ops = &mv88e6290_ops,
3606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3607 .family = MV88E6XXX_FAMILY_6320,
3608 .name = "Marvell 88E6320",
3609 .num_databases = 4096,
3612 .port_base_addr = 0x10,
3613 .global1_addr = 0x1b,
3614 .global2_addr = 0x1c,
3615 .age_time_coeff = 15000,
3617 .atu_move_port_mask = 0xf,
3620 .tag_protocol = DSA_TAG_PROTO_EDSA,
3621 .ops = &mv88e6320_ops,
3625 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3626 .family = MV88E6XXX_FAMILY_6320,
3627 .name = "Marvell 88E6321",
3628 .num_databases = 4096,
3631 .port_base_addr = 0x10,
3632 .global1_addr = 0x1b,
3633 .global2_addr = 0x1c,
3634 .age_time_coeff = 15000,
3636 .atu_move_port_mask = 0xf,
3638 .tag_protocol = DSA_TAG_PROTO_EDSA,
3639 .ops = &mv88e6321_ops,
3643 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3644 .family = MV88E6XXX_FAMILY_6341,
3645 .name = "Marvell 88E6341",
3646 .num_databases = 4096,
3649 .port_base_addr = 0x10,
3650 .global1_addr = 0x1b,
3651 .global2_addr = 0x1c,
3652 .age_time_coeff = 3750,
3653 .atu_move_port_mask = 0x1f,
3657 .tag_protocol = DSA_TAG_PROTO_EDSA,
3658 .ops = &mv88e6341_ops,
3662 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3663 .family = MV88E6XXX_FAMILY_6351,
3664 .name = "Marvell 88E6350",
3665 .num_databases = 4096,
3668 .port_base_addr = 0x10,
3669 .global1_addr = 0x1b,
3670 .global2_addr = 0x1c,
3671 .age_time_coeff = 15000,
3674 .atu_move_port_mask = 0xf,
3677 .tag_protocol = DSA_TAG_PROTO_EDSA,
3678 .ops = &mv88e6350_ops,
3682 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3683 .family = MV88E6XXX_FAMILY_6351,
3684 .name = "Marvell 88E6351",
3685 .num_databases = 4096,
3688 .port_base_addr = 0x10,
3689 .global1_addr = 0x1b,
3690 .global2_addr = 0x1c,
3691 .age_time_coeff = 15000,
3694 .atu_move_port_mask = 0xf,
3697 .tag_protocol = DSA_TAG_PROTO_EDSA,
3698 .ops = &mv88e6351_ops,
3702 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3703 .family = MV88E6XXX_FAMILY_6352,
3704 .name = "Marvell 88E6352",
3705 .num_databases = 4096,
3708 .port_base_addr = 0x10,
3709 .global1_addr = 0x1b,
3710 .global2_addr = 0x1c,
3711 .age_time_coeff = 15000,
3714 .atu_move_port_mask = 0xf,
3717 .tag_protocol = DSA_TAG_PROTO_EDSA,
3718 .ops = &mv88e6352_ops,
3721 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3722 .family = MV88E6XXX_FAMILY_6390,
3723 .name = "Marvell 88E6390",
3724 .num_databases = 4096,
3725 .num_ports = 11, /* 10 + Z80 */
3727 .port_base_addr = 0x0,
3728 .global1_addr = 0x1b,
3729 .global2_addr = 0x1c,
3730 .age_time_coeff = 3750,
3733 .atu_move_port_mask = 0x1f,
3736 .tag_protocol = DSA_TAG_PROTO_DSA,
3737 .ops = &mv88e6390_ops,
3740 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3741 .family = MV88E6XXX_FAMILY_6390,
3742 .name = "Marvell 88E6390X",
3743 .num_databases = 4096,
3744 .num_ports = 11, /* 10 + Z80 */
3746 .port_base_addr = 0x0,
3747 .global1_addr = 0x1b,
3748 .global2_addr = 0x1c,
3749 .age_time_coeff = 3750,
3752 .atu_move_port_mask = 0x1f,
3755 .tag_protocol = DSA_TAG_PROTO_DSA,
3756 .ops = &mv88e6390x_ops,
3760 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3764 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3765 if (mv88e6xxx_table[i].prod_num == prod_num)
3766 return &mv88e6xxx_table[i];
3771 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3773 const struct mv88e6xxx_info *info;
3774 unsigned int prod_num, rev;
3778 mutex_lock(&chip->reg_lock);
3779 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3780 mutex_unlock(&chip->reg_lock);
3784 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3785 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3787 info = mv88e6xxx_lookup_info(prod_num);
3791 /* Update the compatible info with the probed one */
3794 err = mv88e6xxx_g2_require(chip);
3798 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3799 chip->info->prod_num, chip->info->name, rev);
3804 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3806 struct mv88e6xxx_chip *chip;
3808 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3814 mutex_init(&chip->reg_lock);
3815 INIT_LIST_HEAD(&chip->mdios);
3820 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3821 struct mii_bus *bus, int sw_addr)
3824 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3825 else if (chip->info->multi_chip)
3826 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3831 chip->sw_addr = sw_addr;
3836 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3838 struct mv88e6xxx_chip *chip = ds->priv;
3840 return chip->info->tag_protocol;
3843 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3844 struct device *host_dev, int sw_addr,
3847 struct mv88e6xxx_chip *chip;
3848 struct mii_bus *bus;
3851 bus = dsa_host_dev_to_mii_bus(host_dev);
3855 chip = mv88e6xxx_alloc_chip(dsa_dev);
3859 /* Legacy SMI probing will only support chips similar to 88E6085 */
3860 chip->info = &mv88e6xxx_table[MV88E6085];
3862 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3866 err = mv88e6xxx_detect(chip);
3870 mutex_lock(&chip->reg_lock);
3871 err = mv88e6xxx_switch_reset(chip);
3872 mutex_unlock(&chip->reg_lock);
3876 mv88e6xxx_phy_init(chip);
3878 err = mv88e6xxx_mdios_register(chip, NULL);
3884 return chip->info->name;
3886 devm_kfree(dsa_dev, chip);
3891 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3892 const struct switchdev_obj_port_mdb *mdb,
3893 struct switchdev_trans *trans)
3895 /* We don't need any dynamic resource from the kernel (yet),
3896 * so skip the prepare phase.
3902 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3903 const struct switchdev_obj_port_mdb *mdb,
3904 struct switchdev_trans *trans)
3906 struct mv88e6xxx_chip *chip = ds->priv;
3908 mutex_lock(&chip->reg_lock);
3909 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3910 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3911 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3913 mutex_unlock(&chip->reg_lock);
3916 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3917 const struct switchdev_obj_port_mdb *mdb)
3919 struct mv88e6xxx_chip *chip = ds->priv;
3922 mutex_lock(&chip->reg_lock);
3923 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3924 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3925 mutex_unlock(&chip->reg_lock);
3930 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3931 .probe = mv88e6xxx_drv_probe,
3932 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3933 .setup = mv88e6xxx_setup,
3934 .set_addr = mv88e6xxx_set_addr,
3935 .adjust_link = mv88e6xxx_adjust_link,
3936 .get_strings = mv88e6xxx_get_strings,
3937 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3938 .get_sset_count = mv88e6xxx_get_sset_count,
3939 .port_enable = mv88e6xxx_port_enable,
3940 .port_disable = mv88e6xxx_port_disable,
3941 .get_mac_eee = mv88e6xxx_get_mac_eee,
3942 .set_mac_eee = mv88e6xxx_set_mac_eee,
3943 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3944 .get_eeprom = mv88e6xxx_get_eeprom,
3945 .set_eeprom = mv88e6xxx_set_eeprom,
3946 .get_regs_len = mv88e6xxx_get_regs_len,
3947 .get_regs = mv88e6xxx_get_regs,
3948 .set_ageing_time = mv88e6xxx_set_ageing_time,
3949 .port_bridge_join = mv88e6xxx_port_bridge_join,
3950 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3951 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3952 .port_fast_age = mv88e6xxx_port_fast_age,
3953 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3954 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3955 .port_vlan_add = mv88e6xxx_port_vlan_add,
3956 .port_vlan_del = mv88e6xxx_port_vlan_del,
3957 .port_fdb_add = mv88e6xxx_port_fdb_add,
3958 .port_fdb_del = mv88e6xxx_port_fdb_del,
3959 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3960 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3961 .port_mdb_add = mv88e6xxx_port_mdb_add,
3962 .port_mdb_del = mv88e6xxx_port_mdb_del,
3963 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3964 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
3967 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3968 .ops = &mv88e6xxx_switch_ops,
3971 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3973 struct device *dev = chip->dev;
3974 struct dsa_switch *ds;
3976 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3981 ds->ops = &mv88e6xxx_switch_ops;
3982 ds->ageing_time_min = chip->info->age_time_coeff;
3983 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3985 dev_set_drvdata(dev, ds);
3987 return dsa_register_switch(ds);
3990 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3992 dsa_unregister_switch(chip->ds);
3995 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3997 struct device *dev = &mdiodev->dev;
3998 struct device_node *np = dev->of_node;
3999 const struct mv88e6xxx_info *compat_info;
4000 struct mv88e6xxx_chip *chip;
4004 compat_info = of_device_get_match_data(dev);
4008 chip = mv88e6xxx_alloc_chip(dev);
4012 chip->info = compat_info;
4014 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4018 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4019 if (IS_ERR(chip->reset))
4020 return PTR_ERR(chip->reset);
4022 err = mv88e6xxx_detect(chip);
4026 mv88e6xxx_phy_init(chip);
4028 if (chip->info->ops->get_eeprom &&
4029 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4030 chip->eeprom_len = eeprom_len;
4032 mutex_lock(&chip->reg_lock);
4033 err = mv88e6xxx_switch_reset(chip);
4034 mutex_unlock(&chip->reg_lock);
4038 chip->irq = of_irq_get(np, 0);
4039 if (chip->irq == -EPROBE_DEFER) {
4044 if (chip->irq > 0) {
4045 /* Has to be performed before the MDIO bus is created,
4046 * because the PHYs will link there interrupts to these
4047 * interrupt controllers
4049 mutex_lock(&chip->reg_lock);
4050 err = mv88e6xxx_g1_irq_setup(chip);
4051 mutex_unlock(&chip->reg_lock);
4056 if (chip->info->g2_irqs > 0) {
4057 err = mv88e6xxx_g2_irq_setup(chip);
4063 usleep_range(1000, 2000);
4065 err = mv88e6xxx_mdios_register(chip, np);
4069 err = mv88e6xxx_register_switch(chip);
4076 mv88e6xxx_mdios_unregister(chip);
4078 if (chip->info->g2_irqs > 0 && chip->irq > 0)
4079 mv88e6xxx_g2_irq_free(chip);
4081 if (chip->irq > 0) {
4082 mutex_lock(&chip->reg_lock);
4083 mv88e6xxx_g1_irq_free(chip);
4084 mutex_unlock(&chip->reg_lock);
4090 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4092 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4093 struct mv88e6xxx_chip *chip = ds->priv;
4095 mv88e6xxx_phy_destroy(chip);
4096 mv88e6xxx_unregister_switch(chip);
4097 mv88e6xxx_mdios_unregister(chip);
4099 if (chip->irq > 0) {
4100 if (chip->info->g2_irqs > 0)
4101 mv88e6xxx_g2_irq_free(chip);
4102 mutex_lock(&chip->reg_lock);
4103 mv88e6xxx_g1_irq_free(chip);
4104 mutex_unlock(&chip->reg_lock);
4108 static const struct of_device_id mv88e6xxx_of_match[] = {
4110 .compatible = "marvell,mv88e6085",
4111 .data = &mv88e6xxx_table[MV88E6085],
4114 .compatible = "marvell,mv88e6190",
4115 .data = &mv88e6xxx_table[MV88E6190],
4120 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4122 static struct mdio_driver mv88e6xxx_driver = {
4123 .probe = mv88e6xxx_probe,
4124 .remove = mv88e6xxx_remove,
4126 .name = "mv88e6085",
4127 .of_match_table = mv88e6xxx_of_match,
4131 static int __init mv88e6xxx_init(void)
4133 register_switch_driver(&mv88e6xxx_switch_drv);
4134 return mdio_driver_register(&mv88e6xxx_driver);
4136 module_init(mv88e6xxx_init);
4138 static void __exit mv88e6xxx_cleanup(void)
4140 mdio_driver_unregister(&mv88e6xxx_driver);
4141 unregister_switch_driver(&mv88e6xxx_switch_drv);
4143 module_exit(mv88e6xxx_cleanup);
4145 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4146 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4147 MODULE_LICENSE("GPL");