2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
18 #include "mv88e6060.h"
20 static int reg_read(struct dsa_switch *ds, int addr, int reg)
22 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
27 return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
30 #define REG_READ(addr, reg) \
34 __ret = reg_read(ds, addr, reg); \
41 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
43 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
48 return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
51 #define REG_WRITE(addr, reg, val) \
55 __ret = reg_write(ds, addr, reg, val); \
60 static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
62 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
68 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
70 if (ret == PORT_SWITCH_ID_6060)
71 return "Marvell 88E6060 (A0)";
72 if (ret == PORT_SWITCH_ID_6060_R1 ||
73 ret == PORT_SWITCH_ID_6060_R2)
74 return "Marvell 88E6060 (B0)";
75 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
76 return "Marvell 88E6060";
82 static int mv88e6060_switch_reset(struct dsa_switch *ds)
86 unsigned long timeout;
88 /* Set all ports to the disabled state. */
89 for (i = 0; i < MV88E6060_PORTS; i++) {
90 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
91 REG_WRITE(REG_PORT(i), PORT_CONTROL,
92 ret & ~PORT_CONTROL_STATE_MASK);
95 /* Wait for transmit queues to drain. */
96 usleep_range(2000, 4000);
98 /* Reset the switch. */
99 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
100 GLOBAL_ATU_CONTROL_SWRESET |
101 GLOBAL_ATU_CONTROL_LEARNDIS);
103 /* Wait up to one second for reset to complete. */
104 timeout = jiffies + 1 * HZ;
105 while (time_before(jiffies, timeout)) {
106 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
107 if (ret & GLOBAL_STATUS_INIT_READY)
110 usleep_range(1000, 2000);
112 if (time_after(jiffies, timeout))
118 static int mv88e6060_setup_global(struct dsa_switch *ds)
120 /* Disable discarding of frames with excessive collisions,
121 * set the maximum frame size to 1536 bytes, and mask all
124 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
126 /* Disable automatic address learning.
128 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
129 GLOBAL_ATU_CONTROL_LEARNDIS);
134 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
136 int addr = REG_PORT(p);
138 /* Do not force flow control, disable Ingress and Egress
139 * Header tagging, disable VLAN tunneling, and set the port
140 * state to Forwarding. Additionally, if this is the CPU
141 * port, enable Ingress and Egress Trailer tagging mode.
143 REG_WRITE(addr, PORT_CONTROL,
144 dsa_is_cpu_port(ds, p) ?
145 PORT_CONTROL_TRAILER |
146 PORT_CONTROL_INGRESS_MODE |
147 PORT_CONTROL_STATE_FORWARDING :
148 PORT_CONTROL_STATE_FORWARDING);
150 /* Port based VLAN map: give each port its own address
151 * database, allow the CPU port to talk to each of the 'real'
152 * ports, and allow each of the 'real' ports to only talk to
155 REG_WRITE(addr, PORT_VLAN_MAP,
156 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
157 (dsa_is_cpu_port(ds, p) ?
159 BIT(ds->dst->cpu_port)));
161 /* Port Association Vector: when learning source addresses
162 * of packets, add the address to the address database using
163 * a port bitmap that has only the bit for this port set and
164 * the other bits clear.
166 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
171 static int mv88e6060_setup(struct dsa_switch *ds)
176 ret = mv88e6060_switch_reset(ds);
180 /* @@@ initialise atu */
182 ret = mv88e6060_setup_global(ds);
186 for (i = 0; i < MV88E6060_PORTS; i++) {
187 ret = mv88e6060_setup_port(ds, i);
195 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
197 /* Use the same MAC Address as FD Pause frames for all ports */
198 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
199 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
205 static int mv88e6060_port_to_phy_addr(int port)
207 if (port >= 0 && port < MV88E6060_PORTS)
212 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
216 addr = mv88e6060_port_to_phy_addr(port);
220 return reg_read(ds, addr, regnum);
224 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
228 addr = mv88e6060_port_to_phy_addr(port);
232 return reg_write(ds, addr, regnum, val);
235 static struct dsa_switch_driver mv88e6060_switch_driver = {
236 .tag_protocol = DSA_TAG_PROTO_TRAILER,
237 .probe = mv88e6060_probe,
238 .setup = mv88e6060_setup,
239 .set_addr = mv88e6060_set_addr,
240 .phy_read = mv88e6060_phy_read,
241 .phy_write = mv88e6060_phy_write,
244 static int __init mv88e6060_init(void)
246 register_switch_driver(&mv88e6060_switch_driver);
249 module_init(mv88e6060_init);
251 static void __exit mv88e6060_cleanup(void)
253 unregister_switch_driver(&mv88e6060_switch_driver);
255 module_exit(mv88e6060_cleanup);
257 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
258 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
259 MODULE_LICENSE("GPL");
260 MODULE_ALIAS("platform:mv88e6060");