drivers/net/dsa/lantiq_gswip.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Lantiq / Intel GSWIP switch driver for VRX200 SoCs
   4  *
   5  * Copyright (C) 2010 Lantiq Deutschland
   6  * Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
   8  *
   9  * The VLAN and bridge model the GSWIP hardware uses does not directly
  10  * matches the model DSA uses.
  11  *
  12  * The hardware has 64 possible table entries for bridges with one VLAN
  13  * ID, one flow id and a list of ports for each bridge. All entries which
  14  * match the same flow ID are combined in the mac learning table, they
  15  * act as one global bridge.
  16  * The hardware does not support VLAN filter on the port, but on the
  17  * bridge, this driver converts the DSA model to the hardware.
  18  *
  19  * The CPU gets all the exception frames which do not match any forwarding
  20  * rule and the CPU port is also added to all bridges. This makes it possible
  21  * to handle all the special cases easily in software.
  22  * At the initialization the driver allocates one bridge table entry for
  23  * each switch port which is used when the port is used without an
  24  * explicit bridge. This prevents the frames from being forwarded
  25  * between all LAN ports by default.
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/firmware.h>
  32 #include <linux/if_bridge.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/iopoll.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/module.h>
  37 #include <linux/of_mdio.h>
  38 #include <linux/of_net.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/phy.h>
  41 #include <linux/phylink.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/regmap.h>
  44 #include <linux/reset.h>
  45 #include <net/dsa.h>
  46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
  47
  48 #include "lantiq_pce.h"
  49
  50 /* GSWIP MDIO Registers */
  51 #define GSWIP_MDIO_GLOB                 0x00
  52 #define  GSWIP_MDIO_GLOB_ENABLE         BIT(15)
  53 #define GSWIP_MDIO_CTRL                 0x08
  54 #define  GSWIP_MDIO_CTRL_BUSY           BIT(12)
  55 #define  GSWIP_MDIO_CTRL_RD             BIT(11)
  56 #define  GSWIP_MDIO_CTRL_WR             BIT(10)
  57 #define  GSWIP_MDIO_CTRL_PHYAD_MASK     0x1f
  58 #define  GSWIP_MDIO_CTRL_PHYAD_SHIFT    5
  59 #define  GSWIP_MDIO_CTRL_REGAD_MASK     0x1f
  60 #define GSWIP_MDIO_READ                 0x09
  61 #define GSWIP_MDIO_WRITE                0x0A
  62 #define GSWIP_MDIO_MDC_CFG0             0x0B
  63 #define GSWIP_MDIO_MDC_CFG1             0x0C
  64 #define GSWIP_MDIO_PHYp(p)              (0x15 - (p))
  65 #define  GSWIP_MDIO_PHY_LINK_MASK       0x6000
  66 #define  GSWIP_MDIO_PHY_LINK_AUTO       0x0000
  67 #define  GSWIP_MDIO_PHY_LINK_DOWN       0x4000
  68 #define  GSWIP_MDIO_PHY_LINK_UP         0x2000
  69 #define  GSWIP_MDIO_PHY_SPEED_MASK      0x1800
  70 #define  GSWIP_MDIO_PHY_SPEED_AUTO      0x1800
  71 #define  GSWIP_MDIO_PHY_SPEED_M10       0x0000
  72 #define  GSWIP_MDIO_PHY_SPEED_M100      0x0800
  73 #define  GSWIP_MDIO_PHY_SPEED_G1        0x1000
  74 #define  GSWIP_MDIO_PHY_FDUP_MASK       0x0600
  75 #define  GSWIP_MDIO_PHY_FDUP_AUTO       0x0000
  76 #define  GSWIP_MDIO_PHY_FDUP_EN         0x0200
  77 #define  GSWIP_MDIO_PHY_FDUP_DIS        0x0600
  78 #define  GSWIP_MDIO_PHY_FCONTX_MASK     0x0180
  79 #define  GSWIP_MDIO_PHY_FCONTX_AUTO     0x0000
  80 #define  GSWIP_MDIO_PHY_FCONTX_EN       0x0100
  81 #define  GSWIP_MDIO_PHY_FCONTX_DIS      0x0180
  82 #define  GSWIP_MDIO_PHY_FCONRX_MASK     0x0060
  83 #define  GSWIP_MDIO_PHY_FCONRX_AUTO     0x0000
  84 #define  GSWIP_MDIO_PHY_FCONRX_EN       0x0020
  85 #define  GSWIP_MDIO_PHY_FCONRX_DIS      0x0060
  86 #define  GSWIP_MDIO_PHY_ADDR_MASK       0x001f
  87 #define  GSWIP_MDIO_PHY_MASK            (GSWIP_MDIO_PHY_ADDR_MASK | \
  88                                          GSWIP_MDIO_PHY_FCONRX_MASK | \
  89                                          GSWIP_MDIO_PHY_FCONTX_MASK | \
  90                                          GSWIP_MDIO_PHY_LINK_MASK | \
  91                                          GSWIP_MDIO_PHY_SPEED_MASK | \
  92                                          GSWIP_MDIO_PHY_FDUP_MASK)
  93
  94 /* GSWIP MII Registers */
  95 #define GSWIP_MII_CFGp(p)               (0x2 * (p))
  96 #define  GSWIP_MII_CFG_RESET            BIT(15)
  97 #define  GSWIP_MII_CFG_EN               BIT(14)
  98 #define  GSWIP_MII_CFG_ISOLATE          BIT(13)
  99 #define  GSWIP_MII_CFG_LDCLKDIS         BIT(12)
 100 #define  GSWIP_MII_CFG_RGMII_IBS        BIT(8)
 101 #define  GSWIP_MII_CFG_RMII_CLK         BIT(7)
 102 #define  GSWIP_MII_CFG_MODE_MIIP        0x0
 103 #define  GSWIP_MII_CFG_MODE_MIIM        0x1
 104 #define  GSWIP_MII_CFG_MODE_RMIIP       0x2
 105 #define  GSWIP_MII_CFG_MODE_RMIIM       0x3
 106 #define  GSWIP_MII_CFG_MODE_RGMII       0x4
 107 #define  GSWIP_MII_CFG_MODE_MASK        0xf
 108 #define  GSWIP_MII_CFG_RATE_M2P5        0x00
 109 #define  GSWIP_MII_CFG_RATE_M25 0x10
 110 #define  GSWIP_MII_CFG_RATE_M125        0x20
 111 #define  GSWIP_MII_CFG_RATE_M50 0x30
 112 #define  GSWIP_MII_CFG_RATE_AUTO        0x40
 113 #define  GSWIP_MII_CFG_RATE_MASK        0x70
 114 #define GSWIP_MII_PCDU0                 0x01
 115 #define GSWIP_MII_PCDU1                 0x03
 116 #define GSWIP_MII_PCDU5                 0x05
 117 #define  GSWIP_MII_PCDU_TXDLY_MASK      GENMASK(2, 0)
 118 #define  GSWIP_MII_PCDU_RXDLY_MASK      GENMASK(9, 7)
 119
 120 /* GSWIP Core Registers */
 121 #define GSWIP_SWRES                     0x000
 122 #define  GSWIP_SWRES_R1                 BIT(1)  /* GSWIP Software reset */
 123 #define  GSWIP_SWRES_R0                 BIT(0)  /* GSWIP Hardware reset */
 124 #define GSWIP_VERSION                   0x013
 125 #define  GSWIP_VERSION_REV_SHIFT        0
 126 #define  GSWIP_VERSION_REV_MASK         GENMASK(7, 0)
 127 #define  GSWIP_VERSION_MOD_SHIFT        8
 128 #define  GSWIP_VERSION_MOD_MASK         GENMASK(15, 8)
 129 #define   GSWIP_VERSION_2_0             0x100
 130 #define   GSWIP_VERSION_2_1             0x021
 131 #define   GSWIP_VERSION_2_2             0x122
 132 #define   GSWIP_VERSION_2_2_ETC         0x022
 133
 134 #define GSWIP_BM_RAM_VAL(x)             (0x043 - (x))
 135 #define GSWIP_BM_RAM_ADDR               0x044
 136 #define GSWIP_BM_RAM_CTRL               0x045
 137 #define  GSWIP_BM_RAM_CTRL_BAS          BIT(15)
 138 #define  GSWIP_BM_RAM_CTRL_OPMOD        BIT(5)
 139 #define  GSWIP_BM_RAM_CTRL_ADDR_MASK    GENMASK(4, 0)
 140 #define GSWIP_BM_QUEUE_GCTRL            0x04A
 141 #define  GSWIP_BM_QUEUE_GCTRL_GL_MOD    BIT(10)
 142 /* buffer management Port Configuration Register */
 143 #define GSWIP_BM_PCFGp(p)               (0x080 + ((p) * 2))
 144 #define  GSWIP_BM_PCFG_CNTEN            BIT(0)  /* RMON Counter Enable */
 145 #define  GSWIP_BM_PCFG_IGCNT            BIT(1)  /* Ingres Special Tag RMON count */
 146 /* buffer management Port Control Register */
 147 #define GSWIP_BM_RMON_CTRLp(p)          (0x81 + ((p) * 2))
 148 #define  GSWIP_BM_CTRL_RMON_RAM1_RES    BIT(0)  /* Software Reset for RMON RAM 1 */
 149 #define  GSWIP_BM_CTRL_RMON_RAM2_RES    BIT(1)  /* Software Reset for RMON RAM 2 */
 150
 151 /* PCE */
 152 #define GSWIP_PCE_TBL_KEY(x)            (0x447 - (x))
 153 #define GSWIP_PCE_TBL_MASK              0x448
 154 #define GSWIP_PCE_TBL_VAL(x)            (0x44D - (x))
 155 #define GSWIP_PCE_TBL_ADDR              0x44E
 156 #define GSWIP_PCE_TBL_CTRL              0x44F
 157 #define  GSWIP_PCE_TBL_CTRL_BAS         BIT(15)
 158 #define  GSWIP_PCE_TBL_CTRL_TYPE        BIT(13)
 159 #define  GSWIP_PCE_TBL_CTRL_VLD         BIT(12)
 160 #define  GSWIP_PCE_TBL_CTRL_KEYFORM     BIT(11)
 161 #define  GSWIP_PCE_TBL_CTRL_GMAP_MASK   GENMASK(10, 7)
 162 #define  GSWIP_PCE_TBL_CTRL_OPMOD_MASK  GENMASK(6, 5)
 163 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADRD  0x00
 164 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR  0x20
 165 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSRD  0x40
 166 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSWR  0x60
 167 #define  GSWIP_PCE_TBL_CTRL_ADDR_MASK   GENMASK(4, 0)
 168 #define GSWIP_PCE_PMAP1                 0x453   /* Monitoring port map */
 169 #define GSWIP_PCE_PMAP2                 0x454   /* Default Multicast port map */
 170 #define GSWIP_PCE_PMAP3                 0x455   /* Default Unknown Unicast port map */
 171 #define GSWIP_PCE_GCTRL_0               0x456
 172 #define  GSWIP_PCE_GCTRL_0_MTFL         BIT(0)  /* MAC Table Flushing */
 173 #define  GSWIP_PCE_GCTRL_0_MC_VALID     BIT(3)
 174 #define  GSWIP_PCE_GCTRL_0_VLAN         BIT(14) /* VLAN aware Switching */
 175 #define GSWIP_PCE_GCTRL_1               0x457
 176 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK    BIT(2)  /* MAC Address table lock */
 177 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD        BIT(3) /* Mac address table lock forwarding mode */
 178 #define GSWIP_PCE_PCTRL_0p(p)           (0x480 + ((p) * 0xA))
 179 #define  GSWIP_PCE_PCTRL_0_TVM          BIT(5)  /* Transparent VLAN mode */
 180 #define  GSWIP_PCE_PCTRL_0_VREP         BIT(6)  /* VLAN Replace Mode */
 181 #define  GSWIP_PCE_PCTRL_0_INGRESS      BIT(11) /* Accept special tag in ingress */
 182 #define  GSWIP_PCE_PCTRL_0_PSTATE_LISTEN        0x0
 183 #define  GSWIP_PCE_PCTRL_0_PSTATE_RX            0x1
 184 #define  GSWIP_PCE_PCTRL_0_PSTATE_TX            0x2
 185 #define  GSWIP_PCE_PCTRL_0_PSTATE_LEARNING      0x3
 186 #define  GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING    0x7
 187 #define  GSWIP_PCE_PCTRL_0_PSTATE_MASK  GENMASK(2, 0)
 188 #define GSWIP_PCE_VCTRL(p)              (0x485 + ((p) * 0xA))
 189 #define  GSWIP_PCE_VCTRL_UVR            BIT(0)  /* Unknown VLAN Rule */
 190 #define  GSWIP_PCE_VCTRL_VIMR           BIT(3)  /* VLAN Ingress Member violation rule */
 191 #define  GSWIP_PCE_VCTRL_VEMR           BIT(4)  /* VLAN Egress Member violation rule */
 192 #define  GSWIP_PCE_VCTRL_VSR            BIT(5)  /* VLAN Security */
 193 #define  GSWIP_PCE_VCTRL_VID0           BIT(6)  /* Priority Tagged Rule */
 194 #define GSWIP_PCE_DEFPVID(p)            (0x486 + ((p) * 0xA))
 195
 196 #define GSWIP_MAC_FLEN                  0x8C5
 197 #define GSWIP_MAC_CTRL_0p(p)            (0x903 + ((p) * 0xC))
 198 #define  GSWIP_MAC_CTRL_0_PADEN         BIT(8)
 199 #define  GSWIP_MAC_CTRL_0_FCS_EN        BIT(7)
 200 #define  GSWIP_MAC_CTRL_0_FCON_MASK     0x0070
 201 #define  GSWIP_MAC_CTRL_0_FCON_AUTO     0x0000
 202 #define  GSWIP_MAC_CTRL_0_FCON_RX       0x0010
 203 #define  GSWIP_MAC_CTRL_0_FCON_TX       0x0020
 204 #define  GSWIP_MAC_CTRL_0_FCON_RXTX     0x0030
 205 #define  GSWIP_MAC_CTRL_0_FCON_NONE     0x0040
 206 #define  GSWIP_MAC_CTRL_0_FDUP_MASK     0x000C
 207 #define  GSWIP_MAC_CTRL_0_FDUP_AUTO     0x0000
 208 #define  GSWIP_MAC_CTRL_0_FDUP_EN       0x0004
 209 #define  GSWIP_MAC_CTRL_0_FDUP_DIS      0x000C
 210 #define  GSWIP_MAC_CTRL_0_GMII_MASK     0x0003
 211 #define  GSWIP_MAC_CTRL_0_GMII_AUTO     0x0000
 212 #define  GSWIP_MAC_CTRL_0_GMII_MII      0x0001
 213 #define  GSWIP_MAC_CTRL_0_GMII_RGMII    0x0002
 214 #define GSWIP_MAC_CTRL_2p(p)            (0x905 + ((p) * 0xC))
 215 #define GSWIP_MAC_CTRL_2_MLEN           BIT(3) /* Maximum Untagged Frame Lnegth */
 216
 217 /* Ethernet Switch Fetch DMA Port Control Register */
 218 #define GSWIP_FDMA_PCTRLp(p)            (0xA80 + ((p) * 0x6))
 219 #define  GSWIP_FDMA_PCTRL_EN            BIT(0)  /* FDMA Port Enable */
 220 #define  GSWIP_FDMA_PCTRL_STEN          BIT(1)  /* Special Tag Insertion Enable */
 221 #define  GSWIP_FDMA_PCTRL_VLANMOD_MASK  GENMASK(4, 3)   /* VLAN Modification Control */
 222 #define  GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3       /* VLAN Modification Control */
 223 #define  GSWIP_FDMA_PCTRL_VLANMOD_DIS   (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 224 #define  GSWIP_FDMA_PCTRL_VLANMOD_PRIO  (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 225 #define  GSWIP_FDMA_PCTRL_VLANMOD_ID    (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 226 #define  GSWIP_FDMA_PCTRL_VLANMOD_BOTH  (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 227
 228 /* Ethernet Switch Store DMA Port Control Register */
 229 #define GSWIP_SDMA_PCTRLp(p)            (0xBC0 + ((p) * 0x6))
 230 #define  GSWIP_SDMA_PCTRL_EN            BIT(0)  /* SDMA Port Enable */
 231 #define  GSWIP_SDMA_PCTRL_FCEN          BIT(1)  /* Flow Control Enable */
 232 #define  GSWIP_SDMA_PCTRL_PAUFWD        BIT(3)  /* Pause Frame Forwarding */
 233
 234 #define GSWIP_TABLE_ACTIVE_VLAN         0x01
 235 #define GSWIP_TABLE_VLAN_MAPPING        0x02
 236 #define GSWIP_TABLE_MAC_BRIDGE          0x0b
 237 #define  GSWIP_TABLE_MAC_BRIDGE_STATIC  0x01    /* Static not, aging entry */
 238
 239 #define XRX200_GPHY_FW_ALIGN    (16 * 1024)
 240
 241 struct gswip_hw_info {
 242         int max_ports;
 243         int cpu_port;
 244 };
 245
 246 struct xway_gphy_match_data {
 247         char *fe_firmware_name;
 248         char *ge_firmware_name;
 249 };
 250
 251 struct gswip_gphy_fw {
 252         struct clk *clk_gate;
 253         struct reset_control *reset;
 254         u32 fw_addr_offset;
 255         char *fw_name;
 256 };
 257
 258 struct gswip_vlan {
 259         struct net_device *bridge;
 260         u16 vid;
 261         u8 fid;
 262 };
 263
 264 struct gswip_priv {
 265         __iomem void *gswip;
 266         __iomem void *mdio;
 267         __iomem void *mii;
 268         const struct gswip_hw_info *hw_info;
 269         const struct xway_gphy_match_data *gphy_fw_name_cfg;
 270         struct dsa_switch *ds;
 271         struct device *dev;
 272         struct regmap *rcu_regmap;
 273         struct gswip_vlan vlans[64];
 274         int num_gphy_fw;
 275         struct gswip_gphy_fw *gphy_fw;
 276         u32 port_vlan_filter;
 277 };
 278
 279 struct gswip_pce_table_entry {
 280         u16 index;      // PCE_TBL_ADDR.ADDR = pData->table_index
 281         u16 table;      // PCE_TBL_CTRL.ADDR = pData->table
 282         u16 key[8];
 283         u16 val[5];
 284         u16 mask;
 285         u8 gmap;
 286         bool type;
 287         bool valid;
 288         bool key_mode;
 289 };
 290
 291 struct gswip_rmon_cnt_desc {
 292         unsigned int size;
 293         unsigned int offset;
 294         const char *name;
 295 };
 296
 297 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
 298
 299 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
 300         /** Receive Packet Count (only packets that are accepted and not discarded). */
 301         MIB_DESC(1, 0x1F, "RxGoodPkts"),
 302         MIB_DESC(1, 0x23, "RxUnicastPkts"),
 303         MIB_DESC(1, 0x22, "RxMulticastPkts"),
 304         MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
 305         MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
 306         MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
 307         MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
 308         MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
 309         MIB_DESC(1, 0x20, "RxGoodPausePkts"),
 310         MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
 311         MIB_DESC(1, 0x12, "Rx64BytePkts"),
 312         MIB_DESC(1, 0x13, "Rx127BytePkts"),
 313         MIB_DESC(1, 0x14, "Rx255BytePkts"),
 314         MIB_DESC(1, 0x15, "Rx511BytePkts"),
 315         MIB_DESC(1, 0x16, "Rx1023BytePkts"),
 316         /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
 317         MIB_DESC(1, 0x17, "RxMaxBytePkts"),
 318         MIB_DESC(1, 0x18, "RxDroppedPkts"),
 319         MIB_DESC(1, 0x19, "RxFilteredPkts"),
 320         MIB_DESC(2, 0x24, "RxGoodBytes"),
 321         MIB_DESC(2, 0x26, "RxBadBytes"),
 322         MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
 323         MIB_DESC(1, 0x0C, "TxGoodPkts"),
 324         MIB_DESC(1, 0x06, "TxUnicastPkts"),
 325         MIB_DESC(1, 0x07, "TxMulticastPkts"),
 326         MIB_DESC(1, 0x00, "Tx64BytePkts"),
 327         MIB_DESC(1, 0x01, "Tx127BytePkts"),
 328         MIB_DESC(1, 0x02, "Tx255BytePkts"),
 329         MIB_DESC(1, 0x03, "Tx511BytePkts"),
 330         MIB_DESC(1, 0x04, "Tx1023BytePkts"),
 331         /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
 332         MIB_DESC(1, 0x05, "TxMaxBytePkts"),
 333         MIB_DESC(1, 0x08, "TxSingleCollCount"),
 334         MIB_DESC(1, 0x09, "TxMultCollCount"),
 335         MIB_DESC(1, 0x0A, "TxLateCollCount"),
 336         MIB_DESC(1, 0x0B, "TxExcessCollCount"),
 337         MIB_DESC(1, 0x0D, "TxPauseCount"),
 338         MIB_DESC(1, 0x10, "TxDroppedPkts"),
 339         MIB_DESC(2, 0x0E, "TxGoodBytes"),
 340 };
 341
 342 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
 343 {
 344         return __raw_readl(priv->gswip + (offset * 4));
 345 }
 346
 347 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
 348 {
 349         __raw_writel(val, priv->gswip + (offset * 4));
 350 }
 351
 352 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
 353                               u32 offset)
 354 {
 355         u32 val = gswip_switch_r(priv, offset);
 356
 357         val &= ~(clear);
 358         val |= set;
 359         gswip_switch_w(priv, val, offset);
 360 }
 361
 362 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
 363                                   u32 cleared)
 364 {
 365         u32 val;
 366
 367         return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
 368                                   (val & cleared) == 0, 20, 50000);
 369 }
 370
 371 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
 372 {
 373         return __raw_readl(priv->mdio + (offset * 4));
 374 }
 375
 376 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
 377 {
 378         __raw_writel(val, priv->mdio + (offset * 4));
 379 }
 380
 381 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
 382                             u32 offset)
 383 {
 384         u32 val = gswip_mdio_r(priv, offset);
 385
 386         val &= ~(clear);
 387         val |= set;
 388         gswip_mdio_w(priv, val, offset);
 389 }
 390
 391 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
 392 {
 393         return __raw_readl(priv->mii + (offset * 4));
 394 }
 395
 396 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
 397 {
 398         __raw_writel(val, priv->mii + (offset * 4));
 399 }
 400
 401 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
 402                            u32 offset)
 403 {
 404         u32 val = gswip_mii_r(priv, offset);
 405
 406         val &= ~(clear);
 407         val |= set;
 408         gswip_mii_w(priv, val, offset);
 409 }
 410
 411 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
 412                                int port)
 413 {
 414         /* There's no MII_CFG register for the CPU port */
 415         if (!dsa_is_cpu_port(priv->ds, port))
 416                 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
 417 }
 418
 419 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
 420                                 int port)
 421 {
 422         switch (port) {
 423         case 0:
 424                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
 425                 break;
 426         case 1:
 427                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
 428                 break;
 429         case 5:
 430                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
 431                 break;
 432         }
 433 }
 434
 435 static int gswip_mdio_poll(struct gswip_priv *priv)
 436 {
 437         int cnt = 100;
 438
 439         while (likely(cnt--)) {
 440                 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
 441
 442                 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
 443                         return 0;
 444                 usleep_range(20, 40);
 445         }
 446
 447         return -ETIMEDOUT;
 448 }
 449
 450 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
 451 {
 452         struct gswip_priv *priv = bus->priv;
 453         int err;
 454
 455         err = gswip_mdio_poll(priv);
 456         if (err) {
 457                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 458                 return err;
 459         }
 460
 461         gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
 462         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
 463                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 464                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 465                 GSWIP_MDIO_CTRL);
 466
 467         return 0;
 468 }
 469
 470 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
 471 {
 472         struct gswip_priv *priv = bus->priv;
 473         int err;
 474
 475         err = gswip_mdio_poll(priv);
 476         if (err) {
 477                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 478                 return err;
 479         }
 480
 481         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
 482                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 483                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 484                 GSWIP_MDIO_CTRL);
 485
 486         err = gswip_mdio_poll(priv);
 487         if (err) {
 488                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 489                 return err;
 490         }
 491
 492         return gswip_mdio_r(priv, GSWIP_MDIO_READ);
 493 }
 494
 495 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
 496 {
 497         struct dsa_switch *ds = priv->ds;
 498         int err;
 499
 500         ds->slave_mii_bus = mdiobus_alloc();
 501         if (!ds->slave_mii_bus)
 502                 return -ENOMEM;
 503
 504         ds->slave_mii_bus->priv = priv;
 505         ds->slave_mii_bus->read = gswip_mdio_rd;
 506         ds->slave_mii_bus->write = gswip_mdio_wr;
 507         ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
 508         snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
 509                  dev_name(priv->dev));
 510         ds->slave_mii_bus->parent = priv->dev;
 511         ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
 512
 513         err = of_mdiobus_register(ds->slave_mii_bus, mdio_np);
 514         if (err)
 515                 mdiobus_free(ds->slave_mii_bus);
 516
 517         return err;
 518 }
 519
 520 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
 521                                       struct gswip_pce_table_entry *tbl)
 522 {
 523         int i;
 524         int err;
 525         u16 crtl;
 526         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
 527                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
 528
 529         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 530                                      GSWIP_PCE_TBL_CTRL_BAS);
 531         if (err)
 532                 return err;
 533
 534         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 535         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 536                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 537                           tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
 538                           GSWIP_PCE_TBL_CTRL);
 539
 540         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 541                                      GSWIP_PCE_TBL_CTRL_BAS);
 542         if (err)
 543                 return err;
 544
 545         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 546                 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
 547
 548         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 549                 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
 550
 551         tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
 552
 553         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 554
 555         tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
 556         tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
 557         tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
 558
 559         return 0;
 560 }
 561
 562 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
 563                                        struct gswip_pce_table_entry *tbl)
 564 {
 565         int i;
 566         int err;
 567         u16 crtl;
 568         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
 569                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
 570
 571         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 572                                      GSWIP_PCE_TBL_CTRL_BAS);
 573         if (err)
 574                 return err;
 575
 576         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 577         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 578                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 579                           tbl->table | addr_mode,
 580                           GSWIP_PCE_TBL_CTRL);
 581
 582         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 583                 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
 584
 585         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 586                 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
 587
 588         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 589                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 590                           tbl->table | addr_mode,
 591                           GSWIP_PCE_TBL_CTRL);
 592
 593         gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
 594
 595         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 596         crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
 597                   GSWIP_PCE_TBL_CTRL_GMAP_MASK);
 598         if (tbl->type)
 599                 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
 600         if (tbl->valid)
 601                 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
 602         crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
 603         crtl |= GSWIP_PCE_TBL_CTRL_BAS;
 604         gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
 605
 606         return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 607                                       GSWIP_PCE_TBL_CTRL_BAS);
 608 }
 609
 610 /* Add the LAN port into a bridge with the CPU port by
 611  * default. This prevents automatic forwarding of
 612  * packages between the LAN ports when no explicit
 613  * bridge is configured.
 614  */
 615 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
 616 {
 617         struct gswip_pce_table_entry vlan_active = {0,};
 618         struct gswip_pce_table_entry vlan_mapping = {0,};
 619         unsigned int cpu_port = priv->hw_info->cpu_port;
 620         unsigned int max_ports = priv->hw_info->max_ports;
 621         int err;
 622
 623         if (port >= max_ports) {
 624                 dev_err(priv->dev, "single port for %i supported\n", port);
 625                 return -EIO;
 626         }
 627
 628         vlan_active.index = port + 1;
 629         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 630         vlan_active.key[0] = 0; /* vid */
 631         vlan_active.val[0] = port + 1 /* fid */;
 632         vlan_active.valid = add;
 633         err = gswip_pce_table_entry_write(priv, &vlan_active);
 634         if (err) {
 635                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 636                 return err;
 637         }
 638
 639         if (!add)
 640                 return 0;
 641
 642         vlan_mapping.index = port + 1;
 643         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 644         vlan_mapping.val[0] = 0 /* vid */;
 645         vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
 646         vlan_mapping.val[2] = 0;
 647         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 648         if (err) {
 649                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 650                 return err;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int gswip_port_enable(struct dsa_switch *ds, int port,
 657                              struct phy_device *phydev)
 658 {
 659         struct gswip_priv *priv = ds->priv;
 660         int err;
 661
 662         if (!dsa_is_user_port(ds, port))
 663                 return 0;
 664
 665         if (!dsa_is_cpu_port(ds, port)) {
 666                 err = gswip_add_single_port_br(priv, port, true);
 667                 if (err)
 668                         return err;
 669         }
 670
 671         /* RMON Counter Enable for port */
 672         gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
 673
 674         /* enable port fetch/store dma & VLAN Modification */
 675         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
 676                                    GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
 677                          GSWIP_FDMA_PCTRLp(port));
 678         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
 679                           GSWIP_SDMA_PCTRLp(port));
 680
 681         if (!dsa_is_cpu_port(ds, port)) {
 682                 u32 mdio_phy = 0;
 683
 684                 if (phydev)
 685                         mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
 686
 687                 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
 688                                 GSWIP_MDIO_PHYp(port));
 689         }
 690
 691         return 0;
 692 }
 693
 694 static void gswip_port_disable(struct dsa_switch *ds, int port)
 695 {
 696         struct gswip_priv *priv = ds->priv;
 697
 698         if (!dsa_is_user_port(ds, port))
 699                 return;
 700
 701         gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
 702                           GSWIP_FDMA_PCTRLp(port));
 703         gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
 704                           GSWIP_SDMA_PCTRLp(port));
 705 }
 706
 707 static int gswip_pce_load_microcode(struct gswip_priv *priv)
 708 {
 709         int i;
 710         int err;
 711
 712         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 713                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 714                           GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
 715         gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
 716
 717         for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
 718                 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
 719                 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
 720                                GSWIP_PCE_TBL_VAL(0));
 721                 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
 722                                GSWIP_PCE_TBL_VAL(1));
 723                 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
 724                                GSWIP_PCE_TBL_VAL(2));
 725                 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
 726                                GSWIP_PCE_TBL_VAL(3));
 727
 728                 /* start the table access: */
 729                 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
 730                                   GSWIP_PCE_TBL_CTRL);
 731                 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 732                                              GSWIP_PCE_TBL_CTRL_BAS);
 733                 if (err)
 734                         return err;
 735         }
 736
 737         /* tell the switch that the microcode is loaded */
 738         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
 739                           GSWIP_PCE_GCTRL_0);
 740
 741         return 0;
 742 }
 743
 744 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
 745                                      bool vlan_filtering,
 746                                      struct switchdev_trans *trans)
 747 {
 748         struct gswip_priv *priv = ds->priv;
 749
 750         /* Do not allow changing the VLAN filtering options while in bridge */
 751         if (switchdev_trans_ph_prepare(trans)) {
 752                 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
 753
 754                 if (!bridge)
 755                         return 0;
 756
 757                 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering)
 758                         return -EIO;
 759
 760                 return 0;
 761         }
 762
 763         if (vlan_filtering) {
 764                 /* Use port based VLAN tag */
 765                 gswip_switch_mask(priv,
 766                                   GSWIP_PCE_VCTRL_VSR,
 767                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 768                                   GSWIP_PCE_VCTRL_VEMR,
 769                                   GSWIP_PCE_VCTRL(port));
 770                 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
 771                                   GSWIP_PCE_PCTRL_0p(port));
 772         } else {
 773                 /* Use port based VLAN tag */
 774                 gswip_switch_mask(priv,
 775                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 776                                   GSWIP_PCE_VCTRL_VEMR,
 777                                   GSWIP_PCE_VCTRL_VSR,
 778                                   GSWIP_PCE_VCTRL(port));
 779                 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
 780                                   GSWIP_PCE_PCTRL_0p(port));
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int gswip_setup(struct dsa_switch *ds)
 787 {
 788         struct gswip_priv *priv = ds->priv;
 789         unsigned int cpu_port = priv->hw_info->cpu_port;
 790         int i;
 791         int err;
 792
 793         gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
 794         usleep_range(5000, 10000);
 795         gswip_switch_w(priv, 0, GSWIP_SWRES);
 796
 797         /* disable port fetch/store dma on all ports */
 798         for (i = 0; i < priv->hw_info->max_ports; i++) {
 799                 struct switchdev_trans trans;
 800
 801                 /* Skip the prepare phase, this shouldn't return an error
 802                  * during setup.
 803                  */
 804                 trans.ph_prepare = false;
 805
 806                 gswip_port_disable(ds, i);
 807                 gswip_port_vlan_filtering(ds, i, false, &trans);
 808         }
 809
 810         /* enable Switch */
 811         gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
 812
 813         err = gswip_pce_load_microcode(priv);
 814         if (err) {
 815                 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
 816                 return err;
 817         }
 818
 819         /* Default unknown Broadcast/Multicast/Unicast port maps */
 820         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
 821         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
 822         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
 823
 824         /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
 825          * interoperability problem with this auto polling mechanism because
 826          * their status registers think that the link is in a different state
 827          * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
 828          * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
 829          * auto polling state machine consider the link being negotiated with
 830          * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
 831          * to the switch port being completely dead (RX and TX are both not
 832          * working).
 833          * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
 834          * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
 835          * it would work fine for a few minutes to hours and then stop, on
 836          * other device it would no traffic could be sent or received at all.
 837          * Testing shows that when PHY auto polling is disabled these problems
 838          * go away.
 839          */
 840         gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
 841
 842         /* Configure the MDIO Clock 2.5 MHz */
 843         gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
 844
 845         /* Disable the xMII interface and clear it's isolation bit */
 846         for (i = 0; i < priv->hw_info->max_ports; i++)
 847                 gswip_mii_mask_cfg(priv,
 848                                    GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
 849                                    0, i);
 850
 851         /* enable special tag insertion on cpu port */
 852         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
 853                           GSWIP_FDMA_PCTRLp(cpu_port));
 854
 855         /* accept special tag in ingress direction */
 856         gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
 857                           GSWIP_PCE_PCTRL_0p(cpu_port));
 858
 859         gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
 860                           GSWIP_MAC_CTRL_2p(cpu_port));
 861         gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN,
 862                        GSWIP_MAC_FLEN);
 863         gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
 864                           GSWIP_BM_QUEUE_GCTRL);
 865
 866         /* VLAN aware Switching */
 867         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
 868
 869         /* Flush MAC Table */
 870         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
 871
 872         err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
 873                                      GSWIP_PCE_GCTRL_0_MTFL);
 874         if (err) {
 875                 dev_err(priv->dev, "MAC flushing didn't finish\n");
 876                 return err;
 877         }
 878
 879         gswip_port_enable(ds, cpu_port, NULL);
 880         return 0;
 881 }
 882
 883 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
 884                                                     int port,
 885                                                     enum dsa_tag_protocol mp)
 886 {
 887         return DSA_TAG_PROTO_GSWIP;
 888 }
 889
 890 static int gswip_vlan_active_create(struct gswip_priv *priv,
 891                                     struct net_device *bridge,
 892                                     int fid, u16 vid)
 893 {
 894         struct gswip_pce_table_entry vlan_active = {0,};
 895         unsigned int max_ports = priv->hw_info->max_ports;
 896         int idx = -1;
 897         int err;
 898         int i;
 899
 900         /* Look for a free slot */
 901         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 902                 if (!priv->vlans[i].bridge) {
 903                         idx = i;
 904                         break;
 905                 }
 906         }
 907
 908         if (idx == -1)
 909                 return -ENOSPC;
 910
 911         if (fid == -1)
 912                 fid = idx;
 913
 914         vlan_active.index = idx;
 915         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 916         vlan_active.key[0] = vid;
 917         vlan_active.val[0] = fid;
 918         vlan_active.valid = true;
 919
 920         err = gswip_pce_table_entry_write(priv, &vlan_active);
 921         if (err) {
 922                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 923                 return err;
 924         }
 925
 926         priv->vlans[idx].bridge = bridge;
 927         priv->vlans[idx].vid = vid;
 928         priv->vlans[idx].fid = fid;
 929
 930         return idx;
 931 }
 932
 933 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
 934 {
 935         struct gswip_pce_table_entry vlan_active = {0,};
 936         int err;
 937
 938         vlan_active.index = idx;
 939         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 940         vlan_active.valid = false;
 941         err = gswip_pce_table_entry_write(priv, &vlan_active);
 942         if (err)
 943                 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
 944         priv->vlans[idx].bridge = NULL;
 945
 946         return err;
 947 }
 948
 949 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
 950                                   struct net_device *bridge, int port)
 951 {
 952         struct gswip_pce_table_entry vlan_mapping = {0,};
 953         unsigned int max_ports = priv->hw_info->max_ports;
 954         unsigned int cpu_port = priv->hw_info->cpu_port;
 955         bool active_vlan_created = false;
 956         int idx = -1;
 957         int i;
 958         int err;
 959
 960         /* Check if there is already a page for this bridge */
 961         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 962                 if (priv->vlans[i].bridge == bridge) {
 963                         idx = i;
 964                         break;
 965                 }
 966         }
 967
 968         /* If this bridge is not programmed yet, add a Active VLAN table
 969          * entry in a free slot and prepare the VLAN mapping table entry.
 970          */
 971         if (idx == -1) {
 972                 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
 973                 if (idx < 0)
 974                         return idx;
 975                 active_vlan_created = true;
 976
 977                 vlan_mapping.index = idx;
 978                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 979                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
 980                 vlan_mapping.val[0] = 0;
 981         } else {
 982                 /* Read the existing VLAN mapping entry from the switch */
 983                 vlan_mapping.index = idx;
 984                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 985                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
 986                 if (err) {
 987                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
 988                                 err);
 989                         return err;
 990                 }
 991         }
 992
 993         /* Update the VLAN mapping entry and write it to the switch */
 994         vlan_mapping.val[1] |= BIT(cpu_port);
 995         vlan_mapping.val[1] |= BIT(port);
 996         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 997         if (err) {
 998                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 999                 /* In case an Active VLAN was creaetd delete it again */
1000                 if (active_vlan_created)
1001                         gswip_vlan_active_remove(priv, idx);
1002                 return err;
1003         }
1004
1005         gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1006         return 0;
1007 }
1008
1009 static int gswip_vlan_add_aware(struct gswip_priv *priv,
1010                                 struct net_device *bridge, int port,
1011                                 u16 vid, bool untagged,
1012                                 bool pvid)
1013 {
1014         struct gswip_pce_table_entry vlan_mapping = {0,};
1015         unsigned int max_ports = priv->hw_info->max_ports;
1016         unsigned int cpu_port = priv->hw_info->cpu_port;
1017         bool active_vlan_created = false;
1018         int idx = -1;
1019         int fid = -1;
1020         int i;
1021         int err;
1022
1023         /* Check if there is already a page for this bridge */
1024         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1025                 if (priv->vlans[i].bridge == bridge) {
1026                         if (fid != -1 && fid != priv->vlans[i].fid)
1027                                 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1028                         fid = priv->vlans[i].fid;
1029                         if (priv->vlans[i].vid == vid) {
1030                                 idx = i;
1031                                 break;
1032                         }
1033                 }
1034         }
1035
1036         /* If this bridge is not programmed yet, add a Active VLAN table
1037          * entry in a free slot and prepare the VLAN mapping table entry.
1038          */
1039         if (idx == -1) {
1040                 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1041                 if (idx < 0)
1042                         return idx;
1043                 active_vlan_created = true;
1044
1045                 vlan_mapping.index = idx;
1046                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1047                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1048                 vlan_mapping.val[0] = vid;
1049         } else {
1050                 /* Read the existing VLAN mapping entry from the switch */
1051                 vlan_mapping.index = idx;
1052                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1053                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1054                 if (err) {
1055                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1056                                 err);
1057                         return err;
1058                 }
1059         }
1060
1061         vlan_mapping.val[0] = vid;
1062         /* Update the VLAN mapping entry and write it to the switch */
1063         vlan_mapping.val[1] |= BIT(cpu_port);
1064         vlan_mapping.val[2] |= BIT(cpu_port);
1065         vlan_mapping.val[1] |= BIT(port);
1066         if (untagged)
1067                 vlan_mapping.val[2] &= ~BIT(port);
1068         else
1069                 vlan_mapping.val[2] |= BIT(port);
1070         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1071         if (err) {
1072                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1073                 /* In case an Active VLAN was creaetd delete it again */
1074                 if (active_vlan_created)
1075                         gswip_vlan_active_remove(priv, idx);
1076                 return err;
1077         }
1078
1079         if (pvid)
1080                 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1081
1082         return 0;
1083 }
1084
1085 static int gswip_vlan_remove(struct gswip_priv *priv,
1086                              struct net_device *bridge, int port,
1087                              u16 vid, bool pvid, bool vlan_aware)
1088 {
1089         struct gswip_pce_table_entry vlan_mapping = {0,};
1090         unsigned int max_ports = priv->hw_info->max_ports;
1091         unsigned int cpu_port = priv->hw_info->cpu_port;
1092         int idx = -1;
1093         int i;
1094         int err;
1095
1096         /* Check if there is already a page for this bridge */
1097         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1098                 if (priv->vlans[i].bridge == bridge &&
1099                     (!vlan_aware || priv->vlans[i].vid == vid)) {
1100                         idx = i;
1101                         break;
1102                 }
1103         }
1104
1105         if (idx == -1) {
1106                 dev_err(priv->dev, "bridge to leave does not exists\n");
1107                 return -ENOENT;
1108         }
1109
1110         vlan_mapping.index = idx;
1111         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1112         err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1113         if (err) {
1114                 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1115                 return err;
1116         }
1117
1118         vlan_mapping.val[1] &= ~BIT(port);
1119         vlan_mapping.val[2] &= ~BIT(port);
1120         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1121         if (err) {
1122                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1123                 return err;
1124         }
1125
1126         /* In case all ports are removed from the bridge, remove the VLAN */
1127         if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1128                 err = gswip_vlan_active_remove(priv, idx);
1129                 if (err) {
1130                         dev_err(priv->dev, "failed to write active VLAN: %d\n",
1131                                 err);
1132                         return err;
1133                 }
1134         }
1135
1136         /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1137         if (pvid)
1138                 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1139
1140         return 0;
1141 }
1142
1143 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1144                                   struct net_device *bridge)
1145 {
1146         struct gswip_priv *priv = ds->priv;
1147         int err;
1148
1149         /* When the bridge uses VLAN filtering we have to configure VLAN
1150          * specific bridges. No bridge is configured here.
1151          */
1152         if (!br_vlan_enabled(bridge)) {
1153                 err = gswip_vlan_add_unaware(priv, bridge, port);
1154                 if (err)
1155                         return err;
1156                 priv->port_vlan_filter &= ~BIT(port);
1157         } else {
1158                 priv->port_vlan_filter |= BIT(port);
1159         }
1160         return gswip_add_single_port_br(priv, port, false);
1161 }
1162
1163 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1164                                     struct net_device *bridge)
1165 {
1166         struct gswip_priv *priv = ds->priv;
1167
1168         gswip_add_single_port_br(priv, port, true);
1169
1170         /* When the bridge uses VLAN filtering we have to configure VLAN
1171          * specific bridges. No bridge is configured here.
1172          */
1173         if (!br_vlan_enabled(bridge))
1174                 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1175 }
1176
1177 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1178                                    const struct switchdev_obj_port_vlan *vlan)
1179 {
1180         struct gswip_priv *priv = ds->priv;
1181         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1182         unsigned int max_ports = priv->hw_info->max_ports;
1183         u16 vid;
1184         int i;
1185         int pos = max_ports;
1186
1187         /* We only support VLAN filtering on bridges */
1188         if (!dsa_is_cpu_port(ds, port) && !bridge)
1189                 return -EOPNOTSUPP;
1190
1191         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1192                 int idx = -1;
1193
1194                 /* Check if there is already a page for this VLAN */
1195                 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1196                         if (priv->vlans[i].bridge == bridge &&
1197                             priv->vlans[i].vid == vid) {
1198                                 idx = i;
1199                                 break;
1200                         }
1201                 }
1202
1203                 /* If this VLAN is not programmed yet, we have to reserve
1204                  * one entry in the VLAN table. Make sure we start at the
1205                  * next position round.
1206                  */
1207                 if (idx == -1) {
1208                         /* Look for a free slot */
1209                         for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1210                                 if (!priv->vlans[pos].bridge) {
1211                                         idx = pos;
1212                                         pos++;
1213                                         break;
1214                                 }
1215                         }
1216
1217                         if (idx == -1)
1218                                 return -ENOSPC;
1219                 }
1220         }
1221
1222         return 0;
1223 }
1224
1225 static void gswip_port_vlan_add(struct dsa_switch *ds, int port,
1226                                 const struct switchdev_obj_port_vlan *vlan)
1227 {
1228         struct gswip_priv *priv = ds->priv;
1229         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1230         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1231         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1232         u16 vid;
1233
1234         /* We have to receive all packets on the CPU port and should not
1235          * do any VLAN filtering here. This is also called with bridge
1236          * NULL and then we do not know for which bridge to configure
1237          * this.
1238          */
1239         if (dsa_is_cpu_port(ds, port))
1240                 return;
1241
1242         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1243                 gswip_vlan_add_aware(priv, bridge, port, vid, untagged, pvid);
1244 }
1245
1246 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1247                                const struct switchdev_obj_port_vlan *vlan)
1248 {
1249         struct gswip_priv *priv = ds->priv;
1250         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1251         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1252         u16 vid;
1253         int err;
1254
1255         /* We have to receive all packets on the CPU port and should not
1256          * do any VLAN filtering here. This is also called with bridge
1257          * NULL and then we do not know for which bridge to configure
1258          * this.
1259          */
1260         if (dsa_is_cpu_port(ds, port))
1261                 return 0;
1262
1263         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1264                 err = gswip_vlan_remove(priv, bridge, port, vid, pvid, true);
1265                 if (err)
1266                         return err;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1273 {
1274         struct gswip_priv *priv = ds->priv;
1275         struct gswip_pce_table_entry mac_bridge = {0,};
1276         int i;
1277         int err;
1278
1279         for (i = 0; i < 2048; i++) {
1280                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1281                 mac_bridge.index = i;
1282
1283                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1284                 if (err) {
1285                         dev_err(priv->dev, "failed to read mac bridge: %d\n",
1286                                 err);
1287                         return;
1288                 }
1289
1290                 if (!mac_bridge.valid)
1291                         continue;
1292
1293                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1294                         continue;
1295
1296                 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1297                         continue;
1298
1299                 mac_bridge.valid = false;
1300                 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1301                 if (err) {
1302                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1303                                 err);
1304                         return;
1305                 }
1306         }
1307 }
1308
1309 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1310 {
1311         struct gswip_priv *priv = ds->priv;
1312         u32 stp_state;
1313
1314         switch (state) {
1315         case BR_STATE_DISABLED:
1316                 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1317                                   GSWIP_SDMA_PCTRLp(port));
1318                 return;
1319         case BR_STATE_BLOCKING:
1320         case BR_STATE_LISTENING:
1321                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1322                 break;
1323         case BR_STATE_LEARNING:
1324                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1325                 break;
1326         case BR_STATE_FORWARDING:
1327                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1328                 break;
1329         default:
1330                 dev_err(priv->dev, "invalid STP state: %d\n", state);
1331                 return;
1332         }
1333
1334         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1335                           GSWIP_SDMA_PCTRLp(port));
1336         gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1337                           GSWIP_PCE_PCTRL_0p(port));
1338 }
1339
1340 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1341                           const unsigned char *addr, u16 vid, bool add)
1342 {
1343         struct gswip_priv *priv = ds->priv;
1344         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1345         struct gswip_pce_table_entry mac_bridge = {0,};
1346         unsigned int cpu_port = priv->hw_info->cpu_port;
1347         int fid = -1;
1348         int i;
1349         int err;
1350
1351         if (!bridge)
1352                 return -EINVAL;
1353
1354         for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1355                 if (priv->vlans[i].bridge == bridge) {
1356                         fid = priv->vlans[i].fid;
1357                         break;
1358                 }
1359         }
1360
1361         if (fid == -1) {
1362                 dev_err(priv->dev, "Port not part of a bridge\n");
1363                 return -EINVAL;
1364         }
1365
1366         mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1367         mac_bridge.key_mode = true;
1368         mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1369         mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1370         mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1371         mac_bridge.key[3] = fid;
1372         mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1373         mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1374         mac_bridge.valid = add;
1375
1376         err = gswip_pce_table_entry_write(priv, &mac_bridge);
1377         if (err)
1378                 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1379
1380         return err;
1381 }
1382
1383 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1384                               const unsigned char *addr, u16 vid)
1385 {
1386         return gswip_port_fdb(ds, port, addr, vid, true);
1387 }
1388
1389 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1390                               const unsigned char *addr, u16 vid)
1391 {
1392         return gswip_port_fdb(ds, port, addr, vid, false);
1393 }
1394
1395 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1396                                dsa_fdb_dump_cb_t *cb, void *data)
1397 {
1398         struct gswip_priv *priv = ds->priv;
1399         struct gswip_pce_table_entry mac_bridge = {0,};
1400         unsigned char addr[6];
1401         int i;
1402         int err;
1403
1404         for (i = 0; i < 2048; i++) {
1405                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1406                 mac_bridge.index = i;
1407
1408                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1409                 if (err) {
1410                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1411                                 err);
1412                         return err;
1413                 }
1414
1415                 if (!mac_bridge.valid)
1416                         continue;
1417
1418                 addr[5] = mac_bridge.key[0] & 0xff;
1419                 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1420                 addr[3] = mac_bridge.key[1] & 0xff;
1421                 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1422                 addr[1] = mac_bridge.key[2] & 0xff;
1423                 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1424                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1425                         if (mac_bridge.val[0] & BIT(port)) {
1426                                 err = cb(addr, 0, true, data);
1427                                 if (err)
1428                                         return err;
1429                         }
1430                 } else {
1431                         if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
1432                                 err = cb(addr, 0, false, data);
1433                                 if (err)
1434                                         return err;
1435                         }
1436                 }
1437         }
1438         return 0;
1439 }
1440
1441 static void gswip_phylink_validate(struct dsa_switch *ds, int port,
1442                                    unsigned long *supported,
1443                                    struct phylink_link_state *state)
1444 {
1445         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1446
1447         switch (port) {
1448         case 0:
1449         case 1:
1450                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1451                     state->interface != PHY_INTERFACE_MODE_MII &&
1452                     state->interface != PHY_INTERFACE_MODE_REVMII &&
1453                     state->interface != PHY_INTERFACE_MODE_RMII)
1454                         goto unsupported;
1455                 break;
1456         case 2:
1457         case 3:
1458         case 4:
1459                 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1460                         goto unsupported;
1461                 break;
1462         case 5:
1463                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1464                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1465                         goto unsupported;
1466                 break;
1467         default:
1468                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1469                 dev_err(ds->dev, "Unsupported port: %i\n", port);
1470                 return;
1471         }
1472
1473         /* Allow all the expected bits */
1474         phylink_set(mask, Autoneg);
1475         phylink_set_port_modes(mask);
1476         phylink_set(mask, Pause);
1477         phylink_set(mask, Asym_Pause);
1478
1479         /* With the exclusion of MII, Reverse MII and Reduced MII, we
1480          * support Gigabit, including Half duplex
1481          */
1482         if (state->interface != PHY_INTERFACE_MODE_MII &&
1483             state->interface != PHY_INTERFACE_MODE_REVMII &&
1484             state->interface != PHY_INTERFACE_MODE_RMII) {
1485                 phylink_set(mask, 1000baseT_Full);
1486                 phylink_set(mask, 1000baseT_Half);
1487         }
1488
1489         phylink_set(mask, 10baseT_Half);
1490         phylink_set(mask, 10baseT_Full);
1491         phylink_set(mask, 100baseT_Half);
1492         phylink_set(mask, 100baseT_Full);
1493
1494         bitmap_and(supported, supported, mask,
1495                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1496         bitmap_and(state->advertising, state->advertising, mask,
1497                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1498         return;
1499
1500 unsupported:
1501         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1502         dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1503                 phy_modes(state->interface), port);
1504         return;
1505 }
1506
1507 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1508 {
1509         u32 mdio_phy;
1510
1511         if (link)
1512                 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1513         else
1514                 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1515
1516         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1517                         GSWIP_MDIO_PHYp(port));
1518 }
1519
1520 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1521                                  phy_interface_t interface)
1522 {
1523         u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1524
1525         switch (speed) {
1526         case SPEED_10:
1527                 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1528
1529                 if (interface == PHY_INTERFACE_MODE_RMII)
1530                         mii_cfg = GSWIP_MII_CFG_RATE_M50;
1531                 else
1532                         mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1533
1534                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1535                 break;
1536
1537         case SPEED_100:
1538                 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1539
1540                 if (interface == PHY_INTERFACE_MODE_RMII)
1541                         mii_cfg = GSWIP_MII_CFG_RATE_M50;
1542                 else
1543                         mii_cfg = GSWIP_MII_CFG_RATE_M25;
1544
1545                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1546                 break;
1547
1548         case SPEED_1000:
1549                 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1550
1551                 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1552
1553                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1554                 break;
1555         }
1556
1557         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1558                         GSWIP_MDIO_PHYp(port));
1559         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1560         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1561                           GSWIP_MAC_CTRL_0p(port));
1562 }
1563
1564 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1565 {
1566         u32 mac_ctrl_0, mdio_phy;
1567
1568         if (duplex == DUPLEX_FULL) {
1569                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1570                 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1571         } else {
1572                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1573                 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1574         }
1575
1576         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1577                           GSWIP_MAC_CTRL_0p(port));
1578         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1579                         GSWIP_MDIO_PHYp(port));
1580 }
1581
1582 static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1583                                  bool tx_pause, bool rx_pause)
1584 {
1585         u32 mac_ctrl_0, mdio_phy;
1586
1587         if (tx_pause && rx_pause) {
1588                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1589                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1590                            GSWIP_MDIO_PHY_FCONRX_EN;
1591         } else if (tx_pause) {
1592                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1593                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1594                            GSWIP_MDIO_PHY_FCONRX_DIS;
1595         } else if (rx_pause) {
1596                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1597                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1598                            GSWIP_MDIO_PHY_FCONRX_EN;
1599         } else {
1600                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1601                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1602                            GSWIP_MDIO_PHY_FCONRX_DIS;
1603         }
1604
1605         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1606                           mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1607         gswip_mdio_mask(priv,
1608                         GSWIP_MDIO_PHY_FCONTX_MASK |
1609                         GSWIP_MDIO_PHY_FCONRX_MASK,
1610                         mdio_phy, GSWIP_MDIO_PHYp(port));
1611 }
1612
1613 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1614                                      unsigned int mode,
1615                                      const struct phylink_link_state *state)
1616 {
1617         struct gswip_priv *priv = ds->priv;
1618         u32 miicfg = 0;
1619
1620         miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1621
1622         switch (state->interface) {
1623         case PHY_INTERFACE_MODE_MII:
1624         case PHY_INTERFACE_MODE_INTERNAL:
1625                 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1626                 break;
1627         case PHY_INTERFACE_MODE_REVMII:
1628                 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1629                 break;
1630         case PHY_INTERFACE_MODE_RMII:
1631                 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1632                 break;
1633         case PHY_INTERFACE_MODE_RGMII:
1634         case PHY_INTERFACE_MODE_RGMII_ID:
1635         case PHY_INTERFACE_MODE_RGMII_RXID:
1636         case PHY_INTERFACE_MODE_RGMII_TXID:
1637                 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1638                 break;
1639         default:
1640                 dev_err(ds->dev,
1641                         "Unsupported interface: %d\n", state->interface);
1642                 return;
1643         }
1644
1645         gswip_mii_mask_cfg(priv,
1646                            GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1647                            GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1648                            miicfg, port);
1649
1650         switch (state->interface) {
1651         case PHY_INTERFACE_MODE_RGMII_ID:
1652                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1653                                           GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1654                 break;
1655         case PHY_INTERFACE_MODE_RGMII_RXID:
1656                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1657                 break;
1658         case PHY_INTERFACE_MODE_RGMII_TXID:
1659                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1660                 break;
1661         default:
1662                 break;
1663         }
1664 }
1665
1666 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1667                                         unsigned int mode,
1668                                         phy_interface_t interface)
1669 {
1670         struct gswip_priv *priv = ds->priv;
1671
1672         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1673
1674         if (!dsa_is_cpu_port(ds, port))
1675                 gswip_port_set_link(priv, port, false);
1676 }
1677
1678 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1679                                       unsigned int mode,
1680                                       phy_interface_t interface,
1681                                       struct phy_device *phydev,
1682                                       int speed, int duplex,
1683                                       bool tx_pause, bool rx_pause)
1684 {
1685         struct gswip_priv *priv = ds->priv;
1686
1687         if (!dsa_is_cpu_port(ds, port)) {
1688                 gswip_port_set_link(priv, port, true);
1689                 gswip_port_set_speed(priv, port, speed, interface);
1690                 gswip_port_set_duplex(priv, port, duplex);
1691                 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1692         }
1693
1694         gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1695 }
1696
1697 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1698                               uint8_t *data)
1699 {
1700         int i;
1701
1702         if (stringset != ETH_SS_STATS)
1703                 return;
1704
1705         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1706                 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1707                         ETH_GSTRING_LEN);
1708 }
1709
1710 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1711                                     u32 index)
1712 {
1713         u32 result;
1714         int err;
1715
1716         gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1717         gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1718                                 GSWIP_BM_RAM_CTRL_OPMOD,
1719                               table | GSWIP_BM_RAM_CTRL_BAS,
1720                               GSWIP_BM_RAM_CTRL);
1721
1722         err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1723                                      GSWIP_BM_RAM_CTRL_BAS);
1724         if (err) {
1725                 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1726                         table, index);
1727                 return 0;
1728         }
1729
1730         result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1731         result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1732
1733         return result;
1734 }
1735
1736 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1737                                     uint64_t *data)
1738 {
1739         struct gswip_priv *priv = ds->priv;
1740         const struct gswip_rmon_cnt_desc *rmon_cnt;
1741         int i;
1742         u64 high;
1743
1744         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1745                 rmon_cnt = &gswip_rmon_cnt[i];
1746
1747                 data[i] = gswip_bcm_ram_entry_read(priv, port,
1748                                                    rmon_cnt->offset);
1749                 if (rmon_cnt->size == 2) {
1750                         high = gswip_bcm_ram_entry_read(priv, port,
1751                                                         rmon_cnt->offset + 1);
1752                         data[i] |= high << 32;
1753                 }
1754         }
1755 }
1756
1757 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1758 {
1759         if (sset != ETH_SS_STATS)
1760                 return 0;
1761
1762         return ARRAY_SIZE(gswip_rmon_cnt);
1763 }
1764
1765 static const struct dsa_switch_ops gswip_switch_ops = {
1766         .get_tag_protocol       = gswip_get_tag_protocol,
1767         .setup                  = gswip_setup,
1768         .port_enable            = gswip_port_enable,
1769         .port_disable           = gswip_port_disable,
1770         .port_bridge_join       = gswip_port_bridge_join,
1771         .port_bridge_leave      = gswip_port_bridge_leave,
1772         .port_fast_age          = gswip_port_fast_age,
1773         .port_vlan_filtering    = gswip_port_vlan_filtering,
1774         .port_vlan_prepare      = gswip_port_vlan_prepare,
1775         .port_vlan_add          = gswip_port_vlan_add,
1776         .port_vlan_del          = gswip_port_vlan_del,
1777         .port_stp_state_set     = gswip_port_stp_state_set,
1778         .port_fdb_add           = gswip_port_fdb_add,
1779         .port_fdb_del           = gswip_port_fdb_del,
1780         .port_fdb_dump          = gswip_port_fdb_dump,
1781         .phylink_validate       = gswip_phylink_validate,
1782         .phylink_mac_config     = gswip_phylink_mac_config,
1783         .phylink_mac_link_down  = gswip_phylink_mac_link_down,
1784         .phylink_mac_link_up    = gswip_phylink_mac_link_up,
1785         .get_strings            = gswip_get_strings,
1786         .get_ethtool_stats      = gswip_get_ethtool_stats,
1787         .get_sset_count         = gswip_get_sset_count,
1788 };
1789
1790 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1791         .fe_firmware_name = "/*(DEBLOBBED)*/",
1792         .ge_firmware_name = "/*(DEBLOBBED)*/",
1793 };
1794
1795 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1796         .fe_firmware_name = "/*(DEBLOBBED)*/",
1797         .ge_firmware_name = "/*(DEBLOBBED)*/",
1798 };
1799
1800 static const struct xway_gphy_match_data xrx300_gphy_data = {
1801         .fe_firmware_name = "/*(DEBLOBBED)*/",
1802         .ge_firmware_name = "/*(DEBLOBBED)*/",
1803 };
1804
1805 static const struct of_device_id xway_gphy_match[] = {
1806         { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1807         { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1808         { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1809         { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1810         { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1811         {},
1812 };
1813
1814 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1815 {
1816         struct device *dev = priv->dev;
1817         const struct firmware *fw;
1818         void *fw_addr;
1819         dma_addr_t dma_addr;
1820         dma_addr_t dev_addr;
1821         size_t size;
1822         int ret;
1823
1824         ret = clk_prepare_enable(gphy_fw->clk_gate);
1825         if (ret)
1826                 return ret;
1827
1828         reset_control_assert(gphy_fw->reset);
1829
1830         ret = reject_firmware(&fw, gphy_fw->fw_name, dev);
1831         if (ret) {
1832                 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1833                         gphy_fw->fw_name, ret);
1834                 return ret;
1835         }
1836
1837         /* GPHY cores need the firmware code in a persistent and contiguous
1838          * memory area with a 16 kB boundary aligned start address.
1839          */
1840         size = fw->size + XRX200_GPHY_FW_ALIGN;
1841
1842         fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1843         if (fw_addr) {
1844                 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1845                 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1846                 memcpy(fw_addr, fw->data, fw->size);
1847         } else {
1848                 dev_err(dev, "failed to alloc firmware memory\n");
1849                 release_firmware(fw);
1850                 return -ENOMEM;
1851         }
1852
1853         release_firmware(fw);
1854
1855         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1856         if (ret)
1857                 return ret;
1858
1859         reset_control_deassert(gphy_fw->reset);
1860
1861         return ret;
1862 }
1863
1864 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1865                                struct gswip_gphy_fw *gphy_fw,
1866                                struct device_node *gphy_fw_np, int i)
1867 {
1868         struct device *dev = priv->dev;
1869         u32 gphy_mode;
1870         int ret;
1871         char gphyname[10];
1872
1873         snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1874
1875         gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1876         if (IS_ERR(gphy_fw->clk_gate)) {
1877                 dev_err(dev, "Failed to lookup gate clock\n");
1878                 return PTR_ERR(gphy_fw->clk_gate);
1879         }
1880
1881         ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1882         if (ret)
1883                 return ret;
1884
1885         ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1886         /* Default to GE mode */
1887         if (ret)
1888                 gphy_mode = GPHY_MODE_GE;
1889
1890         switch (gphy_mode) {
1891         case GPHY_MODE_FE:
1892                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1893                 break;
1894         case GPHY_MODE_GE:
1895                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1896                 break;
1897         default:
1898                 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1899                 return -EINVAL;
1900         }
1901
1902         gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1903         if (IS_ERR(gphy_fw->reset)) {
1904                 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1905                         dev_err(dev, "Failed to lookup gphy reset\n");
1906                 return PTR_ERR(gphy_fw->reset);
1907         }
1908
1909         return gswip_gphy_fw_load(priv, gphy_fw);
1910 }
1911
1912 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1913                                  struct gswip_gphy_fw *gphy_fw)
1914 {
1915         int ret;
1916
1917         /* check if the device was fully probed */
1918         if (!gphy_fw->fw_name)
1919                 return;
1920
1921         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1922         if (ret)
1923                 dev_err(priv->dev, "can not reset GPHY FW pointer");
1924
1925         clk_disable_unprepare(gphy_fw->clk_gate);
1926
1927         reset_control_put(gphy_fw->reset);
1928 }
1929
1930 static int gswip_gphy_fw_list(struct gswip_priv *priv,
1931                               struct device_node *gphy_fw_list_np, u32 version)
1932 {
1933         struct device *dev = priv->dev;
1934         struct device_node *gphy_fw_np;
1935         const struct of_device_id *match;
1936         int err;
1937         int i = 0;
1938
1939         /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
1940          * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
1941          * needs a different GPHY firmware.
1942          */
1943         if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
1944                 switch (version) {
1945                 case GSWIP_VERSION_2_0:
1946                         priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
1947                         break;
1948                 case GSWIP_VERSION_2_1:
1949                         priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
1950                         break;
1951                 default:
1952                         dev_err(dev, "unknown GSWIP version: 0x%x", version);
1953                         return -ENOENT;
1954                 }
1955         }
1956
1957         match = of_match_node(xway_gphy_match, gphy_fw_list_np);
1958         if (match && match->data)
1959                 priv->gphy_fw_name_cfg = match->data;
1960
1961         if (!priv->gphy_fw_name_cfg) {
1962                 dev_err(dev, "GPHY compatible type not supported");
1963                 return -ENOENT;
1964         }
1965
1966         priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
1967         if (!priv->num_gphy_fw)
1968                 return -ENOENT;
1969
1970         priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
1971                                                            "lantiq,rcu");
1972         if (IS_ERR(priv->rcu_regmap))
1973                 return PTR_ERR(priv->rcu_regmap);
1974
1975         priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
1976                                            sizeof(*priv->gphy_fw),
1977                                            GFP_KERNEL | __GFP_ZERO);
1978         if (!priv->gphy_fw)
1979                 return -ENOMEM;
1980
1981         for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
1982                 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
1983                                           gphy_fw_np, i);
1984                 if (err) {
1985                         of_node_put(gphy_fw_np);
1986                         goto remove_gphy;
1987                 }
1988                 i++;
1989         }
1990
1991         /* The standalone PHY11G requires 300ms to be fully
1992          * initialized and ready for any MDIO communication after being
1993          * taken out of reset. For the SoC-internal GPHY variant there
1994          * is no (known) documentation for the minimum time after a
1995          * reset. Use the same value as for the standalone variant as
1996          * some users have reported internal PHYs not being detected
1997          * without any delay.
1998          */
1999         msleep(300);
2000
2001         return 0;
2002
2003 remove_gphy:
2004         for (i = 0; i < priv->num_gphy_fw; i++)
2005                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2006         return err;
2007 }
2008
2009 static int gswip_probe(struct platform_device *pdev)
2010 {
2011         struct gswip_priv *priv;
2012         struct device_node *mdio_np, *gphy_fw_np;
2013         struct device *dev = &pdev->dev;
2014         int err;
2015         int i;
2016         u32 version;
2017
2018         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2019         if (!priv)
2020                 return -ENOMEM;
2021
2022         priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2023         if (IS_ERR(priv->gswip))
2024                 return PTR_ERR(priv->gswip);
2025
2026         priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2027         if (IS_ERR(priv->mdio))
2028                 return PTR_ERR(priv->mdio);
2029
2030         priv->mii = devm_platform_ioremap_resource(pdev, 2);
2031         if (IS_ERR(priv->mii))
2032                 return PTR_ERR(priv->mii);
2033
2034         priv->hw_info = of_device_get_match_data(dev);
2035         if (!priv->hw_info)
2036                 return -EINVAL;
2037
2038         priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2039         if (!priv->ds)
2040                 return -ENOMEM;
2041
2042         priv->ds->dev = dev;
2043         priv->ds->num_ports = priv->hw_info->max_ports;
2044         priv->ds->priv = priv;
2045         priv->ds->ops = &gswip_switch_ops;
2046         priv->dev = dev;
2047         version = gswip_switch_r(priv, GSWIP_VERSION);
2048
2049         /* bring up the mdio bus */
2050         gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2051         if (gphy_fw_np) {
2052                 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2053                 of_node_put(gphy_fw_np);
2054                 if (err) {
2055                         dev_err(dev, "gphy fw probe failed\n");
2056                         return err;
2057                 }
2058         }
2059
2060         /* bring up the mdio bus */
2061         mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
2062         if (mdio_np) {
2063                 err = gswip_mdio(priv, mdio_np);
2064                 if (err) {
2065                         dev_err(dev, "mdio probe failed\n");
2066                         goto put_mdio_node;
2067                 }
2068         }
2069
2070         err = dsa_register_switch(priv->ds);
2071         if (err) {
2072                 dev_err(dev, "dsa switch register failed: %i\n", err);
2073                 goto mdio_bus;
2074         }
2075         if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2076                 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
2077                         priv->hw_info->cpu_port);
2078                 err = -EINVAL;
2079                 goto disable_switch;
2080         }
2081
2082         platform_set_drvdata(pdev, priv);
2083
2084         dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2085                  (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2086                  (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2087         return 0;
2088
2089 disable_switch:
2090         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2091         dsa_unregister_switch(priv->ds);
2092 mdio_bus:
2093         if (mdio_np) {
2094                 mdiobus_unregister(priv->ds->slave_mii_bus);
2095                 mdiobus_free(priv->ds->slave_mii_bus);
2096         }
2097 put_mdio_node:
2098         of_node_put(mdio_np);
2099         for (i = 0; i < priv->num_gphy_fw; i++)
2100                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2101         return err;
2102 }
2103
2104 static int gswip_remove(struct platform_device *pdev)
2105 {
2106         struct gswip_priv *priv = platform_get_drvdata(pdev);
2107         int i;
2108
2109         /* disable the switch */
2110         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2111
2112         dsa_unregister_switch(priv->ds);
2113
2114         if (priv->ds->slave_mii_bus) {
2115                 mdiobus_unregister(priv->ds->slave_mii_bus);
2116                 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
2117                 mdiobus_free(priv->ds->slave_mii_bus);
2118         }
2119
2120         for (i = 0; i < priv->num_gphy_fw; i++)
2121                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2122
2123         return 0;
2124 }
2125
2126 static const struct gswip_hw_info gswip_xrx200 = {
2127         .max_ports = 7,
2128         .cpu_port = 6,
2129 };
2130
2131 static const struct of_device_id gswip_of_match[] = {
2132         { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2133         {},
2134 };
2135 MODULE_DEVICE_TABLE(of, gswip_of_match);
2136
2137 static struct platform_driver gswip_driver = {
2138         .probe = gswip_probe,
2139         .remove = gswip_remove,
2140         .driver = {
2141                 .name = "gswip",
2142                 .of_match_table = gswip_of_match,
2143         },
2144 };
2145
2146 module_platform_driver(gswip_driver);
2147
2148 /*(DEBLOBBED)*/
2149 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2150 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2151 MODULE_LICENSE("GPL v2");