drivers/net/dsa/lantiq_gswip.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
   4  *
   5  * Copyright (C) 2010 Lantiq Deutschland
   6  * Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
   8  *
   9  * The VLAN and bridge model the GSWIP hardware uses does not directly
  10  * matches the model DSA uses.
  11  *
  12  * The hardware has 64 possible table entries for bridges with one VLAN
  13  * ID, one flow id and a list of ports for each bridge. All entries which
  14  * match the same flow ID are combined in the mac learning table, they
  15  * act as one global bridge.
  16  * The hardware does not support VLAN filter on the port, but on the
  17  * bridge, this driver converts the DSA model to the hardware.
  18  *
  19  * The CPU gets all the exception frames which do not match any forwarding
  20  * rule and the CPU port is also added to all bridges. This makes it possible
  21  * to handle all the special cases easily in software.
  22  * At the initialization the driver allocates one bridge table entry for
  23  * each switch port which is used when the port is used without an
  24  * explicit bridge. This prevents the frames from being forwarded
  25  * between all LAN ports by default.
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/firmware.h>
  32 #include <linux/if_bridge.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/iopoll.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/module.h>
  37 #include <linux/of_mdio.h>
  38 #include <linux/of_net.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/phy.h>
  41 #include <linux/phylink.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/regmap.h>
  44 #include <linux/reset.h>
  45 #include <net/dsa.h>
  46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
  47
  48 #include "lantiq_pce.h"
  49
  50 /* GSWIP MDIO Registers */
  51 #define GSWIP_MDIO_GLOB                 0x00
  52 #define  GSWIP_MDIO_GLOB_ENABLE         BIT(15)
  53 #define GSWIP_MDIO_CTRL                 0x08
  54 #define  GSWIP_MDIO_CTRL_BUSY           BIT(12)
  55 #define  GSWIP_MDIO_CTRL_RD             BIT(11)
  56 #define  GSWIP_MDIO_CTRL_WR             BIT(10)
  57 #define  GSWIP_MDIO_CTRL_PHYAD_MASK     0x1f
  58 #define  GSWIP_MDIO_CTRL_PHYAD_SHIFT    5
  59 #define  GSWIP_MDIO_CTRL_REGAD_MASK     0x1f
  60 #define GSWIP_MDIO_READ                 0x09
  61 #define GSWIP_MDIO_WRITE                0x0A
  62 #define GSWIP_MDIO_MDC_CFG0             0x0B
  63 #define GSWIP_MDIO_MDC_CFG1             0x0C
  64 #define GSWIP_MDIO_PHYp(p)              (0x15 - (p))
  65 #define  GSWIP_MDIO_PHY_LINK_MASK       0x6000
  66 #define  GSWIP_MDIO_PHY_LINK_AUTO       0x0000
  67 #define  GSWIP_MDIO_PHY_LINK_DOWN       0x4000
  68 #define  GSWIP_MDIO_PHY_LINK_UP         0x2000
  69 #define  GSWIP_MDIO_PHY_SPEED_MASK      0x1800
  70 #define  GSWIP_MDIO_PHY_SPEED_AUTO      0x1800
  71 #define  GSWIP_MDIO_PHY_SPEED_M10       0x0000
  72 #define  GSWIP_MDIO_PHY_SPEED_M100      0x0800
  73 #define  GSWIP_MDIO_PHY_SPEED_G1        0x1000
  74 #define  GSWIP_MDIO_PHY_FDUP_MASK       0x0600
  75 #define  GSWIP_MDIO_PHY_FDUP_AUTO       0x0000
  76 #define  GSWIP_MDIO_PHY_FDUP_EN         0x0200
  77 #define  GSWIP_MDIO_PHY_FDUP_DIS        0x0600
  78 #define  GSWIP_MDIO_PHY_FCONTX_MASK     0x0180
  79 #define  GSWIP_MDIO_PHY_FCONTX_AUTO     0x0000
  80 #define  GSWIP_MDIO_PHY_FCONTX_EN       0x0100
  81 #define  GSWIP_MDIO_PHY_FCONTX_DIS      0x0180
  82 #define  GSWIP_MDIO_PHY_FCONRX_MASK     0x0060
  83 #define  GSWIP_MDIO_PHY_FCONRX_AUTO     0x0000
  84 #define  GSWIP_MDIO_PHY_FCONRX_EN       0x0020
  85 #define  GSWIP_MDIO_PHY_FCONRX_DIS      0x0060
  86 #define  GSWIP_MDIO_PHY_ADDR_MASK       0x001f
  87 #define  GSWIP_MDIO_PHY_MASK            (GSWIP_MDIO_PHY_ADDR_MASK | \
  88                                          GSWIP_MDIO_PHY_FCONRX_MASK | \
  89                                          GSWIP_MDIO_PHY_FCONTX_MASK | \
  90                                          GSWIP_MDIO_PHY_LINK_MASK | \
  91                                          GSWIP_MDIO_PHY_SPEED_MASK | \
  92                                          GSWIP_MDIO_PHY_FDUP_MASK)
  93
  94 /* GSWIP MII Registers */
  95 #define GSWIP_MII_CFGp(p)               (0x2 * (p))
  96 #define  GSWIP_MII_CFG_RESET            BIT(15)
  97 #define  GSWIP_MII_CFG_EN               BIT(14)
  98 #define  GSWIP_MII_CFG_ISOLATE          BIT(13)
  99 #define  GSWIP_MII_CFG_LDCLKDIS         BIT(12)
 100 #define  GSWIP_MII_CFG_RGMII_IBS        BIT(8)
 101 #define  GSWIP_MII_CFG_RMII_CLK         BIT(7)
 102 #define  GSWIP_MII_CFG_MODE_MIIP        0x0
 103 #define  GSWIP_MII_CFG_MODE_MIIM        0x1
 104 #define  GSWIP_MII_CFG_MODE_RMIIP       0x2
 105 #define  GSWIP_MII_CFG_MODE_RMIIM       0x3
 106 #define  GSWIP_MII_CFG_MODE_RGMII       0x4
 107 #define  GSWIP_MII_CFG_MODE_GMII        0x9
 108 #define  GSWIP_MII_CFG_MODE_MASK        0xf
 109 #define  GSWIP_MII_CFG_RATE_M2P5        0x00
 110 #define  GSWIP_MII_CFG_RATE_M25 0x10
 111 #define  GSWIP_MII_CFG_RATE_M125        0x20
 112 #define  GSWIP_MII_CFG_RATE_M50 0x30
 113 #define  GSWIP_MII_CFG_RATE_AUTO        0x40
 114 #define  GSWIP_MII_CFG_RATE_MASK        0x70
 115 #define GSWIP_MII_PCDU0                 0x01
 116 #define GSWIP_MII_PCDU1                 0x03
 117 #define GSWIP_MII_PCDU5                 0x05
 118 #define  GSWIP_MII_PCDU_TXDLY_MASK      GENMASK(2, 0)
 119 #define  GSWIP_MII_PCDU_RXDLY_MASK      GENMASK(9, 7)
 120
 121 /* GSWIP Core Registers */
 122 #define GSWIP_SWRES                     0x000
 123 #define  GSWIP_SWRES_R1                 BIT(1)  /* GSWIP Software reset */
 124 #define  GSWIP_SWRES_R0                 BIT(0)  /* GSWIP Hardware reset */
 125 #define GSWIP_VERSION                   0x013
 126 #define  GSWIP_VERSION_REV_SHIFT        0
 127 #define  GSWIP_VERSION_REV_MASK         GENMASK(7, 0)
 128 #define  GSWIP_VERSION_MOD_SHIFT        8
 129 #define  GSWIP_VERSION_MOD_MASK         GENMASK(15, 8)
 130 #define   GSWIP_VERSION_2_0             0x100
 131 #define   GSWIP_VERSION_2_1             0x021
 132 #define   GSWIP_VERSION_2_2             0x122
 133 #define   GSWIP_VERSION_2_2_ETC         0x022
 134
 135 #define GSWIP_BM_RAM_VAL(x)             (0x043 - (x))
 136 #define GSWIP_BM_RAM_ADDR               0x044
 137 #define GSWIP_BM_RAM_CTRL               0x045
 138 #define  GSWIP_BM_RAM_CTRL_BAS          BIT(15)
 139 #define  GSWIP_BM_RAM_CTRL_OPMOD        BIT(5)
 140 #define  GSWIP_BM_RAM_CTRL_ADDR_MASK    GENMASK(4, 0)
 141 #define GSWIP_BM_QUEUE_GCTRL            0x04A
 142 #define  GSWIP_BM_QUEUE_GCTRL_GL_MOD    BIT(10)
 143 /* buffer management Port Configuration Register */
 144 #define GSWIP_BM_PCFGp(p)               (0x080 + ((p) * 2))
 145 #define  GSWIP_BM_PCFG_CNTEN            BIT(0)  /* RMON Counter Enable */
 146 #define  GSWIP_BM_PCFG_IGCNT            BIT(1)  /* Ingres Special Tag RMON count */
 147 /* buffer management Port Control Register */
 148 #define GSWIP_BM_RMON_CTRLp(p)          (0x81 + ((p) * 2))
 149 #define  GSWIP_BM_CTRL_RMON_RAM1_RES    BIT(0)  /* Software Reset for RMON RAM 1 */
 150 #define  GSWIP_BM_CTRL_RMON_RAM2_RES    BIT(1)  /* Software Reset for RMON RAM 2 */
 151
 152 /* PCE */
 153 #define GSWIP_PCE_TBL_KEY(x)            (0x447 - (x))
 154 #define GSWIP_PCE_TBL_MASK              0x448
 155 #define GSWIP_PCE_TBL_VAL(x)            (0x44D - (x))
 156 #define GSWIP_PCE_TBL_ADDR              0x44E
 157 #define GSWIP_PCE_TBL_CTRL              0x44F
 158 #define  GSWIP_PCE_TBL_CTRL_BAS         BIT(15)
 159 #define  GSWIP_PCE_TBL_CTRL_TYPE        BIT(13)
 160 #define  GSWIP_PCE_TBL_CTRL_VLD         BIT(12)
 161 #define  GSWIP_PCE_TBL_CTRL_KEYFORM     BIT(11)
 162 #define  GSWIP_PCE_TBL_CTRL_GMAP_MASK   GENMASK(10, 7)
 163 #define  GSWIP_PCE_TBL_CTRL_OPMOD_MASK  GENMASK(6, 5)
 164 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADRD  0x00
 165 #define  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR  0x20
 166 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSRD  0x40
 167 #define  GSWIP_PCE_TBL_CTRL_OPMOD_KSWR  0x60
 168 #define  GSWIP_PCE_TBL_CTRL_ADDR_MASK   GENMASK(4, 0)
 169 #define GSWIP_PCE_PMAP1                 0x453   /* Monitoring port map */
 170 #define GSWIP_PCE_PMAP2                 0x454   /* Default Multicast port map */
 171 #define GSWIP_PCE_PMAP3                 0x455   /* Default Unknown Unicast port map */
 172 #define GSWIP_PCE_GCTRL_0               0x456
 173 #define  GSWIP_PCE_GCTRL_0_MTFL         BIT(0)  /* MAC Table Flushing */
 174 #define  GSWIP_PCE_GCTRL_0_MC_VALID     BIT(3)
 175 #define  GSWIP_PCE_GCTRL_0_VLAN         BIT(14) /* VLAN aware Switching */
 176 #define GSWIP_PCE_GCTRL_1               0x457
 177 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK    BIT(2)  /* MAC Address table lock */
 178 #define  GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD        BIT(3) /* Mac address table lock forwarding mode */
 179 #define GSWIP_PCE_PCTRL_0p(p)           (0x480 + ((p) * 0xA))
 180 #define  GSWIP_PCE_PCTRL_0_TVM          BIT(5)  /* Transparent VLAN mode */
 181 #define  GSWIP_PCE_PCTRL_0_VREP         BIT(6)  /* VLAN Replace Mode */
 182 #define  GSWIP_PCE_PCTRL_0_INGRESS      BIT(11) /* Accept special tag in ingress */
 183 #define  GSWIP_PCE_PCTRL_0_PSTATE_LISTEN        0x0
 184 #define  GSWIP_PCE_PCTRL_0_PSTATE_RX            0x1
 185 #define  GSWIP_PCE_PCTRL_0_PSTATE_TX            0x2
 186 #define  GSWIP_PCE_PCTRL_0_PSTATE_LEARNING      0x3
 187 #define  GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING    0x7
 188 #define  GSWIP_PCE_PCTRL_0_PSTATE_MASK  GENMASK(2, 0)
 189 #define GSWIP_PCE_VCTRL(p)              (0x485 + ((p) * 0xA))
 190 #define  GSWIP_PCE_VCTRL_UVR            BIT(0)  /* Unknown VLAN Rule */
 191 #define  GSWIP_PCE_VCTRL_VIMR           BIT(3)  /* VLAN Ingress Member violation rule */
 192 #define  GSWIP_PCE_VCTRL_VEMR           BIT(4)  /* VLAN Egress Member violation rule */
 193 #define  GSWIP_PCE_VCTRL_VSR            BIT(5)  /* VLAN Security */
 194 #define  GSWIP_PCE_VCTRL_VID0           BIT(6)  /* Priority Tagged Rule */
 195 #define GSWIP_PCE_DEFPVID(p)            (0x486 + ((p) * 0xA))
 196
 197 #define GSWIP_MAC_FLEN                  0x8C5
 198 #define GSWIP_MAC_CTRL_0p(p)            (0x903 + ((p) * 0xC))
 199 #define  GSWIP_MAC_CTRL_0_PADEN         BIT(8)
 200 #define  GSWIP_MAC_CTRL_0_FCS_EN        BIT(7)
 201 #define  GSWIP_MAC_CTRL_0_FCON_MASK     0x0070
 202 #define  GSWIP_MAC_CTRL_0_FCON_AUTO     0x0000
 203 #define  GSWIP_MAC_CTRL_0_FCON_RX       0x0010
 204 #define  GSWIP_MAC_CTRL_0_FCON_TX       0x0020
 205 #define  GSWIP_MAC_CTRL_0_FCON_RXTX     0x0030
 206 #define  GSWIP_MAC_CTRL_0_FCON_NONE     0x0040
 207 #define  GSWIP_MAC_CTRL_0_FDUP_MASK     0x000C
 208 #define  GSWIP_MAC_CTRL_0_FDUP_AUTO     0x0000
 209 #define  GSWIP_MAC_CTRL_0_FDUP_EN       0x0004
 210 #define  GSWIP_MAC_CTRL_0_FDUP_DIS      0x000C
 211 #define  GSWIP_MAC_CTRL_0_GMII_MASK     0x0003
 212 #define  GSWIP_MAC_CTRL_0_GMII_AUTO     0x0000
 213 #define  GSWIP_MAC_CTRL_0_GMII_MII      0x0001
 214 #define  GSWIP_MAC_CTRL_0_GMII_RGMII    0x0002
 215 #define GSWIP_MAC_CTRL_2p(p)            (0x905 + ((p) * 0xC))
 216 #define GSWIP_MAC_CTRL_2_MLEN           BIT(3) /* Maximum Untagged Frame Lnegth */
 217
 218 /* Ethernet Switch Fetch DMA Port Control Register */
 219 #define GSWIP_FDMA_PCTRLp(p)            (0xA80 + ((p) * 0x6))
 220 #define  GSWIP_FDMA_PCTRL_EN            BIT(0)  /* FDMA Port Enable */
 221 #define  GSWIP_FDMA_PCTRL_STEN          BIT(1)  /* Special Tag Insertion Enable */
 222 #define  GSWIP_FDMA_PCTRL_VLANMOD_MASK  GENMASK(4, 3)   /* VLAN Modification Control */
 223 #define  GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3       /* VLAN Modification Control */
 224 #define  GSWIP_FDMA_PCTRL_VLANMOD_DIS   (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 225 #define  GSWIP_FDMA_PCTRL_VLANMOD_PRIO  (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 226 #define  GSWIP_FDMA_PCTRL_VLANMOD_ID    (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 227 #define  GSWIP_FDMA_PCTRL_VLANMOD_BOTH  (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
 228
 229 /* Ethernet Switch Store DMA Port Control Register */
 230 #define GSWIP_SDMA_PCTRLp(p)            (0xBC0 + ((p) * 0x6))
 231 #define  GSWIP_SDMA_PCTRL_EN            BIT(0)  /* SDMA Port Enable */
 232 #define  GSWIP_SDMA_PCTRL_FCEN          BIT(1)  /* Flow Control Enable */
 233 #define  GSWIP_SDMA_PCTRL_PAUFWD        BIT(3)  /* Pause Frame Forwarding */
 234
 235 #define GSWIP_TABLE_ACTIVE_VLAN         0x01
 236 #define GSWIP_TABLE_VLAN_MAPPING        0x02
 237 #define GSWIP_TABLE_MAC_BRIDGE          0x0b
 238 #define  GSWIP_TABLE_MAC_BRIDGE_STATIC  0x01    /* Static not, aging entry */
 239
 240 #define XRX200_GPHY_FW_ALIGN    (16 * 1024)
 241
 242 struct gswip_hw_info {
 243         int max_ports;
 244         int cpu_port;
 245         const struct dsa_switch_ops *ops;
 246 };
 247
 248 struct xway_gphy_match_data {
 249         char *fe_firmware_name;
 250         char *ge_firmware_name;
 251 };
 252
 253 struct gswip_gphy_fw {
 254         struct clk *clk_gate;
 255         struct reset_control *reset;
 256         u32 fw_addr_offset;
 257         char *fw_name;
 258 };
 259
 260 struct gswip_vlan {
 261         struct net_device *bridge;
 262         u16 vid;
 263         u8 fid;
 264 };
 265
 266 struct gswip_priv {
 267         __iomem void *gswip;
 268         __iomem void *mdio;
 269         __iomem void *mii;
 270         const struct gswip_hw_info *hw_info;
 271         const struct xway_gphy_match_data *gphy_fw_name_cfg;
 272         struct dsa_switch *ds;
 273         struct device *dev;
 274         struct regmap *rcu_regmap;
 275         struct gswip_vlan vlans[64];
 276         int num_gphy_fw;
 277         struct gswip_gphy_fw *gphy_fw;
 278         u32 port_vlan_filter;
 279 };
 280
 281 struct gswip_pce_table_entry {
 282         u16 index;      // PCE_TBL_ADDR.ADDR = pData->table_index
 283         u16 table;      // PCE_TBL_CTRL.ADDR = pData->table
 284         u16 key[8];
 285         u16 val[5];
 286         u16 mask;
 287         u8 gmap;
 288         bool type;
 289         bool valid;
 290         bool key_mode;
 291 };
 292
 293 struct gswip_rmon_cnt_desc {
 294         unsigned int size;
 295         unsigned int offset;
 296         const char *name;
 297 };
 298
 299 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
 300
 301 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
 302         /** Receive Packet Count (only packets that are accepted and not discarded). */
 303         MIB_DESC(1, 0x1F, "RxGoodPkts"),
 304         MIB_DESC(1, 0x23, "RxUnicastPkts"),
 305         MIB_DESC(1, 0x22, "RxMulticastPkts"),
 306         MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
 307         MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
 308         MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
 309         MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
 310         MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
 311         MIB_DESC(1, 0x20, "RxGoodPausePkts"),
 312         MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
 313         MIB_DESC(1, 0x12, "Rx64BytePkts"),
 314         MIB_DESC(1, 0x13, "Rx127BytePkts"),
 315         MIB_DESC(1, 0x14, "Rx255BytePkts"),
 316         MIB_DESC(1, 0x15, "Rx511BytePkts"),
 317         MIB_DESC(1, 0x16, "Rx1023BytePkts"),
 318         /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
 319         MIB_DESC(1, 0x17, "RxMaxBytePkts"),
 320         MIB_DESC(1, 0x18, "RxDroppedPkts"),
 321         MIB_DESC(1, 0x19, "RxFilteredPkts"),
 322         MIB_DESC(2, 0x24, "RxGoodBytes"),
 323         MIB_DESC(2, 0x26, "RxBadBytes"),
 324         MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
 325         MIB_DESC(1, 0x0C, "TxGoodPkts"),
 326         MIB_DESC(1, 0x06, "TxUnicastPkts"),
 327         MIB_DESC(1, 0x07, "TxMulticastPkts"),
 328         MIB_DESC(1, 0x00, "Tx64BytePkts"),
 329         MIB_DESC(1, 0x01, "Tx127BytePkts"),
 330         MIB_DESC(1, 0x02, "Tx255BytePkts"),
 331         MIB_DESC(1, 0x03, "Tx511BytePkts"),
 332         MIB_DESC(1, 0x04, "Tx1023BytePkts"),
 333         /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
 334         MIB_DESC(1, 0x05, "TxMaxBytePkts"),
 335         MIB_DESC(1, 0x08, "TxSingleCollCount"),
 336         MIB_DESC(1, 0x09, "TxMultCollCount"),
 337         MIB_DESC(1, 0x0A, "TxLateCollCount"),
 338         MIB_DESC(1, 0x0B, "TxExcessCollCount"),
 339         MIB_DESC(1, 0x0D, "TxPauseCount"),
 340         MIB_DESC(1, 0x10, "TxDroppedPkts"),
 341         MIB_DESC(2, 0x0E, "TxGoodBytes"),
 342 };
 343
 344 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
 345 {
 346         return __raw_readl(priv->gswip + (offset * 4));
 347 }
 348
 349 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
 350 {
 351         __raw_writel(val, priv->gswip + (offset * 4));
 352 }
 353
 354 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
 355                               u32 offset)
 356 {
 357         u32 val = gswip_switch_r(priv, offset);
 358
 359         val &= ~(clear);
 360         val |= set;
 361         gswip_switch_w(priv, val, offset);
 362 }
 363
 364 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
 365                                   u32 cleared)
 366 {
 367         u32 val;
 368
 369         return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
 370                                   (val & cleared) == 0, 20, 50000);
 371 }
 372
 373 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
 374 {
 375         return __raw_readl(priv->mdio + (offset * 4));
 376 }
 377
 378 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
 379 {
 380         __raw_writel(val, priv->mdio + (offset * 4));
 381 }
 382
 383 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
 384                             u32 offset)
 385 {
 386         u32 val = gswip_mdio_r(priv, offset);
 387
 388         val &= ~(clear);
 389         val |= set;
 390         gswip_mdio_w(priv, val, offset);
 391 }
 392
 393 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
 394 {
 395         return __raw_readl(priv->mii + (offset * 4));
 396 }
 397
 398 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
 399 {
 400         __raw_writel(val, priv->mii + (offset * 4));
 401 }
 402
 403 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
 404                            u32 offset)
 405 {
 406         u32 val = gswip_mii_r(priv, offset);
 407
 408         val &= ~(clear);
 409         val |= set;
 410         gswip_mii_w(priv, val, offset);
 411 }
 412
 413 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
 414                                int port)
 415 {
 416         /* There's no MII_CFG register for the CPU port */
 417         if (!dsa_is_cpu_port(priv->ds, port))
 418                 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
 419 }
 420
 421 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
 422                                 int port)
 423 {
 424         switch (port) {
 425         case 0:
 426                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
 427                 break;
 428         case 1:
 429                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
 430                 break;
 431         case 5:
 432                 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
 433                 break;
 434         }
 435 }
 436
 437 static int gswip_mdio_poll(struct gswip_priv *priv)
 438 {
 439         int cnt = 100;
 440
 441         while (likely(cnt--)) {
 442                 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
 443
 444                 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
 445                         return 0;
 446                 usleep_range(20, 40);
 447         }
 448
 449         return -ETIMEDOUT;
 450 }
 451
 452 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
 453 {
 454         struct gswip_priv *priv = bus->priv;
 455         int err;
 456
 457         err = gswip_mdio_poll(priv);
 458         if (err) {
 459                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 460                 return err;
 461         }
 462
 463         gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
 464         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
 465                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 466                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 467                 GSWIP_MDIO_CTRL);
 468
 469         return 0;
 470 }
 471
 472 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
 473 {
 474         struct gswip_priv *priv = bus->priv;
 475         int err;
 476
 477         err = gswip_mdio_poll(priv);
 478         if (err) {
 479                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 480                 return err;
 481         }
 482
 483         gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
 484                 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
 485                 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
 486                 GSWIP_MDIO_CTRL);
 487
 488         err = gswip_mdio_poll(priv);
 489         if (err) {
 490                 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
 491                 return err;
 492         }
 493
 494         return gswip_mdio_r(priv, GSWIP_MDIO_READ);
 495 }
 496
 497 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
 498 {
 499         struct dsa_switch *ds = priv->ds;
 500         int err;
 501
 502         ds->slave_mii_bus = mdiobus_alloc();
 503         if (!ds->slave_mii_bus)
 504                 return -ENOMEM;
 505
 506         ds->slave_mii_bus->priv = priv;
 507         ds->slave_mii_bus->read = gswip_mdio_rd;
 508         ds->slave_mii_bus->write = gswip_mdio_wr;
 509         ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
 510         snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
 511                  dev_name(priv->dev));
 512         ds->slave_mii_bus->parent = priv->dev;
 513         ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
 514
 515         err = of_mdiobus_register(ds->slave_mii_bus, mdio_np);
 516         if (err)
 517                 mdiobus_free(ds->slave_mii_bus);
 518
 519         return err;
 520 }
 521
 522 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
 523                                       struct gswip_pce_table_entry *tbl)
 524 {
 525         int i;
 526         int err;
 527         u16 crtl;
 528         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
 529                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
 530
 531         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 532                                      GSWIP_PCE_TBL_CTRL_BAS);
 533         if (err)
 534                 return err;
 535
 536         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 537         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 538                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 539                           tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
 540                           GSWIP_PCE_TBL_CTRL);
 541
 542         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 543                                      GSWIP_PCE_TBL_CTRL_BAS);
 544         if (err)
 545                 return err;
 546
 547         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 548                 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
 549
 550         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 551                 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
 552
 553         tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
 554
 555         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 556
 557         tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
 558         tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
 559         tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
 560
 561         return 0;
 562 }
 563
 564 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
 565                                        struct gswip_pce_table_entry *tbl)
 566 {
 567         int i;
 568         int err;
 569         u16 crtl;
 570         u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
 571                                         GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
 572
 573         err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 574                                      GSWIP_PCE_TBL_CTRL_BAS);
 575         if (err)
 576                 return err;
 577
 578         gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
 579         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 580                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 581                           tbl->table | addr_mode,
 582                           GSWIP_PCE_TBL_CTRL);
 583
 584         for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
 585                 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
 586
 587         for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
 588                 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
 589
 590         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 591                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 592                           tbl->table | addr_mode,
 593                           GSWIP_PCE_TBL_CTRL);
 594
 595         gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
 596
 597         crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
 598         crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
 599                   GSWIP_PCE_TBL_CTRL_GMAP_MASK);
 600         if (tbl->type)
 601                 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
 602         if (tbl->valid)
 603                 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
 604         crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
 605         crtl |= GSWIP_PCE_TBL_CTRL_BAS;
 606         gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
 607
 608         return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 609                                       GSWIP_PCE_TBL_CTRL_BAS);
 610 }
 611
 612 /* Add the LAN port into a bridge with the CPU port by
 613  * default. This prevents automatic forwarding of
 614  * packages between the LAN ports when no explicit
 615  * bridge is configured.
 616  */
 617 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
 618 {
 619         struct gswip_pce_table_entry vlan_active = {0,};
 620         struct gswip_pce_table_entry vlan_mapping = {0,};
 621         unsigned int cpu_port = priv->hw_info->cpu_port;
 622         unsigned int max_ports = priv->hw_info->max_ports;
 623         int err;
 624
 625         if (port >= max_ports) {
 626                 dev_err(priv->dev, "single port for %i supported\n", port);
 627                 return -EIO;
 628         }
 629
 630         vlan_active.index = port + 1;
 631         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 632         vlan_active.key[0] = 0; /* vid */
 633         vlan_active.val[0] = port + 1 /* fid */;
 634         vlan_active.valid = add;
 635         err = gswip_pce_table_entry_write(priv, &vlan_active);
 636         if (err) {
 637                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 638                 return err;
 639         }
 640
 641         if (!add)
 642                 return 0;
 643
 644         vlan_mapping.index = port + 1;
 645         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 646         vlan_mapping.val[0] = 0 /* vid */;
 647         vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
 648         vlan_mapping.val[2] = 0;
 649         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 650         if (err) {
 651                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 652                 return err;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static int gswip_port_enable(struct dsa_switch *ds, int port,
 659                              struct phy_device *phydev)
 660 {
 661         struct gswip_priv *priv = ds->priv;
 662         int err;
 663
 664         if (!dsa_is_user_port(ds, port))
 665                 return 0;
 666
 667         if (!dsa_is_cpu_port(ds, port)) {
 668                 err = gswip_add_single_port_br(priv, port, true);
 669                 if (err)
 670                         return err;
 671         }
 672
 673         /* RMON Counter Enable for port */
 674         gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
 675
 676         /* enable port fetch/store dma & VLAN Modification */
 677         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
 678                                    GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
 679                          GSWIP_FDMA_PCTRLp(port));
 680         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
 681                           GSWIP_SDMA_PCTRLp(port));
 682
 683         if (!dsa_is_cpu_port(ds, port)) {
 684                 u32 mdio_phy = 0;
 685
 686                 if (phydev)
 687                         mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
 688
 689                 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
 690                                 GSWIP_MDIO_PHYp(port));
 691         }
 692
 693         return 0;
 694 }
 695
 696 static void gswip_port_disable(struct dsa_switch *ds, int port)
 697 {
 698         struct gswip_priv *priv = ds->priv;
 699
 700         if (!dsa_is_user_port(ds, port))
 701                 return;
 702
 703         gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
 704                           GSWIP_FDMA_PCTRLp(port));
 705         gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
 706                           GSWIP_SDMA_PCTRLp(port));
 707 }
 708
 709 static int gswip_pce_load_microcode(struct gswip_priv *priv)
 710 {
 711         int i;
 712         int err;
 713
 714         gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
 715                                 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
 716                           GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
 717         gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
 718
 719         for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
 720                 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
 721                 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
 722                                GSWIP_PCE_TBL_VAL(0));
 723                 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
 724                                GSWIP_PCE_TBL_VAL(1));
 725                 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
 726                                GSWIP_PCE_TBL_VAL(2));
 727                 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
 728                                GSWIP_PCE_TBL_VAL(3));
 729
 730                 /* start the table access: */
 731                 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
 732                                   GSWIP_PCE_TBL_CTRL);
 733                 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
 734                                              GSWIP_PCE_TBL_CTRL_BAS);
 735                 if (err)
 736                         return err;
 737         }
 738
 739         /* tell the switch that the microcode is loaded */
 740         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
 741                           GSWIP_PCE_GCTRL_0);
 742
 743         return 0;
 744 }
 745
 746 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
 747                                      bool vlan_filtering,
 748                                      struct netlink_ext_ack *extack)
 749 {
 750         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
 751         struct gswip_priv *priv = ds->priv;
 752
 753         /* Do not allow changing the VLAN filtering options while in bridge */
 754         if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) {
 755                 NL_SET_ERR_MSG_MOD(extack,
 756                                    "Dynamic toggling of vlan_filtering not supported");
 757                 return -EIO;
 758         }
 759
 760         if (vlan_filtering) {
 761                 /* Use port based VLAN tag */
 762                 gswip_switch_mask(priv,
 763                                   GSWIP_PCE_VCTRL_VSR,
 764                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 765                                   GSWIP_PCE_VCTRL_VEMR,
 766                                   GSWIP_PCE_VCTRL(port));
 767                 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
 768                                   GSWIP_PCE_PCTRL_0p(port));
 769         } else {
 770                 /* Use port based VLAN tag */
 771                 gswip_switch_mask(priv,
 772                                   GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
 773                                   GSWIP_PCE_VCTRL_VEMR,
 774                                   GSWIP_PCE_VCTRL_VSR,
 775                                   GSWIP_PCE_VCTRL(port));
 776                 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
 777                                   GSWIP_PCE_PCTRL_0p(port));
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int gswip_setup(struct dsa_switch *ds)
 784 {
 785         struct gswip_priv *priv = ds->priv;
 786         unsigned int cpu_port = priv->hw_info->cpu_port;
 787         int i;
 788         int err;
 789
 790         gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
 791         usleep_range(5000, 10000);
 792         gswip_switch_w(priv, 0, GSWIP_SWRES);
 793
 794         /* disable port fetch/store dma on all ports */
 795         for (i = 0; i < priv->hw_info->max_ports; i++) {
 796                 gswip_port_disable(ds, i);
 797                 gswip_port_vlan_filtering(ds, i, false, NULL);
 798         }
 799
 800         /* enable Switch */
 801         gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
 802
 803         err = gswip_pce_load_microcode(priv);
 804         if (err) {
 805                 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
 806                 return err;
 807         }
 808
 809         /* Default unknown Broadcast/Multicast/Unicast port maps */
 810         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
 811         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
 812         gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
 813
 814         /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
 815          * interoperability problem with this auto polling mechanism because
 816          * their status registers think that the link is in a different state
 817          * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
 818          * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
 819          * auto polling state machine consider the link being negotiated with
 820          * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
 821          * to the switch port being completely dead (RX and TX are both not
 822          * working).
 823          * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
 824          * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
 825          * it would work fine for a few minutes to hours and then stop, on
 826          * other device it would no traffic could be sent or received at all.
 827          * Testing shows that when PHY auto polling is disabled these problems
 828          * go away.
 829          */
 830         gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
 831
 832         /* Configure the MDIO Clock 2.5 MHz */
 833         gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
 834
 835         /* Disable the xMII interface and clear it's isolation bit */
 836         for (i = 0; i < priv->hw_info->max_ports; i++)
 837                 gswip_mii_mask_cfg(priv,
 838                                    GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
 839                                    0, i);
 840
 841         /* enable special tag insertion on cpu port */
 842         gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
 843                           GSWIP_FDMA_PCTRLp(cpu_port));
 844
 845         /* accept special tag in ingress direction */
 846         gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
 847                           GSWIP_PCE_PCTRL_0p(cpu_port));
 848
 849         gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
 850                           GSWIP_MAC_CTRL_2p(cpu_port));
 851         gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN,
 852                        GSWIP_MAC_FLEN);
 853         gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
 854                           GSWIP_BM_QUEUE_GCTRL);
 855
 856         /* VLAN aware Switching */
 857         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
 858
 859         /* Flush MAC Table */
 860         gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
 861
 862         err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
 863                                      GSWIP_PCE_GCTRL_0_MTFL);
 864         if (err) {
 865                 dev_err(priv->dev, "MAC flushing didn't finish\n");
 866                 return err;
 867         }
 868
 869         gswip_port_enable(ds, cpu_port, NULL);
 870
 871         ds->configure_vlan_while_not_filtering = false;
 872
 873         return 0;
 874 }
 875
 876 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
 877                                                     int port,
 878                                                     enum dsa_tag_protocol mp)
 879 {
 880         return DSA_TAG_PROTO_GSWIP;
 881 }
 882
 883 static int gswip_vlan_active_create(struct gswip_priv *priv,
 884                                     struct net_device *bridge,
 885                                     int fid, u16 vid)
 886 {
 887         struct gswip_pce_table_entry vlan_active = {0,};
 888         unsigned int max_ports = priv->hw_info->max_ports;
 889         int idx = -1;
 890         int err;
 891         int i;
 892
 893         /* Look for a free slot */
 894         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 895                 if (!priv->vlans[i].bridge) {
 896                         idx = i;
 897                         break;
 898                 }
 899         }
 900
 901         if (idx == -1)
 902                 return -ENOSPC;
 903
 904         if (fid == -1)
 905                 fid = idx;
 906
 907         vlan_active.index = idx;
 908         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 909         vlan_active.key[0] = vid;
 910         vlan_active.val[0] = fid;
 911         vlan_active.valid = true;
 912
 913         err = gswip_pce_table_entry_write(priv, &vlan_active);
 914         if (err) {
 915                 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
 916                 return err;
 917         }
 918
 919         priv->vlans[idx].bridge = bridge;
 920         priv->vlans[idx].vid = vid;
 921         priv->vlans[idx].fid = fid;
 922
 923         return idx;
 924 }
 925
 926 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
 927 {
 928         struct gswip_pce_table_entry vlan_active = {0,};
 929         int err;
 930
 931         vlan_active.index = idx;
 932         vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
 933         vlan_active.valid = false;
 934         err = gswip_pce_table_entry_write(priv, &vlan_active);
 935         if (err)
 936                 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
 937         priv->vlans[idx].bridge = NULL;
 938
 939         return err;
 940 }
 941
 942 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
 943                                   struct net_device *bridge, int port)
 944 {
 945         struct gswip_pce_table_entry vlan_mapping = {0,};
 946         unsigned int max_ports = priv->hw_info->max_ports;
 947         unsigned int cpu_port = priv->hw_info->cpu_port;
 948         bool active_vlan_created = false;
 949         int idx = -1;
 950         int i;
 951         int err;
 952
 953         /* Check if there is already a page for this bridge */
 954         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
 955                 if (priv->vlans[i].bridge == bridge) {
 956                         idx = i;
 957                         break;
 958                 }
 959         }
 960
 961         /* If this bridge is not programmed yet, add a Active VLAN table
 962          * entry in a free slot and prepare the VLAN mapping table entry.
 963          */
 964         if (idx == -1) {
 965                 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
 966                 if (idx < 0)
 967                         return idx;
 968                 active_vlan_created = true;
 969
 970                 vlan_mapping.index = idx;
 971                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 972                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
 973                 vlan_mapping.val[0] = 0;
 974         } else {
 975                 /* Read the existing VLAN mapping entry from the switch */
 976                 vlan_mapping.index = idx;
 977                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
 978                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
 979                 if (err) {
 980                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
 981                                 err);
 982                         return err;
 983                 }
 984         }
 985
 986         /* Update the VLAN mapping entry and write it to the switch */
 987         vlan_mapping.val[1] |= BIT(cpu_port);
 988         vlan_mapping.val[1] |= BIT(port);
 989         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
 990         if (err) {
 991                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
 992                 /* In case an Active VLAN was creaetd delete it again */
 993                 if (active_vlan_created)
 994                         gswip_vlan_active_remove(priv, idx);
 995                 return err;
 996         }
 997
 998         gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
 999         return 0;
1000 }
1001
1002 static int gswip_vlan_add_aware(struct gswip_priv *priv,
1003                                 struct net_device *bridge, int port,
1004                                 u16 vid, bool untagged,
1005                                 bool pvid)
1006 {
1007         struct gswip_pce_table_entry vlan_mapping = {0,};
1008         unsigned int max_ports = priv->hw_info->max_ports;
1009         unsigned int cpu_port = priv->hw_info->cpu_port;
1010         bool active_vlan_created = false;
1011         int idx = -1;
1012         int fid = -1;
1013         int i;
1014         int err;
1015
1016         /* Check if there is already a page for this bridge */
1017         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1018                 if (priv->vlans[i].bridge == bridge) {
1019                         if (fid != -1 && fid != priv->vlans[i].fid)
1020                                 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1021                         fid = priv->vlans[i].fid;
1022                         if (priv->vlans[i].vid == vid) {
1023                                 idx = i;
1024                                 break;
1025                         }
1026                 }
1027         }
1028
1029         /* If this bridge is not programmed yet, add a Active VLAN table
1030          * entry in a free slot and prepare the VLAN mapping table entry.
1031          */
1032         if (idx == -1) {
1033                 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1034                 if (idx < 0)
1035                         return idx;
1036                 active_vlan_created = true;
1037
1038                 vlan_mapping.index = idx;
1039                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1040                 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1041                 vlan_mapping.val[0] = vid;
1042         } else {
1043                 /* Read the existing VLAN mapping entry from the switch */
1044                 vlan_mapping.index = idx;
1045                 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1046                 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1047                 if (err) {
1048                         dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1049                                 err);
1050                         return err;
1051                 }
1052         }
1053
1054         vlan_mapping.val[0] = vid;
1055         /* Update the VLAN mapping entry and write it to the switch */
1056         vlan_mapping.val[1] |= BIT(cpu_port);
1057         vlan_mapping.val[2] |= BIT(cpu_port);
1058         vlan_mapping.val[1] |= BIT(port);
1059         if (untagged)
1060                 vlan_mapping.val[2] &= ~BIT(port);
1061         else
1062                 vlan_mapping.val[2] |= BIT(port);
1063         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1064         if (err) {
1065                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1066                 /* In case an Active VLAN was creaetd delete it again */
1067                 if (active_vlan_created)
1068                         gswip_vlan_active_remove(priv, idx);
1069                 return err;
1070         }
1071
1072         if (pvid)
1073                 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1074
1075         return 0;
1076 }
1077
1078 static int gswip_vlan_remove(struct gswip_priv *priv,
1079                              struct net_device *bridge, int port,
1080                              u16 vid, bool pvid, bool vlan_aware)
1081 {
1082         struct gswip_pce_table_entry vlan_mapping = {0,};
1083         unsigned int max_ports = priv->hw_info->max_ports;
1084         unsigned int cpu_port = priv->hw_info->cpu_port;
1085         int idx = -1;
1086         int i;
1087         int err;
1088
1089         /* Check if there is already a page for this bridge */
1090         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1091                 if (priv->vlans[i].bridge == bridge &&
1092                     (!vlan_aware || priv->vlans[i].vid == vid)) {
1093                         idx = i;
1094                         break;
1095                 }
1096         }
1097
1098         if (idx == -1) {
1099                 dev_err(priv->dev, "bridge to leave does not exists\n");
1100                 return -ENOENT;
1101         }
1102
1103         vlan_mapping.index = idx;
1104         vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1105         err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1106         if (err) {
1107                 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1108                 return err;
1109         }
1110
1111         vlan_mapping.val[1] &= ~BIT(port);
1112         vlan_mapping.val[2] &= ~BIT(port);
1113         err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1114         if (err) {
1115                 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1116                 return err;
1117         }
1118
1119         /* In case all ports are removed from the bridge, remove the VLAN */
1120         if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1121                 err = gswip_vlan_active_remove(priv, idx);
1122                 if (err) {
1123                         dev_err(priv->dev, "failed to write active VLAN: %d\n",
1124                                 err);
1125                         return err;
1126                 }
1127         }
1128
1129         /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1130         if (pvid)
1131                 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1132
1133         return 0;
1134 }
1135
1136 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1137                                   struct net_device *bridge)
1138 {
1139         struct gswip_priv *priv = ds->priv;
1140         int err;
1141
1142         /* When the bridge uses VLAN filtering we have to configure VLAN
1143          * specific bridges. No bridge is configured here.
1144          */
1145         if (!br_vlan_enabled(bridge)) {
1146                 err = gswip_vlan_add_unaware(priv, bridge, port);
1147                 if (err)
1148                         return err;
1149                 priv->port_vlan_filter &= ~BIT(port);
1150         } else {
1151                 priv->port_vlan_filter |= BIT(port);
1152         }
1153         return gswip_add_single_port_br(priv, port, false);
1154 }
1155
1156 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1157                                     struct net_device *bridge)
1158 {
1159         struct gswip_priv *priv = ds->priv;
1160
1161         gswip_add_single_port_br(priv, port, true);
1162
1163         /* When the bridge uses VLAN filtering we have to configure VLAN
1164          * specific bridges. No bridge is configured here.
1165          */
1166         if (!br_vlan_enabled(bridge))
1167                 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1168 }
1169
1170 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1171                                    const struct switchdev_obj_port_vlan *vlan,
1172                                    struct netlink_ext_ack *extack)
1173 {
1174         struct gswip_priv *priv = ds->priv;
1175         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1176         unsigned int max_ports = priv->hw_info->max_ports;
1177         int pos = max_ports;
1178         int i, idx = -1;
1179
1180         /* We only support VLAN filtering on bridges */
1181         if (!dsa_is_cpu_port(ds, port) && !bridge)
1182                 return -EOPNOTSUPP;
1183
1184         /* Check if there is already a page for this VLAN */
1185         for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1186                 if (priv->vlans[i].bridge == bridge &&
1187                     priv->vlans[i].vid == vlan->vid) {
1188                         idx = i;
1189                         break;
1190                 }
1191         }
1192
1193         /* If this VLAN is not programmed yet, we have to reserve
1194          * one entry in the VLAN table. Make sure we start at the
1195          * next position round.
1196          */
1197         if (idx == -1) {
1198                 /* Look for a free slot */
1199                 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1200                         if (!priv->vlans[pos].bridge) {
1201                                 idx = pos;
1202                                 pos++;
1203                                 break;
1204                         }
1205                 }
1206
1207                 if (idx == -1) {
1208                         NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1209                         return -ENOSPC;
1210                 }
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1217                                const struct switchdev_obj_port_vlan *vlan,
1218                                struct netlink_ext_ack *extack)
1219 {
1220         struct gswip_priv *priv = ds->priv;
1221         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1222         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1223         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1224         int err;
1225
1226         err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1227         if (err)
1228                 return err;
1229
1230         /* We have to receive all packets on the CPU port and should not
1231          * do any VLAN filtering here. This is also called with bridge
1232          * NULL and then we do not know for which bridge to configure
1233          * this.
1234          */
1235         if (dsa_is_cpu_port(ds, port))
1236                 return 0;
1237
1238         return gswip_vlan_add_aware(priv, bridge, port, vlan->vid,
1239                                     untagged, pvid);
1240 }
1241
1242 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1243                                const struct switchdev_obj_port_vlan *vlan)
1244 {
1245         struct gswip_priv *priv = ds->priv;
1246         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1247         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1248
1249         /* We have to receive all packets on the CPU port and should not
1250          * do any VLAN filtering here. This is also called with bridge
1251          * NULL and then we do not know for which bridge to configure
1252          * this.
1253          */
1254         if (dsa_is_cpu_port(ds, port))
1255                 return 0;
1256
1257         return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true);
1258 }
1259
1260 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1261 {
1262         struct gswip_priv *priv = ds->priv;
1263         struct gswip_pce_table_entry mac_bridge = {0,};
1264         int i;
1265         int err;
1266
1267         for (i = 0; i < 2048; i++) {
1268                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1269                 mac_bridge.index = i;
1270
1271                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1272                 if (err) {
1273                         dev_err(priv->dev, "failed to read mac bridge: %d\n",
1274                                 err);
1275                         return;
1276                 }
1277
1278                 if (!mac_bridge.valid)
1279                         continue;
1280
1281                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1282                         continue;
1283
1284                 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1285                         continue;
1286
1287                 mac_bridge.valid = false;
1288                 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1289                 if (err) {
1290                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1291                                 err);
1292                         return;
1293                 }
1294         }
1295 }
1296
1297 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1298 {
1299         struct gswip_priv *priv = ds->priv;
1300         u32 stp_state;
1301
1302         switch (state) {
1303         case BR_STATE_DISABLED:
1304                 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1305                                   GSWIP_SDMA_PCTRLp(port));
1306                 return;
1307         case BR_STATE_BLOCKING:
1308         case BR_STATE_LISTENING:
1309                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1310                 break;
1311         case BR_STATE_LEARNING:
1312                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1313                 break;
1314         case BR_STATE_FORWARDING:
1315                 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1316                 break;
1317         default:
1318                 dev_err(priv->dev, "invalid STP state: %d\n", state);
1319                 return;
1320         }
1321
1322         gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1323                           GSWIP_SDMA_PCTRLp(port));
1324         gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1325                           GSWIP_PCE_PCTRL_0p(port));
1326 }
1327
1328 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1329                           const unsigned char *addr, u16 vid, bool add)
1330 {
1331         struct gswip_priv *priv = ds->priv;
1332         struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1333         struct gswip_pce_table_entry mac_bridge = {0,};
1334         unsigned int cpu_port = priv->hw_info->cpu_port;
1335         int fid = -1;
1336         int i;
1337         int err;
1338
1339         if (!bridge)
1340                 return -EINVAL;
1341
1342         for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1343                 if (priv->vlans[i].bridge == bridge) {
1344                         fid = priv->vlans[i].fid;
1345                         break;
1346                 }
1347         }
1348
1349         if (fid == -1) {
1350                 dev_err(priv->dev, "Port not part of a bridge\n");
1351                 return -EINVAL;
1352         }
1353
1354         mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1355         mac_bridge.key_mode = true;
1356         mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1357         mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1358         mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1359         mac_bridge.key[3] = fid;
1360         mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1361         mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1362         mac_bridge.valid = add;
1363
1364         err = gswip_pce_table_entry_write(priv, &mac_bridge);
1365         if (err)
1366                 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1367
1368         return err;
1369 }
1370
1371 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1372                               const unsigned char *addr, u16 vid)
1373 {
1374         return gswip_port_fdb(ds, port, addr, vid, true);
1375 }
1376
1377 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1378                               const unsigned char *addr, u16 vid)
1379 {
1380         return gswip_port_fdb(ds, port, addr, vid, false);
1381 }
1382
1383 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1384                                dsa_fdb_dump_cb_t *cb, void *data)
1385 {
1386         struct gswip_priv *priv = ds->priv;
1387         struct gswip_pce_table_entry mac_bridge = {0,};
1388         unsigned char addr[6];
1389         int i;
1390         int err;
1391
1392         for (i = 0; i < 2048; i++) {
1393                 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1394                 mac_bridge.index = i;
1395
1396                 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1397                 if (err) {
1398                         dev_err(priv->dev, "failed to write mac bridge: %d\n",
1399                                 err);
1400                         return err;
1401                 }
1402
1403                 if (!mac_bridge.valid)
1404                         continue;
1405
1406                 addr[5] = mac_bridge.key[0] & 0xff;
1407                 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1408                 addr[3] = mac_bridge.key[1] & 0xff;
1409                 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1410                 addr[1] = mac_bridge.key[2] & 0xff;
1411                 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1412                 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1413                         if (mac_bridge.val[0] & BIT(port)) {
1414                                 err = cb(addr, 0, true, data);
1415                                 if (err)
1416                                         return err;
1417                         }
1418                 } else {
1419                         if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
1420                                 err = cb(addr, 0, false, data);
1421                                 if (err)
1422                                         return err;
1423                         }
1424                 }
1425         }
1426         return 0;
1427 }
1428
1429 static void gswip_phylink_set_capab(unsigned long *supported,
1430                                     struct phylink_link_state *state)
1431 {
1432         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1433
1434         /* Allow all the expected bits */
1435         phylink_set(mask, Autoneg);
1436         phylink_set_port_modes(mask);
1437         phylink_set(mask, Pause);
1438         phylink_set(mask, Asym_Pause);
1439
1440         /* With the exclusion of MII, Reverse MII and Reduced MII, we
1441          * support Gigabit, including Half duplex
1442          */
1443         if (state->interface != PHY_INTERFACE_MODE_MII &&
1444             state->interface != PHY_INTERFACE_MODE_REVMII &&
1445             state->interface != PHY_INTERFACE_MODE_RMII) {
1446                 phylink_set(mask, 1000baseT_Full);
1447                 phylink_set(mask, 1000baseT_Half);
1448         }
1449
1450         phylink_set(mask, 10baseT_Half);
1451         phylink_set(mask, 10baseT_Full);
1452         phylink_set(mask, 100baseT_Half);
1453         phylink_set(mask, 100baseT_Full);
1454
1455         bitmap_and(supported, supported, mask,
1456                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1457         bitmap_and(state->advertising, state->advertising, mask,
1458                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1459 }
1460
1461 static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port,
1462                                           unsigned long *supported,
1463                                           struct phylink_link_state *state)
1464 {
1465         switch (port) {
1466         case 0:
1467         case 1:
1468                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1469                     state->interface != PHY_INTERFACE_MODE_MII &&
1470                     state->interface != PHY_INTERFACE_MODE_REVMII &&
1471                     state->interface != PHY_INTERFACE_MODE_RMII)
1472                         goto unsupported;
1473                 break;
1474         case 2:
1475         case 3:
1476         case 4:
1477                 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1478                         goto unsupported;
1479                 break;
1480         case 5:
1481                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1482                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1483                         goto unsupported;
1484                 break;
1485         default:
1486                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1487                 dev_err(ds->dev, "Unsupported port: %i\n", port);
1488                 return;
1489         }
1490
1491         gswip_phylink_set_capab(supported, state);
1492
1493         return;
1494
1495 unsupported:
1496         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1497         dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1498                 phy_modes(state->interface), port);
1499 }
1500
1501 static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port,
1502                                           unsigned long *supported,
1503                                           struct phylink_link_state *state)
1504 {
1505         switch (port) {
1506         case 0:
1507                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1508                     state->interface != PHY_INTERFACE_MODE_GMII &&
1509                     state->interface != PHY_INTERFACE_MODE_RMII)
1510                         goto unsupported;
1511                 break;
1512         case 1:
1513         case 2:
1514         case 3:
1515         case 4:
1516                 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1517                         goto unsupported;
1518                 break;
1519         case 5:
1520                 if (!phy_interface_mode_is_rgmii(state->interface) &&
1521                     state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1522                     state->interface != PHY_INTERFACE_MODE_RMII)
1523                         goto unsupported;
1524                 break;
1525         default:
1526                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1527                 dev_err(ds->dev, "Unsupported port: %i\n", port);
1528                 return;
1529         }
1530
1531         gswip_phylink_set_capab(supported, state);
1532
1533         return;
1534
1535 unsupported:
1536         bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1537         dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1538                 phy_modes(state->interface), port);
1539 }
1540
1541 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1542 {
1543         u32 mdio_phy;
1544
1545         if (link)
1546                 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1547         else
1548                 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1549
1550         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1551                         GSWIP_MDIO_PHYp(port));
1552 }
1553
1554 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1555                                  phy_interface_t interface)
1556 {
1557         u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1558
1559         switch (speed) {
1560         case SPEED_10:
1561                 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1562
1563                 if (interface == PHY_INTERFACE_MODE_RMII)
1564                         mii_cfg = GSWIP_MII_CFG_RATE_M50;
1565                 else
1566                         mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1567
1568                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1569                 break;
1570
1571         case SPEED_100:
1572                 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1573
1574                 if (interface == PHY_INTERFACE_MODE_RMII)
1575                         mii_cfg = GSWIP_MII_CFG_RATE_M50;
1576                 else
1577                         mii_cfg = GSWIP_MII_CFG_RATE_M25;
1578
1579                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1580                 break;
1581
1582         case SPEED_1000:
1583                 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1584
1585                 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1586
1587                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1588                 break;
1589         }
1590
1591         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1592                         GSWIP_MDIO_PHYp(port));
1593         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1594         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1595                           GSWIP_MAC_CTRL_0p(port));
1596 }
1597
1598 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1599 {
1600         u32 mac_ctrl_0, mdio_phy;
1601
1602         if (duplex == DUPLEX_FULL) {
1603                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1604                 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1605         } else {
1606                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1607                 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1608         }
1609
1610         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1611                           GSWIP_MAC_CTRL_0p(port));
1612         gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1613                         GSWIP_MDIO_PHYp(port));
1614 }
1615
1616 static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1617                                  bool tx_pause, bool rx_pause)
1618 {
1619         u32 mac_ctrl_0, mdio_phy;
1620
1621         if (tx_pause && rx_pause) {
1622                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1623                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1624                            GSWIP_MDIO_PHY_FCONRX_EN;
1625         } else if (tx_pause) {
1626                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1627                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1628                            GSWIP_MDIO_PHY_FCONRX_DIS;
1629         } else if (rx_pause) {
1630                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1631                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1632                            GSWIP_MDIO_PHY_FCONRX_EN;
1633         } else {
1634                 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1635                 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1636                            GSWIP_MDIO_PHY_FCONRX_DIS;
1637         }
1638
1639         gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1640                           mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1641         gswip_mdio_mask(priv,
1642                         GSWIP_MDIO_PHY_FCONTX_MASK |
1643                         GSWIP_MDIO_PHY_FCONRX_MASK,
1644                         mdio_phy, GSWIP_MDIO_PHYp(port));
1645 }
1646
1647 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1648                                      unsigned int mode,
1649                                      const struct phylink_link_state *state)
1650 {
1651         struct gswip_priv *priv = ds->priv;
1652         u32 miicfg = 0;
1653
1654         miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1655
1656         switch (state->interface) {
1657         case PHY_INTERFACE_MODE_MII:
1658         case PHY_INTERFACE_MODE_INTERNAL:
1659                 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1660                 break;
1661         case PHY_INTERFACE_MODE_REVMII:
1662                 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1663                 break;
1664         case PHY_INTERFACE_MODE_RMII:
1665                 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1666                 break;
1667         case PHY_INTERFACE_MODE_RGMII:
1668         case PHY_INTERFACE_MODE_RGMII_ID:
1669         case PHY_INTERFACE_MODE_RGMII_RXID:
1670         case PHY_INTERFACE_MODE_RGMII_TXID:
1671                 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1672                 break;
1673         case PHY_INTERFACE_MODE_GMII:
1674                 miicfg |= GSWIP_MII_CFG_MODE_GMII;
1675                 break;
1676         default:
1677                 dev_err(ds->dev,
1678                         "Unsupported interface: %d\n", state->interface);
1679                 return;
1680         }
1681
1682         gswip_mii_mask_cfg(priv,
1683                            GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1684                            GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1685                            miicfg, port);
1686
1687         switch (state->interface) {
1688         case PHY_INTERFACE_MODE_RGMII_ID:
1689                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1690                                           GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1691                 break;
1692         case PHY_INTERFACE_MODE_RGMII_RXID:
1693                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1694                 break;
1695         case PHY_INTERFACE_MODE_RGMII_TXID:
1696                 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1697                 break;
1698         default:
1699                 break;
1700         }
1701 }
1702
1703 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1704                                         unsigned int mode,
1705                                         phy_interface_t interface)
1706 {
1707         struct gswip_priv *priv = ds->priv;
1708
1709         gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1710
1711         if (!dsa_is_cpu_port(ds, port))
1712                 gswip_port_set_link(priv, port, false);
1713 }
1714
1715 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1716                                       unsigned int mode,
1717                                       phy_interface_t interface,
1718                                       struct phy_device *phydev,
1719                                       int speed, int duplex,
1720                                       bool tx_pause, bool rx_pause)
1721 {
1722         struct gswip_priv *priv = ds->priv;
1723
1724         if (!dsa_is_cpu_port(ds, port)) {
1725                 gswip_port_set_link(priv, port, true);
1726                 gswip_port_set_speed(priv, port, speed, interface);
1727                 gswip_port_set_duplex(priv, port, duplex);
1728                 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1729         }
1730
1731         gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1732 }
1733
1734 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1735                               uint8_t *data)
1736 {
1737         int i;
1738
1739         if (stringset != ETH_SS_STATS)
1740                 return;
1741
1742         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1743                 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1744                         ETH_GSTRING_LEN);
1745 }
1746
1747 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1748                                     u32 index)
1749 {
1750         u32 result;
1751         int err;
1752
1753         gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1754         gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1755                                 GSWIP_BM_RAM_CTRL_OPMOD,
1756                               table | GSWIP_BM_RAM_CTRL_BAS,
1757                               GSWIP_BM_RAM_CTRL);
1758
1759         err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1760                                      GSWIP_BM_RAM_CTRL_BAS);
1761         if (err) {
1762                 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1763                         table, index);
1764                 return 0;
1765         }
1766
1767         result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1768         result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1769
1770         return result;
1771 }
1772
1773 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1774                                     uint64_t *data)
1775 {
1776         struct gswip_priv *priv = ds->priv;
1777         const struct gswip_rmon_cnt_desc *rmon_cnt;
1778         int i;
1779         u64 high;
1780
1781         for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1782                 rmon_cnt = &gswip_rmon_cnt[i];
1783
1784                 data[i] = gswip_bcm_ram_entry_read(priv, port,
1785                                                    rmon_cnt->offset);
1786                 if (rmon_cnt->size == 2) {
1787                         high = gswip_bcm_ram_entry_read(priv, port,
1788                                                         rmon_cnt->offset + 1);
1789                         data[i] |= high << 32;
1790                 }
1791         }
1792 }
1793
1794 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1795 {
1796         if (sset != ETH_SS_STATS)
1797                 return 0;
1798
1799         return ARRAY_SIZE(gswip_rmon_cnt);
1800 }
1801
1802 static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1803         .get_tag_protocol       = gswip_get_tag_protocol,
1804         .setup                  = gswip_setup,
1805         .port_enable            = gswip_port_enable,
1806         .port_disable           = gswip_port_disable,
1807         .port_bridge_join       = gswip_port_bridge_join,
1808         .port_bridge_leave      = gswip_port_bridge_leave,
1809         .port_fast_age          = gswip_port_fast_age,
1810         .port_vlan_filtering    = gswip_port_vlan_filtering,
1811         .port_vlan_add          = gswip_port_vlan_add,
1812         .port_vlan_del          = gswip_port_vlan_del,
1813         .port_stp_state_set     = gswip_port_stp_state_set,
1814         .port_fdb_add           = gswip_port_fdb_add,
1815         .port_fdb_del           = gswip_port_fdb_del,
1816         .port_fdb_dump          = gswip_port_fdb_dump,
1817         .phylink_validate       = gswip_xrx200_phylink_validate,
1818         .phylink_mac_config     = gswip_phylink_mac_config,
1819         .phylink_mac_link_down  = gswip_phylink_mac_link_down,
1820         .phylink_mac_link_up    = gswip_phylink_mac_link_up,
1821         .get_strings            = gswip_get_strings,
1822         .get_ethtool_stats      = gswip_get_ethtool_stats,
1823         .get_sset_count         = gswip_get_sset_count,
1824 };
1825
1826 static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1827         .get_tag_protocol       = gswip_get_tag_protocol,
1828         .setup                  = gswip_setup,
1829         .port_enable            = gswip_port_enable,
1830         .port_disable           = gswip_port_disable,
1831         .port_bridge_join       = gswip_port_bridge_join,
1832         .port_bridge_leave      = gswip_port_bridge_leave,
1833         .port_fast_age          = gswip_port_fast_age,
1834         .port_vlan_filtering    = gswip_port_vlan_filtering,
1835         .port_vlan_add          = gswip_port_vlan_add,
1836         .port_vlan_del          = gswip_port_vlan_del,
1837         .port_stp_state_set     = gswip_port_stp_state_set,
1838         .port_fdb_add           = gswip_port_fdb_add,
1839         .port_fdb_del           = gswip_port_fdb_del,
1840         .port_fdb_dump          = gswip_port_fdb_dump,
1841         .phylink_validate       = gswip_xrx300_phylink_validate,
1842         .phylink_mac_config     = gswip_phylink_mac_config,
1843         .phylink_mac_link_down  = gswip_phylink_mac_link_down,
1844         .phylink_mac_link_up    = gswip_phylink_mac_link_up,
1845         .get_strings            = gswip_get_strings,
1846         .get_ethtool_stats      = gswip_get_ethtool_stats,
1847         .get_sset_count         = gswip_get_sset_count,
1848 };
1849
1850 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1851         .fe_firmware_name = "/*(DEBLOBBED)*/",
1852         .ge_firmware_name = "/*(DEBLOBBED)*/",
1853 };
1854
1855 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1856         .fe_firmware_name = "/*(DEBLOBBED)*/",
1857         .ge_firmware_name = "/*(DEBLOBBED)*/",
1858 };
1859
1860 static const struct xway_gphy_match_data xrx300_gphy_data = {
1861         .fe_firmware_name = "/*(DEBLOBBED)*/",
1862         .ge_firmware_name = "/*(DEBLOBBED)*/",
1863 };
1864
1865 static const struct of_device_id xway_gphy_match[] = {
1866         { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1867         { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1868         { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1869         { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1870         { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1871         {},
1872 };
1873
1874 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1875 {
1876         struct device *dev = priv->dev;
1877         const struct firmware *fw;
1878         void *fw_addr;
1879         dma_addr_t dma_addr;
1880         dma_addr_t dev_addr;
1881         size_t size;
1882         int ret;
1883
1884         ret = clk_prepare_enable(gphy_fw->clk_gate);
1885         if (ret)
1886                 return ret;
1887
1888         reset_control_assert(gphy_fw->reset);
1889
1890         /* The vendor BSP uses a 200ms delay after asserting the reset line.
1891          * Without this some users are observing that the PHY is not coming up
1892          * on the MDIO bus.
1893          */
1894         msleep(200);
1895
1896         ret = reject_firmware(&fw, gphy_fw->fw_name, dev);
1897         if (ret) {
1898                 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1899                         gphy_fw->fw_name, ret);
1900                 return ret;
1901         }
1902
1903         /* GPHY cores need the firmware code in a persistent and contiguous
1904          * memory area with a 16 kB boundary aligned start address.
1905          */
1906         size = fw->size + XRX200_GPHY_FW_ALIGN;
1907
1908         fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1909         if (fw_addr) {
1910                 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1911                 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1912                 memcpy(fw_addr, fw->data, fw->size);
1913         } else {
1914                 dev_err(dev, "failed to alloc firmware memory\n");
1915                 release_firmware(fw);
1916                 return -ENOMEM;
1917         }
1918
1919         release_firmware(fw);
1920
1921         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1922         if (ret)
1923                 return ret;
1924
1925         reset_control_deassert(gphy_fw->reset);
1926
1927         return ret;
1928 }
1929
1930 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1931                                struct gswip_gphy_fw *gphy_fw,
1932                                struct device_node *gphy_fw_np, int i)
1933 {
1934         struct device *dev = priv->dev;
1935         u32 gphy_mode;
1936         int ret;
1937         char gphyname[10];
1938
1939         snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1940
1941         gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1942         if (IS_ERR(gphy_fw->clk_gate)) {
1943                 dev_err(dev, "Failed to lookup gate clock\n");
1944                 return PTR_ERR(gphy_fw->clk_gate);
1945         }
1946
1947         ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1948         if (ret)
1949                 return ret;
1950
1951         ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1952         /* Default to GE mode */
1953         if (ret)
1954                 gphy_mode = GPHY_MODE_GE;
1955
1956         switch (gphy_mode) {
1957         case GPHY_MODE_FE:
1958                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1959                 break;
1960         case GPHY_MODE_GE:
1961                 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1962                 break;
1963         default:
1964                 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1965                 return -EINVAL;
1966         }
1967
1968         gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1969         if (IS_ERR(gphy_fw->reset)) {
1970                 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1971                         dev_err(dev, "Failed to lookup gphy reset\n");
1972                 return PTR_ERR(gphy_fw->reset);
1973         }
1974
1975         return gswip_gphy_fw_load(priv, gphy_fw);
1976 }
1977
1978 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1979                                  struct gswip_gphy_fw *gphy_fw)
1980 {
1981         int ret;
1982
1983         /* check if the device was fully probed */
1984         if (!gphy_fw->fw_name)
1985                 return;
1986
1987         ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1988         if (ret)
1989                 dev_err(priv->dev, "can not reset GPHY FW pointer");
1990
1991         clk_disable_unprepare(gphy_fw->clk_gate);
1992
1993         reset_control_put(gphy_fw->reset);
1994 }
1995
1996 static int gswip_gphy_fw_list(struct gswip_priv *priv,
1997                               struct device_node *gphy_fw_list_np, u32 version)
1998 {
1999         struct device *dev = priv->dev;
2000         struct device_node *gphy_fw_np;
2001         const struct of_device_id *match;
2002         int err;
2003         int i = 0;
2004
2005         /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
2006          * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
2007          * needs a different GPHY firmware.
2008          */
2009         if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
2010                 switch (version) {
2011                 case GSWIP_VERSION_2_0:
2012                         priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
2013                         break;
2014                 case GSWIP_VERSION_2_1:
2015                         priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
2016                         break;
2017                 default:
2018                         dev_err(dev, "unknown GSWIP version: 0x%x", version);
2019                         return -ENOENT;
2020                 }
2021         }
2022
2023         match = of_match_node(xway_gphy_match, gphy_fw_list_np);
2024         if (match && match->data)
2025                 priv->gphy_fw_name_cfg = match->data;
2026
2027         if (!priv->gphy_fw_name_cfg) {
2028                 dev_err(dev, "GPHY compatible type not supported");
2029                 return -ENOENT;
2030         }
2031
2032         priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
2033         if (!priv->num_gphy_fw)
2034                 return -ENOENT;
2035
2036         priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
2037                                                            "lantiq,rcu");
2038         if (IS_ERR(priv->rcu_regmap))
2039                 return PTR_ERR(priv->rcu_regmap);
2040
2041         priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
2042                                            sizeof(*priv->gphy_fw),
2043                                            GFP_KERNEL | __GFP_ZERO);
2044         if (!priv->gphy_fw)
2045                 return -ENOMEM;
2046
2047         for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
2048                 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
2049                                           gphy_fw_np, i);
2050                 if (err) {
2051                         of_node_put(gphy_fw_np);
2052                         goto remove_gphy;
2053                 }
2054                 i++;
2055         }
2056
2057         /* The standalone PHY11G requires 300ms to be fully
2058          * initialized and ready for any MDIO communication after being
2059          * taken out of reset. For the SoC-internal GPHY variant there
2060          * is no (known) documentation for the minimum time after a
2061          * reset. Use the same value as for the standalone variant as
2062          * some users have reported internal PHYs not being detected
2063          * without any delay.
2064          */
2065         msleep(300);
2066
2067         return 0;
2068
2069 remove_gphy:
2070         for (i = 0; i < priv->num_gphy_fw; i++)
2071                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2072         return err;
2073 }
2074
2075 static int gswip_probe(struct platform_device *pdev)
2076 {
2077         struct gswip_priv *priv;
2078         struct device_node *np, *mdio_np, *gphy_fw_np;
2079         struct device *dev = &pdev->dev;
2080         int err;
2081         int i;
2082         u32 version;
2083
2084         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2085         if (!priv)
2086                 return -ENOMEM;
2087
2088         priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2089         if (IS_ERR(priv->gswip))
2090                 return PTR_ERR(priv->gswip);
2091
2092         priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2093         if (IS_ERR(priv->mdio))
2094                 return PTR_ERR(priv->mdio);
2095
2096         priv->mii = devm_platform_ioremap_resource(pdev, 2);
2097         if (IS_ERR(priv->mii))
2098                 return PTR_ERR(priv->mii);
2099
2100         priv->hw_info = of_device_get_match_data(dev);
2101         if (!priv->hw_info)
2102                 return -EINVAL;
2103
2104         priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2105         if (!priv->ds)
2106                 return -ENOMEM;
2107
2108         priv->ds->dev = dev;
2109         priv->ds->num_ports = priv->hw_info->max_ports;
2110         priv->ds->priv = priv;
2111         priv->ds->ops = priv->hw_info->ops;
2112         priv->dev = dev;
2113         version = gswip_switch_r(priv, GSWIP_VERSION);
2114
2115         np = dev->of_node;
2116         switch (version) {
2117         case GSWIP_VERSION_2_0:
2118         case GSWIP_VERSION_2_1:
2119                 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip"))
2120                         return -EINVAL;
2121                 break;
2122         case GSWIP_VERSION_2_2:
2123         case GSWIP_VERSION_2_2_ETC:
2124                 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") &&
2125                     !of_device_is_compatible(np, "lantiq,xrx330-gswip"))
2126                         return -EINVAL;
2127                 break;
2128         default:
2129                 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2130                 return -ENOENT;
2131         }
2132
2133         /* bring up the mdio bus */
2134         gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2135         if (gphy_fw_np) {
2136                 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2137                 of_node_put(gphy_fw_np);
2138                 if (err) {
2139                         dev_err(dev, "gphy fw probe failed\n");
2140                         return err;
2141                 }
2142         }
2143
2144         /* bring up the mdio bus */
2145         mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
2146         if (mdio_np) {
2147                 err = gswip_mdio(priv, mdio_np);
2148                 if (err) {
2149                         dev_err(dev, "mdio probe failed\n");
2150                         goto put_mdio_node;
2151                 }
2152         }
2153
2154         err = dsa_register_switch(priv->ds);
2155         if (err) {
2156                 dev_err(dev, "dsa switch register failed: %i\n", err);
2157                 goto mdio_bus;
2158         }
2159         if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2160                 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
2161                         priv->hw_info->cpu_port);
2162                 err = -EINVAL;
2163                 goto disable_switch;
2164         }
2165
2166         platform_set_drvdata(pdev, priv);
2167
2168         dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2169                  (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2170                  (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2171         return 0;
2172
2173 disable_switch:
2174         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2175         dsa_unregister_switch(priv->ds);
2176 mdio_bus:
2177         if (mdio_np) {
2178                 mdiobus_unregister(priv->ds->slave_mii_bus);
2179                 mdiobus_free(priv->ds->slave_mii_bus);
2180         }
2181 put_mdio_node:
2182         of_node_put(mdio_np);
2183         for (i = 0; i < priv->num_gphy_fw; i++)
2184                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2185         return err;
2186 }
2187
2188 static int gswip_remove(struct platform_device *pdev)
2189 {
2190         struct gswip_priv *priv = platform_get_drvdata(pdev);
2191         int i;
2192
2193         if (!priv)
2194                 return 0;
2195
2196         /* disable the switch */
2197         gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2198
2199         dsa_unregister_switch(priv->ds);
2200
2201         if (priv->ds->slave_mii_bus) {
2202                 mdiobus_unregister(priv->ds->slave_mii_bus);
2203                 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
2204                 mdiobus_free(priv->ds->slave_mii_bus);
2205         }
2206
2207         for (i = 0; i < priv->num_gphy_fw; i++)
2208                 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2209
2210         platform_set_drvdata(pdev, NULL);
2211
2212         return 0;
2213 }
2214
2215 static void gswip_shutdown(struct platform_device *pdev)
2216 {
2217         struct gswip_priv *priv = platform_get_drvdata(pdev);
2218
2219         if (!priv)
2220                 return;
2221
2222         dsa_switch_shutdown(priv->ds);
2223
2224         platform_set_drvdata(pdev, NULL);
2225 }
2226
2227 static const struct gswip_hw_info gswip_xrx200 = {
2228         .max_ports = 7,
2229         .cpu_port = 6,
2230         .ops = &gswip_xrx200_switch_ops,
2231 };
2232
2233 static const struct gswip_hw_info gswip_xrx300 = {
2234         .max_ports = 7,
2235         .cpu_port = 6,
2236         .ops = &gswip_xrx300_switch_ops,
2237 };
2238
2239 static const struct of_device_id gswip_of_match[] = {
2240         { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2241         { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2242         { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2243         {},
2244 };
2245 MODULE_DEVICE_TABLE(of, gswip_of_match);
2246
2247 static struct platform_driver gswip_driver = {
2248         .probe = gswip_probe,
2249         .remove = gswip_remove,
2250         .shutdown = gswip_shutdown,
2251         .driver = {
2252                 .name = "gswip",
2253                 .of_match_table = gswip_of_match,
2254         },
2255 };
2256
2257 module_platform_driver(gswip_driver);
2258
2259 /*(DEBLOBBED)*/
2260 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2261 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2262 MODULE_LICENSE("GPL v2");