1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/regmap.h>
9 #include <linux/mutex.h>
10 #include <linux/mii.h>
11 #include <linux/phy.h>
12 #include <linux/if_bridge.h>
13 #include <linux/etherdevice.h>
17 #define LAN9303_NUM_PORTS 3
19 /* 13.2 System Control and Status Registers
20 * Multiply register number by 4 to get address offset.
22 #define LAN9303_CHIP_REV 0x14
23 # define LAN9303_CHIP_ID 0x9303
24 #define LAN9303_IRQ_CFG 0x15
25 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
26 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
27 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
28 #define LAN9303_INT_STS 0x16
29 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
30 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
31 #define LAN9303_INT_EN 0x17
32 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
33 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
34 #define LAN9303_HW_CFG 0x1D
35 # define LAN9303_HW_CFG_READY BIT(27)
36 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
37 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
38 #define LAN9303_PMI_DATA 0x29
39 #define LAN9303_PMI_ACCESS 0x2A
40 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
41 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
42 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
43 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
44 #define LAN9303_MANUAL_FC_1 0x68
45 #define LAN9303_MANUAL_FC_2 0x69
46 #define LAN9303_MANUAL_FC_0 0x6a
47 #define LAN9303_SWITCH_CSR_DATA 0x6b
48 #define LAN9303_SWITCH_CSR_CMD 0x6c
49 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
50 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
51 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
52 #define LAN9303_VIRT_PHY_BASE 0x70
53 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
54 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
56 /*13.4 Switch Fabric Control and Status Registers
57 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
59 #define LAN9303_SW_DEV_ID 0x0000
60 #define LAN9303_SW_RESET 0x0001
61 #define LAN9303_SW_RESET_RESET BIT(0)
62 #define LAN9303_SW_IMR 0x0004
63 #define LAN9303_SW_IPR 0x0005
64 #define LAN9303_MAC_VER_ID_0 0x0400
65 #define LAN9303_MAC_RX_CFG_0 0x0401
66 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
67 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
68 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
69 #define LAN9303_MAC_RX_64_CNT_0 0x0411
70 #define LAN9303_MAC_RX_127_CNT_0 0x0412
71 #define LAN9303_MAC_RX_255_CNT_0 0x413
72 #define LAN9303_MAC_RX_511_CNT_0 0x0414
73 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
74 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
75 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
76 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
77 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
78 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
79 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
80 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
81 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
82 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
83 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
84 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
85 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
86 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
87 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
89 #define LAN9303_MAC_TX_CFG_0 0x0440
90 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
91 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
92 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
93 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
94 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
95 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
96 #define LAN9303_MAC_TX_64_CNT_0 0x0454
97 #define LAN9303_MAC_TX_127_CNT_0 0x0455
98 #define LAN9303_MAC_TX_255_CNT_0 0x0456
99 #define LAN9303_MAC_TX_511_CNT_0 0x0457
100 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
101 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
102 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
103 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
104 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
105 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
106 #define LAN9303_MAC_TX_LATECOL_0 0x045f
107 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
108 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
109 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
110 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
112 #define LAN9303_MAC_VER_ID_1 0x0800
113 #define LAN9303_MAC_RX_CFG_1 0x0801
114 #define LAN9303_MAC_TX_CFG_1 0x0840
115 #define LAN9303_MAC_VER_ID_2 0x0c00
116 #define LAN9303_MAC_RX_CFG_2 0x0c01
117 #define LAN9303_MAC_TX_CFG_2 0x0c40
118 #define LAN9303_SWE_ALR_CMD 0x1800
119 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
120 # define LAN9303_ALR_CMD_GET_FIRST BIT(1)
121 # define LAN9303_ALR_CMD_GET_NEXT BIT(0)
122 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
123 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
124 # define LAN9303_ALR_DAT1_VALID BIT(26)
125 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
126 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
127 # define LAN9303_ALR_DAT1_STATIC BIT(24)
128 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16
129 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
130 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
131 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
132 #define LAN9303_SWE_ALR_CMD_STS 0x1808
133 # define ALR_STS_MAKE_PEND BIT(0)
134 #define LAN9303_SWE_VLAN_CMD 0x180b
135 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
136 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
137 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
138 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
139 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
140 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
141 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
142 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
143 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
144 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
145 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
146 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
147 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
148 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
149 #define LAN9303_SWE_PORT_STATE 0x1843
150 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
151 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
152 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
153 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
154 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
155 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
156 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
157 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
158 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
159 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
160 #define LAN9303_SWE_PORT_MIRROR 0x1846
161 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
162 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
163 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
164 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
165 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
166 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
167 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
168 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
169 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
170 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
171 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
172 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
173 #define LAN9303_BM_CFG 0x1c00
174 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
175 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
176 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
177 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
179 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
181 /* the built-in PHYs are of type LAN911X */
182 #define MII_LAN911X_SPECIAL_MODES 0x12
183 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
185 static const struct regmap_range lan9303_valid_regs[] = {
186 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
187 regmap_reg_range(0x19, 0x19), /* endian test */
188 regmap_reg_range(0x1d, 0x1d), /* hardware config */
189 regmap_reg_range(0x23, 0x24), /* general purpose timer */
190 regmap_reg_range(0x27, 0x27), /* counter */
191 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
192 regmap_reg_range(0x68, 0x6a), /* flow control */
193 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
194 regmap_reg_range(0x6d, 0x6f), /* misc */
195 regmap_reg_range(0x70, 0x77), /* virtual phy */
196 regmap_reg_range(0x78, 0x7a), /* GPIO */
197 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
198 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
201 static const struct regmap_range lan9303_reserved_ranges[] = {
202 regmap_reg_range(0x00, 0x13),
203 regmap_reg_range(0x18, 0x18),
204 regmap_reg_range(0x1a, 0x1c),
205 regmap_reg_range(0x1e, 0x22),
206 regmap_reg_range(0x25, 0x26),
207 regmap_reg_range(0x28, 0x28),
208 regmap_reg_range(0x2b, 0x67),
209 regmap_reg_range(0x7b, 0x7b),
210 regmap_reg_range(0x7f, 0x7f),
211 regmap_reg_range(0xb8, 0xff),
214 const struct regmap_access_table lan9303_register_set = {
215 .yes_ranges = lan9303_valid_regs,
216 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
217 .no_ranges = lan9303_reserved_ranges,
218 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
220 EXPORT_SYMBOL(lan9303_register_set);
222 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
226 /* we can lose arbitration for the I2C case, because the device
227 * tries to detect and read an external EEPROM after reset and acts as
228 * a master on the shared I2C bus itself. This conflicts with our
229 * attempts to access the device as a slave at the same moment.
231 for (i = 0; i < 5; i++) {
232 ret = regmap_read(regmap, offset, reg);
243 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
247 for (i = 0; i < 25; i++) {
251 ret = lan9303_read(chip->regmap, offset, ®);
253 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
254 __func__, offset, ret);
259 usleep_range(1000, 2000);
265 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
270 if (regnum > MII_EXPANSION)
273 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
280 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
282 if (regnum > MII_EXPANSION)
285 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
288 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
290 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
291 LAN9303_PMI_ACCESS_MII_BUSY);
294 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
299 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
300 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
302 mutex_lock(&chip->indirect_mutex);
304 ret = lan9303_indirect_phy_wait_for_completion(chip);
308 /* start the MII read cycle */
309 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
313 ret = lan9303_indirect_phy_wait_for_completion(chip);
317 /* read the result of this operation */
318 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
322 mutex_unlock(&chip->indirect_mutex);
327 mutex_unlock(&chip->indirect_mutex);
331 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
337 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
338 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
339 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
341 mutex_lock(&chip->indirect_mutex);
343 ret = lan9303_indirect_phy_wait_for_completion(chip);
347 /* write the data first... */
348 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
352 /* ...then start the MII write cycle */
353 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
356 mutex_unlock(&chip->indirect_mutex);
360 const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
361 .phy_read = lan9303_indirect_phy_read,
362 .phy_write = lan9303_indirect_phy_write,
364 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
366 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
368 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
369 LAN9303_SWITCH_CSR_CMD_BUSY);
372 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
378 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
379 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
381 mutex_lock(&chip->indirect_mutex);
383 ret = lan9303_switch_wait_for_completion(chip);
387 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
389 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
394 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
396 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
400 mutex_unlock(&chip->indirect_mutex);
404 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
410 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
411 reg |= LAN9303_SWITCH_CSR_CMD_RW;
412 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
414 mutex_lock(&chip->indirect_mutex);
416 ret = lan9303_switch_wait_for_completion(chip);
421 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
423 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
428 ret = lan9303_switch_wait_for_completion(chip);
432 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
434 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
436 mutex_unlock(&chip->indirect_mutex);
440 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
446 ret = lan9303_read_switch_reg(chip, regnum, ®);
450 reg = (reg & ~mask) | val;
452 return lan9303_write_switch_reg(chip, regnum, reg);
455 static int lan9303_write_switch_port(struct lan9303 *chip, int port,
458 return lan9303_write_switch_reg(
459 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
462 static int lan9303_read_switch_port(struct lan9303 *chip, int port,
463 u16 regnum, u32 *val)
465 return lan9303_read_switch_reg(
466 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
469 static int lan9303_detect_phy_setup(struct lan9303 *chip)
473 /* Calculate chip->phy_addr_base:
474 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
475 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
476 * 'phy_addr_sel_strap' setting directly, so we need a test, which
477 * configuration is active:
478 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
479 * and the IDs are 0-1-2, else it contains something different from
480 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
481 * 0xffff is returned on MDIO read with no response.
483 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
485 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
489 chip->phy_addr_base = reg != 0 && reg != 0xffff;
491 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
492 chip->phy_addr_base ? "1-2-3" : "0-1-2");
497 /* Map ALR-port bits to port bitmap, and back */
498 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
499 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
501 /* Return pointer to first free ALR cache entry, return NULL if none */
502 static struct lan9303_alr_cache_entry *
503 lan9303_alr_cache_find_free(struct lan9303 *chip)
506 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
508 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
509 if (entr->port_map == 0)
515 /* Return pointer to ALR cache entry matching MAC address */
516 static struct lan9303_alr_cache_entry *
517 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
520 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
522 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
523 "ether_addr_equal require u16 alignment");
525 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
526 if (ether_addr_equal(entr->mac_addr, mac_addr))
532 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
536 for (i = 0; i < 25; i++) {
539 lan9303_read_switch_reg(chip, regno, ®);
542 usleep_range(1000, 2000);
548 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
550 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
551 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
552 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
553 LAN9303_ALR_CMD_MAKE_ENTRY);
554 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
555 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
560 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
561 int portmap, void *ctx);
563 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
567 mutex_lock(&chip->alr_mutex);
568 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
569 LAN9303_ALR_CMD_GET_FIRST);
570 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
572 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
574 int alrport, portmap;
576 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
577 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
578 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
581 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
582 LAN9303_ALR_DAT1_PORT_BITOFFS;
583 portmap = alrport_2_portmap[alrport];
585 ret = cb(chip, dat0, dat1, portmap, ctx);
589 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
590 LAN9303_ALR_CMD_GET_NEXT);
591 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
593 mutex_unlock(&chip->alr_mutex);
598 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
600 mac[0] = (dat0 >> 0) & 0xff;
601 mac[1] = (dat0 >> 8) & 0xff;
602 mac[2] = (dat0 >> 16) & 0xff;
603 mac[3] = (dat0 >> 24) & 0xff;
604 mac[4] = (dat1 >> 0) & 0xff;
605 mac[5] = (dat1 >> 8) & 0xff;
608 struct del_port_learned_ctx {
612 /* Clear learned (non-static) entry on given port */
613 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
614 u32 dat1, int portmap, void *ctx)
616 struct del_port_learned_ctx *del_ctx = ctx;
617 int port = del_ctx->port;
619 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
622 /* learned entries has only one port, we can just delete */
623 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
624 lan9303_alr_make_entry_raw(chip, dat0, dat1);
629 struct port_fdb_dump_ctx {
632 dsa_fdb_dump_cb_t *cb;
635 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
636 u32 dat1, int portmap, void *ctx)
638 struct port_fdb_dump_ctx *dump_ctx = ctx;
642 if ((BIT(dump_ctx->port) & portmap) == 0)
645 alr_reg_to_mac(dat0, dat1, mac);
646 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
647 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
650 /* Set a static ALR entry. Delete entry if port_map is zero */
651 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
652 u8 port_map, bool stp_override)
654 u32 dat0, dat1, alr_port;
656 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
657 dat1 = LAN9303_ALR_DAT1_STATIC;
659 dat1 |= LAN9303_ALR_DAT1_VALID;
660 /* otherwise no ports: delete entry */
662 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
664 alr_port = portmap_2_alrport[port_map & 7];
665 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
666 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
669 dat0 |= (mac[0] << 0);
670 dat0 |= (mac[1] << 8);
671 dat0 |= (mac[2] << 16);
672 dat0 |= (mac[3] << 24);
674 dat1 |= (mac[4] << 0);
675 dat1 |= (mac[5] << 8);
677 lan9303_alr_make_entry_raw(chip, dat0, dat1);
680 /* Add port to static ALR entry, create new static entry if needed */
681 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
684 struct lan9303_alr_cache_entry *entr;
686 mutex_lock(&chip->alr_mutex);
687 entr = lan9303_alr_cache_find_mac(chip, mac);
688 if (!entr) { /*New entry */
689 entr = lan9303_alr_cache_find_free(chip);
691 mutex_unlock(&chip->alr_mutex);
694 ether_addr_copy(entr->mac_addr, mac);
696 entr->port_map |= BIT(port);
697 entr->stp_override = stp_override;
698 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
699 mutex_unlock(&chip->alr_mutex);
704 /* Delete static port from ALR entry, delete entry if last port */
705 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
707 struct lan9303_alr_cache_entry *entr;
709 mutex_lock(&chip->alr_mutex);
710 entr = lan9303_alr_cache_find_mac(chip, mac);
712 goto out; /* no static entry found */
714 entr->port_map &= ~BIT(port);
715 if (entr->port_map == 0) /* zero means its free again */
716 eth_zero_addr(entr->mac_addr);
717 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
720 mutex_unlock(&chip->alr_mutex);
724 static int lan9303_disable_processing_port(struct lan9303 *chip,
729 /* disable RX, but keep register reset default values else */
730 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
731 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
735 /* disable TX, but keep register reset default values else */
736 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
737 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
738 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
741 static int lan9303_enable_processing_port(struct lan9303 *chip,
746 /* enable RX and keep register reset default values else */
747 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
748 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
749 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
753 /* enable TX and keep register reset default values else */
754 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
755 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
756 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
757 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
760 /* forward special tagged packets from port 0 to port 1 *or* port 2 */
761 static int lan9303_setup_tagging(struct lan9303 *chip)
765 /* enable defining the destination port via special VLAN tagging
768 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
769 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
773 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
774 * able to discover their source port
776 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
777 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
780 /* We want a special working switch:
781 * - do not forward packets between port 1 and 2
782 * - forward everything from port 1 to port 0
783 * - forward everything from port 2 to port 0
785 static int lan9303_separate_ports(struct lan9303 *chip)
789 lan9303_alr_del_port(chip, eth_stp_addr, 0);
790 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
791 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
792 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
793 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
794 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
795 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
799 /* prevent port 1 and 2 from forwarding packets by their own */
800 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
801 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
802 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
803 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
806 static void lan9303_bridge_ports(struct lan9303 *chip)
808 /* ports bridged: remove mirroring */
809 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
810 LAN9303_SWE_PORT_MIRROR_DISABLED);
812 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
813 chip->swe_port_state);
814 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
817 static void lan9303_handle_reset(struct lan9303 *chip)
819 if (!chip->reset_gpio)
822 if (chip->reset_duration != 0)
823 msleep(chip->reset_duration);
825 /* release (deassert) reset and activate the device */
826 gpiod_set_value_cansleep(chip->reset_gpio, 0);
829 /* stop processing packets for all ports */
830 static int lan9303_disable_processing(struct lan9303 *chip)
834 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
835 int ret = lan9303_disable_processing_port(chip, p);
844 static int lan9303_check_device(struct lan9303 *chip)
849 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
851 dev_err(chip->dev, "failed to read chip revision register: %d\n",
853 if (!chip->reset_gpio) {
855 "hint: maybe failed due to missing reset GPIO\n");
860 if ((reg >> 16) != LAN9303_CHIP_ID) {
861 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
866 /* The default state of the LAN9303 device is to forward packets between
867 * all ports (if not configured differently by an external EEPROM).
868 * The initial state of a DSA device must be forwarding packets only
869 * between the external and the internal ports and no forwarding
870 * between the external ports. In preparation we stop packet handling
871 * at all for now until the LAN9303 device is re-programmed accordingly.
873 ret = lan9303_disable_processing(chip);
875 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
877 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
879 ret = lan9303_detect_phy_setup(chip);
882 "failed to discover phy bootstrap setup: %d\n", ret);
889 /* ---------------------------- DSA -----------------------------------*/
891 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
893 enum dsa_tag_protocol mp)
895 return DSA_TAG_PROTO_LAN9303;
898 static int lan9303_setup(struct dsa_switch *ds)
900 struct lan9303 *chip = ds->priv;
903 /* Make sure that port 0 is the cpu port */
904 if (!dsa_is_cpu_port(ds, 0)) {
905 dev_err(chip->dev, "port 0 is not the CPU port\n");
909 ret = lan9303_setup_tagging(chip);
911 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
913 ret = lan9303_separate_ports(chip);
915 dev_err(chip->dev, "failed to separate ports %d\n", ret);
917 ret = lan9303_enable_processing_port(chip, 0);
919 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
921 /* Trap IGMP to port 0 */
922 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
923 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
924 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
925 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
926 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
928 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
933 struct lan9303_mib_desc {
934 unsigned int offset; /* offset of first MAC */
938 static const struct lan9303_mib_desc lan9303_mib[] = {
939 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
940 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
941 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
942 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
943 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
944 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
945 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
946 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
947 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
948 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
949 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
950 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
951 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
952 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
953 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
954 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
955 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
956 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
957 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
958 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
959 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
960 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
961 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
962 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
963 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
964 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
965 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
966 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
967 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
968 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
969 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
970 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
971 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
972 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
973 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
974 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
975 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
978 static void lan9303_get_strings(struct dsa_switch *ds, int port,
979 u32 stringset, uint8_t *data)
983 if (stringset != ETH_SS_STATS)
986 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
987 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
992 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
995 struct lan9303 *chip = ds->priv;
998 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1002 ret = lan9303_read_switch_port(
1003 chip, port, lan9303_mib[u].offset, ®);
1006 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1007 port, lan9303_mib[u].offset);
1012 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
1014 if (sset != ETH_SS_STATS)
1017 return ARRAY_SIZE(lan9303_mib);
1020 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
1022 struct lan9303 *chip = ds->priv;
1023 int phy_base = chip->phy_addr_base;
1025 if (phy == phy_base)
1026 return lan9303_virt_phy_reg_read(chip, regnum);
1027 if (phy > phy_base + 2)
1030 return chip->ops->phy_read(chip, phy, regnum);
1033 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
1036 struct lan9303 *chip = ds->priv;
1037 int phy_base = chip->phy_addr_base;
1039 if (phy == phy_base)
1040 return lan9303_virt_phy_reg_write(chip, regnum, val);
1041 if (phy > phy_base + 2)
1044 return chip->ops->phy_write(chip, phy, regnum, val);
1047 static void lan9303_adjust_link(struct dsa_switch *ds, int port,
1048 struct phy_device *phydev)
1050 struct lan9303 *chip = ds->priv;
1053 if (!phy_is_pseudo_fixed_link(phydev))
1056 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1058 ctl &= ~BMCR_ANENABLE;
1060 if (phydev->speed == SPEED_100)
1061 ctl |= BMCR_SPEED100;
1062 else if (phydev->speed == SPEED_10)
1063 ctl &= ~BMCR_SPEED100;
1065 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed);
1067 if (phydev->duplex == DUPLEX_FULL)
1068 ctl |= BMCR_FULLDPLX;
1070 ctl &= ~BMCR_FULLDPLX;
1072 lan9303_phy_write(ds, port, MII_BMCR, ctl);
1074 if (port == chip->phy_addr_base) {
1075 /* Virtual Phy: Remove Turbo 200Mbit mode */
1076 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
1078 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO;
1079 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ctl);
1083 static int lan9303_port_enable(struct dsa_switch *ds, int port,
1084 struct phy_device *phy)
1086 struct lan9303 *chip = ds->priv;
1088 if (!dsa_is_user_port(ds, port))
1091 return lan9303_enable_processing_port(chip, port);
1094 static void lan9303_port_disable(struct dsa_switch *ds, int port)
1096 struct lan9303 *chip = ds->priv;
1098 if (!dsa_is_user_port(ds, port))
1101 lan9303_disable_processing_port(chip, port);
1102 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
1105 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1106 struct net_device *br)
1108 struct lan9303 *chip = ds->priv;
1110 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1111 if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) {
1112 lan9303_bridge_ports(chip);
1113 chip->is_bridged = true; /* unleash stp_state_set() */
1119 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1120 struct net_device *br)
1122 struct lan9303 *chip = ds->priv;
1124 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1125 if (chip->is_bridged) {
1126 lan9303_separate_ports(chip);
1127 chip->is_bridged = false;
1131 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1134 int portmask, portstate;
1135 struct lan9303 *chip = ds->priv;
1137 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1138 __func__, port, state);
1141 case BR_STATE_DISABLED:
1142 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1144 case BR_STATE_BLOCKING:
1145 case BR_STATE_LISTENING:
1146 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1148 case BR_STATE_LEARNING:
1149 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1151 case BR_STATE_FORWARDING:
1152 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1155 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1156 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1160 portmask = 0x3 << (port * 2);
1161 portstate <<= (port * 2);
1163 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1165 if (chip->is_bridged)
1166 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1167 chip->swe_port_state);
1168 /* else: touching SWE_PORT_STATE would break port separation */
1171 static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1173 struct lan9303 *chip = ds->priv;
1174 struct del_port_learned_ctx del_ctx = {
1178 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1179 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1182 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1183 const unsigned char *addr, u16 vid)
1185 struct lan9303 *chip = ds->priv;
1187 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1191 return lan9303_alr_add_port(chip, addr, port, false);
1194 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1195 const unsigned char *addr, u16 vid)
1198 struct lan9303 *chip = ds->priv;
1200 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1203 lan9303_alr_del_port(chip, addr, port);
1208 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1209 dsa_fdb_dump_cb_t *cb, void *data)
1211 struct lan9303 *chip = ds->priv;
1212 struct port_fdb_dump_ctx dump_ctx = {
1218 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1219 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1222 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1223 const struct switchdev_obj_port_mdb *mdb)
1225 struct lan9303 *chip = ds->priv;
1227 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1231 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1233 if (!lan9303_alr_cache_find_free(chip))
1239 static void lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1240 const struct switchdev_obj_port_mdb *mdb)
1242 struct lan9303 *chip = ds->priv;
1244 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1246 lan9303_alr_add_port(chip, mdb->addr, port, false);
1249 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1250 const struct switchdev_obj_port_mdb *mdb)
1252 struct lan9303 *chip = ds->priv;
1254 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1258 lan9303_alr_del_port(chip, mdb->addr, port);
1263 static const struct dsa_switch_ops lan9303_switch_ops = {
1264 .get_tag_protocol = lan9303_get_tag_protocol,
1265 .setup = lan9303_setup,
1266 .get_strings = lan9303_get_strings,
1267 .phy_read = lan9303_phy_read,
1268 .phy_write = lan9303_phy_write,
1269 .adjust_link = lan9303_adjust_link,
1270 .get_ethtool_stats = lan9303_get_ethtool_stats,
1271 .get_sset_count = lan9303_get_sset_count,
1272 .port_enable = lan9303_port_enable,
1273 .port_disable = lan9303_port_disable,
1274 .port_bridge_join = lan9303_port_bridge_join,
1275 .port_bridge_leave = lan9303_port_bridge_leave,
1276 .port_stp_state_set = lan9303_port_stp_state_set,
1277 .port_fast_age = lan9303_port_fast_age,
1278 .port_fdb_add = lan9303_port_fdb_add,
1279 .port_fdb_del = lan9303_port_fdb_del,
1280 .port_fdb_dump = lan9303_port_fdb_dump,
1281 .port_mdb_prepare = lan9303_port_mdb_prepare,
1282 .port_mdb_add = lan9303_port_mdb_add,
1283 .port_mdb_del = lan9303_port_mdb_del,
1286 static int lan9303_register_switch(struct lan9303 *chip)
1290 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL);
1294 chip->ds->dev = chip->dev;
1295 chip->ds->num_ports = LAN9303_NUM_PORTS;
1296 chip->ds->priv = chip;
1297 chip->ds->ops = &lan9303_switch_ops;
1298 base = chip->phy_addr_base;
1299 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
1301 return dsa_register_switch(chip->ds);
1304 static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1305 struct device_node *np)
1307 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1309 if (IS_ERR(chip->reset_gpio))
1310 return PTR_ERR(chip->reset_gpio);
1312 if (!chip->reset_gpio) {
1313 dev_dbg(chip->dev, "No reset GPIO defined\n");
1317 chip->reset_duration = 200;
1320 of_property_read_u32(np, "reset-duration",
1321 &chip->reset_duration);
1323 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1326 /* A sane reset duration should not be longer than 1s */
1327 if (chip->reset_duration > 1000)
1328 chip->reset_duration = 1000;
1333 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1337 mutex_init(&chip->indirect_mutex);
1338 mutex_init(&chip->alr_mutex);
1340 ret = lan9303_probe_reset_gpio(chip, np);
1344 lan9303_handle_reset(chip);
1346 ret = lan9303_check_device(chip);
1350 ret = lan9303_register_switch(chip);
1352 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1358 EXPORT_SYMBOL(lan9303_probe);
1360 int lan9303_remove(struct lan9303 *chip)
1364 rc = lan9303_disable_processing(chip);
1366 dev_warn(chip->dev, "shutting down failed\n");
1368 dsa_unregister_switch(chip->ds);
1370 /* assert reset to the whole device to prevent it from doing anything */
1371 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1372 gpiod_unexport(chip->reset_gpio);
1376 EXPORT_SYMBOL(lan9303_remove);
1378 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1379 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1380 MODULE_LICENSE("GPL v2");