2 * Broadcom Starfighter 2 switch register defines
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #ifndef __BCM_SF2_REGS_H
12 #define __BCM_SF2_REGS_H
14 /* Register set relative to 'REG' */
16 enum bcm_sf2_reg_offs {
33 /* Relative to REG_SWITCH_CNTRL */
34 #define MDIO_MASTER_SEL (1 << 0)
36 /* Relative to REG_SWITCH_REVISION */
37 #define SF2_REV_MASK 0xffff
38 #define SWITCH_TOP_REV_SHIFT 16
39 #define SWITCH_TOP_REV_MASK 0xffff
41 /* Relative to REG_PHY_REVISION */
42 #define PHY_REVISION_MASK 0xffff
44 /* Relative to REG_SPHY_CNTRL */
45 #define IDDQ_BIAS (1 << 0)
46 #define EXT_PWR_DOWN (1 << 1)
47 #define FORCE_DLL_EN (1 << 2)
48 #define IDDQ_GLOBAL_PWR (1 << 3)
49 #define CK25_DIS (1 << 4)
50 #define PHY_RESET (1 << 5)
51 #define PHY_PHYAD_SHIFT 8
52 #define PHY_PHYAD_MASK 0x1F
54 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
56 /* Relative to REG_RGMII_CNTRL */
57 #define RGMII_MODE_EN (1 << 0)
58 #define ID_MODE_DIS (1 << 1)
59 #define PORT_MODE_SHIFT 2
60 #define INT_EPHY (0 << PORT_MODE_SHIFT)
61 #define INT_GPHY (1 << PORT_MODE_SHIFT)
62 #define EXT_EPHY (2 << PORT_MODE_SHIFT)
63 #define EXT_GPHY (3 << PORT_MODE_SHIFT)
64 #define EXT_REVMII (4 << PORT_MODE_SHIFT)
65 #define PORT_MODE_MASK 0x7
66 #define RVMII_REF_SEL (1 << 5)
67 #define RX_PAUSE_EN (1 << 6)
68 #define TX_PAUSE_EN (1 << 7)
69 #define TX_CLK_STOP_EN (1 << 8)
70 #define LPI_COUNT_SHIFT 9
71 #define LPI_COUNT_MASK 0x3F
73 #define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
75 #define SPDLNK_SRC_SEL (1 << 24)
77 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
78 #define INTRL2_CPU_STATUS 0x00
79 #define INTRL2_CPU_SET 0x04
80 #define INTRL2_CPU_CLEAR 0x08
81 #define INTRL2_CPU_MASK_STATUS 0x0c
82 #define INTRL2_CPU_MASK_SET 0x10
83 #define INTRL2_CPU_MASK_CLEAR 0x14
85 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
86 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
87 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
88 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
89 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
90 #define P_GPHY_IRQ(x) (1 << (4 + (x)))
92 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
93 P_LINK_DOWN_IRQ((x)) | \
94 P_ENERGY_ON_IRQ((x)) | \
95 P_ENERGY_OFF_IRQ((x)) | \
98 /* INTRL2_0 interrupt sources */
100 #define MEM_DOUBLE_IRQ (1 << 5)
101 #define EEE_LPI_IRQ (1 << 6)
102 #define P5_CPU_WAKE_IRQ (1 << 7)
103 #define P8_CPU_WAKE_IRQ (1 << 8)
104 #define P7_CPU_WAKE_IRQ (1 << 9)
105 #define IEEE1588_IRQ (1 << 10)
106 #define MDIO_ERR_IRQ (1 << 11)
107 #define MDIO_DONE_IRQ (1 << 12)
108 #define GISB_ERR_IRQ (1 << 13)
109 #define UBUS_ERR_IRQ (1 << 14)
110 #define FAILOVER_ON_IRQ (1 << 15)
111 #define FAILOVER_OFF_IRQ (1 << 16)
112 #define TCAM_SOFT_ERR_IRQ (1 << 17)
114 /* INTRL2_1 interrupt sources */
116 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
118 /* Register set relative to 'CORE' */
119 #define CORE_G_PCTL_PORT0 0x00000
120 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
121 #define CORE_IMP_CTL 0x00020
122 #define RX_DIS (1 << 0)
123 #define TX_DIS (1 << 1)
124 #define RX_BCST_EN (1 << 2)
125 #define RX_MCST_EN (1 << 3)
126 #define RX_UCST_EN (1 << 4)
128 #define CORE_SWMODE 0x0002c
129 #define SW_FWDG_MODE (1 << 0)
130 #define SW_FWDG_EN (1 << 1)
131 #define RTRY_LMT_DIS (1 << 2)
133 #define CORE_STS_OVERRIDE_IMP 0x00038
134 #define GMII_SPEED_UP_2G (1 << 6)
135 #define MII_SW_OR (1 << 7)
137 /* Alternate layout for e.g: 7278 */
138 #define CORE_STS_OVERRIDE_IMP2 0x39040
140 #define CORE_NEW_CTRL 0x00084
141 #define IP_MC (1 << 0)
142 #define OUTRANGEERR_DISCARD (1 << 1)
143 #define INRANGEERR_DISCARD (1 << 2)
144 #define CABLE_DIAG_LEN (1 << 3)
145 #define OVERRIDE_AUTO_PD_WAR (1 << 4)
146 #define EN_AUTO_PD_WAR (1 << 5)
147 #define UC_FWD_EN (1 << 6)
148 #define MC_FWD_EN (1 << 7)
150 #define CORE_SWITCH_CTRL 0x00088
151 #define MII_DUMB_FWDG_EN (1 << 6)
153 #define CORE_DIS_LEARN 0x000f0
155 #define CORE_SFT_LRN_CTRL 0x000f8
156 #define SW_LEARN_CNTL(x) (1 << (x))
158 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
159 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
160 #define LINK_STS (1 << 0)
161 #define DUPLX_MODE (1 << 1)
162 #define SPEED_SHIFT 2
163 #define SPEED_MASK 0x3
164 #define RXFLOW_CNTL (1 << 4)
165 #define TXFLOW_CNTL (1 << 5)
166 #define SW_OVERRIDE (1 << 6)
168 #define CORE_WATCHDOG_CTRL 0x001e4
169 #define SOFTWARE_RESET (1 << 7)
170 #define EN_CHIP_RST (1 << 6)
171 #define EN_SW_RESET (1 << 4)
173 #define CORE_FAST_AGE_CTRL 0x00220
174 #define EN_FAST_AGE_STATIC (1 << 0)
175 #define EN_AGE_DYNAMIC (1 << 1)
176 #define EN_AGE_PORT (1 << 2)
177 #define EN_AGE_VLAN (1 << 3)
178 #define EN_AGE_SPT (1 << 4)
179 #define EN_AGE_MCAST (1 << 5)
180 #define FAST_AGE_STR_DONE (1 << 7)
182 #define CORE_FAST_AGE_PORT 0x00224
183 #define AGE_PORT_MASK 0xf
185 #define CORE_FAST_AGE_VID 0x00228
186 #define AGE_VID_MASK 0x3fff
188 #define CORE_LNKSTS 0x00400
189 #define LNK_STS_MASK 0x1ff
191 #define CORE_SPDSTS 0x00410
194 #define SPDSTS_1000 2
195 #define SPDSTS_SHIFT 2
196 #define SPDSTS_MASK 0x3
198 #define CORE_DUPSTS 0x00420
199 #define CORE_DUPSTS_MASK 0x1ff
201 #define CORE_PAUSESTS 0x00428
202 #define PAUSESTS_TX_PAUSE_SHIFT 9
204 #define CORE_GMNCFGCFG 0x0800
205 #define RST_MIB_CNT (1 << 0)
206 #define RXBPDU_EN (1 << 1)
208 #define CORE_IMP0_PRT_ID 0x0804
210 #define CORE_BRCM_HDR_CTRL 0x0080c
211 #define BRCM_HDR_EN_P8 (1 << 0)
212 #define BRCM_HDR_EN_P5 (1 << 1)
213 #define BRCM_HDR_EN_P7 (1 << 2)
215 #define CORE_RST_MIB_CNT_EN 0x0950
217 #define CORE_BRCM_HDR_RX_DIS 0x0980
218 #define CORE_BRCM_HDR_TX_DIS 0x0988
220 #define CORE_ARLA_VTBL_RWCTRL 0x1600
221 #define ARLA_VTBL_CMD_WRITE 0
222 #define ARLA_VTBL_CMD_READ 1
223 #define ARLA_VTBL_CMD_CLEAR 2
224 #define ARLA_VTBL_STDN (1 << 7)
226 #define CORE_ARLA_VTBL_ADDR 0x1604
227 #define VTBL_ADDR_INDEX_MASK 0xfff
229 #define CORE_ARLA_VTBL_ENTRY 0x160c
230 #define FWD_MAP_MASK 0x1ff
231 #define UNTAG_MAP_MASK 0x1ff
232 #define UNTAG_MAP_SHIFT 9
233 #define MSTP_INDEX_MASK 0x7
234 #define MSTP_INDEX_SHIFT 18
235 #define FWD_MODE (1 << 21)
237 #define CORE_MEM_PSM_VDD_CTRL 0x2380
238 #define P_TXQ_PSM_VDD_SHIFT 2
239 #define P_TXQ_PSM_VDD_MASK 0x3
240 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
241 ((x) * P_TXQ_PSM_VDD_SHIFT))
243 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
244 #define PRT_TO_QID_MASK 0x3
245 #define PRT_TO_QID_SHIFT 3
247 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
248 #define PORT_VLAN_CTRL_MASK 0x1ff
250 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
255 #define CORE_JOIN_ALL_VLAN_EN 0xd140
257 #define CORE_EEE_EN_CTRL 0x24800
258 #define CORE_EEE_LPI_INDICATE 0x24810
260 #define CORE_CFP_ACC 0x28000
261 #define OP_STR_DONE (1 << 0)
262 #define OP_SEL_SHIFT 1
263 #define OP_SEL_READ (1 << OP_SEL_SHIFT)
264 #define OP_SEL_WRITE (2 << OP_SEL_SHIFT)
265 #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT)
266 #define OP_SEL_MASK (7 << OP_SEL_SHIFT)
267 #define CFP_RAM_CLEAR (1 << 4)
268 #define RAM_SEL_SHIFT 10
269 #define TCAM_SEL (1 << RAM_SEL_SHIFT)
270 #define ACT_POL_RAM (2 << RAM_SEL_SHIFT)
271 #define RATE_METER_RAM (4 << RAM_SEL_SHIFT)
272 #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT)
273 #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT)
274 #define RED_STAT_RAM (24 << RAM_SEL_SHIFT)
275 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
276 #define TCAM_RESET (1 << 15)
277 #define XCESS_ADDR_SHIFT 16
278 #define XCESS_ADDR_MASK 0xff
279 #define SEARCH_STS (1 << 27)
280 #define RD_STS_SHIFT 28
281 #define RD_STS_TCAM (1 << RD_STS_SHIFT)
282 #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT)
283 #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT)
284 #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT)
286 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
288 #define CORE_CFP_DATA_PORT_0 0x28040
289 #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \
293 #define L3_FRAMING_SHIFT 24
294 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
295 #define IPPROTO_SHIFT 8
296 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
297 #define IP_FRAG (1 << 7)
300 #define SLICE_VALID 3
301 #define SLICE_NUM_SHIFT 2
302 #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT)
304 #define CORE_CFP_MASK_PORT_0 0x280c0
306 #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \
309 #define CORE_ACT_POL_DATA0 0x28140
310 #define VLAN_BYP (1 << 0)
311 #define EAP_BYP (1 << 1)
312 #define STP_BYP (1 << 2)
313 #define REASON_CODE_SHIFT 3
314 #define REASON_CODE_MASK 0x3f
315 #define LOOP_BK_EN (1 << 9)
316 #define NEW_TC_SHIFT 10
317 #define NEW_TC_MASK 0x7
318 #define CHANGE_TC (1 << 13)
319 #define DST_MAP_IB_SHIFT 14
320 #define DST_MAP_IB_MASK 0x1ff
321 #define CHANGE_FWRD_MAP_IB_SHIFT 24
322 #define CHANGE_FWRD_MAP_IB_MASK 0x3
323 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
324 #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT)
325 #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT)
326 #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT)
327 #define NEW_DSCP_IB_SHIFT 26
328 #define NEW_DSCP_IB_MASK 0x3f
330 #define CORE_ACT_POL_DATA1 0x28150
331 #define CHANGE_DSCP_IB (1 << 0)
332 #define DST_MAP_OB_SHIFT 1
333 #define DST_MAP_OB_MASK 0x3ff
334 #define CHANGE_FWRD_MAP_OB_SHIT 11
335 #define CHANGE_FWRD_MAP_OB_MASK 0x3
336 #define NEW_DSCP_OB_SHIFT 13
337 #define NEW_DSCP_OB_MASK 0x3f
338 #define CHANGE_DSCP_OB (1 << 19)
339 #define CHAIN_ID_SHIFT 20
340 #define CHAIN_ID_MASK 0xff
341 #define CHANGE_COLOR (1 << 28)
342 #define NEW_COLOR_SHIFT 29
343 #define NEW_COLOR_MASK 0x3
344 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
345 #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT)
346 #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT)
347 #define RED_DEFAULT (1 << 31)
349 #define CORE_ACT_POL_DATA2 0x28160
350 #define MAC_LIMIT_BYPASS (1 << 0)
351 #define CHANGE_TC_O (1 << 1)
352 #define NEW_TC_O_SHIFT 2
353 #define NEW_TC_O_MASK 0x7
354 #define SPCP_RMK_DISABLE (1 << 5)
355 #define CPCP_RMK_DISABLE (1 << 6)
356 #define DEI_RMK_DISABLE (1 << 7)
358 #define CORE_RATE_METER0 0x28180
359 #define COLOR_MODE (1 << 0)
360 #define POLICER_ACTION (1 << 1)
361 #define COUPLING_FLAG (1 << 2)
362 #define POLICER_MODE_SHIFT 3
363 #define POLICER_MODE_MASK 0x3
364 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
365 #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT)
366 #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT)
367 #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT)
369 #define CORE_RATE_METER1 0x28190
370 #define EIR_TK_BKT_MASK 0x7fffff
372 #define CORE_RATE_METER2 0x281a0
373 #define EIR_BKT_SIZE_MASK 0xfffff
375 #define CORE_RATE_METER3 0x281b0
376 #define EIR_REF_CNT_MASK 0x7ffff
378 #define CORE_RATE_METER4 0x281c0
379 #define CIR_TK_BKT_MASK 0x7fffff
381 #define CORE_RATE_METER5 0x281d0
382 #define CIR_BKT_SIZE_MASK 0xfffff
384 #define CORE_RATE_METER6 0x281e0
385 #define CIR_REF_CNT_MASK 0x7ffff
387 #define CORE_CFP_CTL_REG 0x28400
388 #define CFP_EN_MAP_MASK 0x1ff
390 /* IPv4 slices, 3 of them */
391 #define CORE_UDF_0_A_0_8_PORT_0 0x28440
392 #define CFG_UDF_OFFSET_MASK 0x1f
393 #define CFG_UDF_OFFSET_BASE_SHIFT 5
394 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
395 #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT)
396 #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT)
398 /* Number of slices for IPv4, IPv6 and non-IP */
399 #define UDF_NUM_SLICES 9
401 /* Spacing between different slices */
402 #define UDF_SLICE_OFFSET 0x40
404 #define CFP_NUM_RULES 256
406 /* Number of egress queues per port */
407 #define SF2_NUM_EGRESS_QUEUES 8
409 #endif /* __BCM_SF2_REGS_H */