1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Broadcom Starfighter 2 switch register defines
5 * Copyright (C) 2014, Broadcom Corporation
7 #ifndef __BCM_SF2_REGS_H
8 #define __BCM_SF2_REGS_H
10 /* Register set relative to 'REG' */
12 enum bcm_sf2_reg_offs {
31 /* Relative to REG_SWITCH_CNTRL */
32 #define MDIO_MASTER_SEL (1 << 0)
34 /* Relative to REG_SWITCH_REVISION */
35 #define SF2_REV_MASK 0xffff
36 #define SWITCH_TOP_REV_SHIFT 16
37 #define SWITCH_TOP_REV_MASK 0xffff
39 /* Relative to REG_PHY_REVISION */
40 #define PHY_REVISION_MASK 0xffff
42 /* Relative to REG_SPHY_CNTRL */
43 #define IDDQ_BIAS (1 << 0)
44 #define EXT_PWR_DOWN (1 << 1)
45 #define FORCE_DLL_EN (1 << 2)
46 #define IDDQ_GLOBAL_PWR (1 << 3)
47 #define CK25_DIS (1 << 4)
48 #define PHY_RESET (1 << 5)
49 #define PHY_PHYAD_SHIFT 8
50 #define PHY_PHYAD_MASK 0x1F
52 /* Relative to REG_CROSSBAR */
53 #define CROSSBAR_BCM4908_INT_P7 0
54 #define CROSSBAR_BCM4908_INT_RUNNER 1
55 #define CROSSBAR_BCM4908_EXT_SERDES 0
56 #define CROSSBAR_BCM4908_EXT_GPHY4 1
57 #define CROSSBAR_BCM4908_EXT_RGMII 2
59 /* Relative to REG_RGMII_CNTRL */
60 #define RGMII_MODE_EN (1 << 0)
61 #define ID_MODE_DIS (1 << 1)
62 #define PORT_MODE_SHIFT 2
63 #define INT_EPHY (0 << PORT_MODE_SHIFT)
64 #define INT_GPHY (1 << PORT_MODE_SHIFT)
65 #define EXT_EPHY (2 << PORT_MODE_SHIFT)
66 #define EXT_GPHY (3 << PORT_MODE_SHIFT)
67 #define EXT_REVMII (4 << PORT_MODE_SHIFT)
68 #define PORT_MODE_MASK 0x7
69 #define RVMII_REF_SEL (1 << 5)
70 #define RX_PAUSE_EN (1 << 6)
71 #define TX_PAUSE_EN (1 << 7)
72 #define TX_CLK_STOP_EN (1 << 8)
73 #define LPI_COUNT_SHIFT 9
74 #define LPI_COUNT_MASK 0x3F
76 #define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
78 #define SPDLNK_SRC_SEL (1 << 24)
80 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
81 #define INTRL2_CPU_STATUS 0x00
82 #define INTRL2_CPU_SET 0x04
83 #define INTRL2_CPU_CLEAR 0x08
84 #define INTRL2_CPU_MASK_STATUS 0x0c
85 #define INTRL2_CPU_MASK_SET 0x10
86 #define INTRL2_CPU_MASK_CLEAR 0x14
88 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
89 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
90 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
91 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
92 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
93 #define P_GPHY_IRQ(x) (1 << (4 + (x)))
95 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
96 P_LINK_DOWN_IRQ((x)) | \
97 P_ENERGY_ON_IRQ((x)) | \
98 P_ENERGY_OFF_IRQ((x)) | \
101 /* INTRL2_0 interrupt sources */
103 #define MEM_DOUBLE_IRQ (1 << 5)
104 #define EEE_LPI_IRQ (1 << 6)
105 #define P5_CPU_WAKE_IRQ (1 << 7)
106 #define P8_CPU_WAKE_IRQ (1 << 8)
107 #define P7_CPU_WAKE_IRQ (1 << 9)
108 #define IEEE1588_IRQ (1 << 10)
109 #define MDIO_ERR_IRQ (1 << 11)
110 #define MDIO_DONE_IRQ (1 << 12)
111 #define GISB_ERR_IRQ (1 << 13)
112 #define UBUS_ERR_IRQ (1 << 14)
113 #define FAILOVER_ON_IRQ (1 << 15)
114 #define FAILOVER_OFF_IRQ (1 << 16)
115 #define TCAM_SOFT_ERR_IRQ (1 << 17)
117 /* INTRL2_1 interrupt sources */
119 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
121 /* Register set relative to 'ACB' */
122 #define ACB_CONTROL 0x00
123 #define ACB_EN (1 << 0)
124 #define ACB_ALGORITHM (1 << 1)
125 #define ACB_FLUSH_SHIFT 2
126 #define ACB_FLUSH_MASK 0x3
128 #define ACB_QUEUE_0_CFG 0x08
129 #define XOFF_THRESHOLD_MASK 0x7ff
130 #define XON_EN (1 << 11)
131 #define TOTAL_XOFF_THRESHOLD_SHIFT 12
132 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
133 #define TOTAL_XOFF_EN (1 << 23)
134 #define TOTAL_XON_EN (1 << 24)
135 #define PKTLEN_SHIFT 25
136 #define PKTLEN_MASK 0x3f
137 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
139 /* Register set relative to 'CORE' */
140 #define CORE_G_PCTL_PORT0 0x00000
141 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
142 #define CORE_IMP_CTL 0x00020
143 #define RX_DIS (1 << 0)
144 #define TX_DIS (1 << 1)
145 #define RX_BCST_EN (1 << 2)
146 #define RX_MCST_EN (1 << 3)
147 #define RX_UCST_EN (1 << 4)
149 #define CORE_SWMODE 0x0002c
150 #define SW_FWDG_MODE (1 << 0)
151 #define SW_FWDG_EN (1 << 1)
152 #define RTRY_LMT_DIS (1 << 2)
154 #define CORE_STS_OVERRIDE_IMP 0x00038
155 #define GMII_SPEED_UP_2G (1 << 6)
156 #define MII_SW_OR (1 << 7)
158 /* Alternate layout for e.g: 7278 */
159 #define CORE_STS_OVERRIDE_IMP2 0x39040
161 #define CORE_NEW_CTRL 0x00084
162 #define IP_MC (1 << 0)
163 #define OUTRANGEERR_DISCARD (1 << 1)
164 #define INRANGEERR_DISCARD (1 << 2)
165 #define CABLE_DIAG_LEN (1 << 3)
166 #define OVERRIDE_AUTO_PD_WAR (1 << 4)
167 #define EN_AUTO_PD_WAR (1 << 5)
168 #define UC_FWD_EN (1 << 6)
169 #define MC_FWD_EN (1 << 7)
171 #define CORE_SWITCH_CTRL 0x00088
172 #define MII_DUMB_FWDG_EN (1 << 6)
174 #define CORE_DIS_LEARN 0x000f0
176 #define CORE_SFT_LRN_CTRL 0x000f8
177 #define SW_LEARN_CNTL(x) (1 << (x))
179 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
180 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
181 #define LINK_STS (1 << 0)
182 #define DUPLX_MODE (1 << 1)
183 #define SPEED_SHIFT 2
184 #define SPEED_MASK 0x3
185 #define RXFLOW_CNTL (1 << 4)
186 #define TXFLOW_CNTL (1 << 5)
187 #define SW_OVERRIDE (1 << 6)
189 #define CORE_WATCHDOG_CTRL 0x001e4
190 #define SOFTWARE_RESET (1 << 7)
191 #define EN_CHIP_RST (1 << 6)
192 #define EN_SW_RESET (1 << 4)
194 #define CORE_FAST_AGE_CTRL 0x00220
195 #define EN_FAST_AGE_STATIC (1 << 0)
196 #define EN_AGE_DYNAMIC (1 << 1)
197 #define EN_AGE_PORT (1 << 2)
198 #define EN_AGE_VLAN (1 << 3)
199 #define EN_AGE_SPT (1 << 4)
200 #define EN_AGE_MCAST (1 << 5)
201 #define FAST_AGE_STR_DONE (1 << 7)
203 #define CORE_FAST_AGE_PORT 0x00224
204 #define AGE_PORT_MASK 0xf
206 #define CORE_FAST_AGE_VID 0x00228
207 #define AGE_VID_MASK 0x3fff
209 #define CORE_LNKSTS 0x00400
210 #define LNK_STS_MASK 0x1ff
212 #define CORE_SPDSTS 0x00410
215 #define SPDSTS_1000 2
216 #define SPDSTS_SHIFT 2
217 #define SPDSTS_MASK 0x3
219 #define CORE_DUPSTS 0x00420
220 #define CORE_DUPSTS_MASK 0x1ff
222 #define CORE_PAUSESTS 0x00428
223 #define PAUSESTS_TX_PAUSE_SHIFT 9
225 #define CORE_GMNCFGCFG 0x0800
226 #define RST_MIB_CNT (1 << 0)
227 #define RXBPDU_EN (1 << 1)
229 #define CORE_IMP0_PRT_ID 0x0804
231 #define CORE_RST_MIB_CNT_EN 0x0950
233 #define CORE_ARLA_VTBL_RWCTRL 0x1600
234 #define ARLA_VTBL_CMD_WRITE 0
235 #define ARLA_VTBL_CMD_READ 1
236 #define ARLA_VTBL_CMD_CLEAR 2
237 #define ARLA_VTBL_STDN (1 << 7)
239 #define CORE_ARLA_VTBL_ADDR 0x1604
240 #define VTBL_ADDR_INDEX_MASK 0xfff
242 #define CORE_ARLA_VTBL_ENTRY 0x160c
243 #define FWD_MAP_MASK 0x1ff
244 #define UNTAG_MAP_MASK 0x1ff
245 #define UNTAG_MAP_SHIFT 9
246 #define MSTP_INDEX_MASK 0x7
247 #define MSTP_INDEX_SHIFT 18
248 #define FWD_MODE (1 << 21)
250 #define CORE_MEM_PSM_VDD_CTRL 0x2380
251 #define P_TXQ_PSM_VDD_SHIFT 2
252 #define P_TXQ_PSM_VDD_MASK 0x3
253 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
254 ((x) * P_TXQ_PSM_VDD_SHIFT))
256 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
257 #define PRT_TO_QID_MASK 0x3
258 #define PRT_TO_QID_SHIFT 3
260 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
261 #define PORT_VLAN_CTRL_MASK 0x1ff
263 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
264 #define TXQ_PAUSE_THD_MASK 0x7ff
265 #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \
268 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
273 #define CORE_JOIN_ALL_VLAN_EN 0xd140
275 #define CORE_CFP_ACC 0x28000
276 #define OP_STR_DONE (1 << 0)
277 #define OP_SEL_SHIFT 1
278 #define OP_SEL_READ (1 << OP_SEL_SHIFT)
279 #define OP_SEL_WRITE (2 << OP_SEL_SHIFT)
280 #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT)
281 #define OP_SEL_MASK (7 << OP_SEL_SHIFT)
282 #define CFP_RAM_CLEAR (1 << 4)
283 #define RAM_SEL_SHIFT 10
284 #define TCAM_SEL (1 << RAM_SEL_SHIFT)
285 #define ACT_POL_RAM (2 << RAM_SEL_SHIFT)
286 #define RATE_METER_RAM (4 << RAM_SEL_SHIFT)
287 #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT)
288 #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT)
289 #define RED_STAT_RAM (24 << RAM_SEL_SHIFT)
290 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
291 #define TCAM_RESET (1 << 15)
292 #define XCESS_ADDR_SHIFT 16
293 #define XCESS_ADDR_MASK 0xff
294 #define SEARCH_STS (1 << 27)
295 #define RD_STS_SHIFT 28
296 #define RD_STS_TCAM (1 << RD_STS_SHIFT)
297 #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT)
298 #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT)
299 #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT)
301 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
303 #define CORE_CFP_DATA_PORT_0 0x28040
304 #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \
308 #define L3_FRAMING_SHIFT 24
309 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
310 #define IPTOS_SHIFT 16
311 #define IPTOS_MASK 0xff
312 #define IPPROTO_SHIFT 8
313 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
314 #define IP_FRAG_SHIFT 7
315 #define IP_FRAG (1 << IP_FRAG_SHIFT)
318 #define SLICE_VALID 3
319 #define SLICE_NUM_SHIFT 2
320 #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT)
321 #define SLICE_NUM_MASK 0x3
323 #define CORE_CFP_MASK_PORT_0 0x280c0
325 #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \
328 #define CORE_ACT_POL_DATA0 0x28140
329 #define VLAN_BYP (1 << 0)
330 #define EAP_BYP (1 << 1)
331 #define STP_BYP (1 << 2)
332 #define REASON_CODE_SHIFT 3
333 #define REASON_CODE_MASK 0x3f
334 #define LOOP_BK_EN (1 << 9)
335 #define NEW_TC_SHIFT 10
336 #define NEW_TC_MASK 0x7
337 #define CHANGE_TC (1 << 13)
338 #define DST_MAP_IB_SHIFT 14
339 #define DST_MAP_IB_MASK 0x1ff
340 #define CHANGE_FWRD_MAP_IB_SHIFT 24
341 #define CHANGE_FWRD_MAP_IB_MASK 0x3
342 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
343 #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT)
344 #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT)
345 #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT)
346 #define NEW_DSCP_IB_SHIFT 26
347 #define NEW_DSCP_IB_MASK 0x3f
349 #define CORE_ACT_POL_DATA1 0x28150
350 #define CHANGE_DSCP_IB (1 << 0)
351 #define DST_MAP_OB_SHIFT 1
352 #define DST_MAP_OB_MASK 0x3ff
353 #define CHANGE_FWRD_MAP_OB_SHIT 11
354 #define CHANGE_FWRD_MAP_OB_MASK 0x3
355 #define NEW_DSCP_OB_SHIFT 13
356 #define NEW_DSCP_OB_MASK 0x3f
357 #define CHANGE_DSCP_OB (1 << 19)
358 #define CHAIN_ID_SHIFT 20
359 #define CHAIN_ID_MASK 0xff
360 #define CHANGE_COLOR (1 << 28)
361 #define NEW_COLOR_SHIFT 29
362 #define NEW_COLOR_MASK 0x3
363 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
364 #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT)
365 #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT)
366 #define RED_DEFAULT (1 << 31)
368 #define CORE_ACT_POL_DATA2 0x28160
369 #define MAC_LIMIT_BYPASS (1 << 0)
370 #define CHANGE_TC_O (1 << 1)
371 #define NEW_TC_O_SHIFT 2
372 #define NEW_TC_O_MASK 0x7
373 #define SPCP_RMK_DISABLE (1 << 5)
374 #define CPCP_RMK_DISABLE (1 << 6)
375 #define DEI_RMK_DISABLE (1 << 7)
377 #define CORE_RATE_METER0 0x28180
378 #define COLOR_MODE (1 << 0)
379 #define POLICER_ACTION (1 << 1)
380 #define COUPLING_FLAG (1 << 2)
381 #define POLICER_MODE_SHIFT 3
382 #define POLICER_MODE_MASK 0x3
383 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
384 #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT)
385 #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT)
386 #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT)
388 #define CORE_RATE_METER1 0x28190
389 #define EIR_TK_BKT_MASK 0x7fffff
391 #define CORE_RATE_METER2 0x281a0
392 #define EIR_BKT_SIZE_MASK 0xfffff
394 #define CORE_RATE_METER3 0x281b0
395 #define EIR_REF_CNT_MASK 0x7ffff
397 #define CORE_RATE_METER4 0x281c0
398 #define CIR_TK_BKT_MASK 0x7fffff
400 #define CORE_RATE_METER5 0x281d0
401 #define CIR_BKT_SIZE_MASK 0xfffff
403 #define CORE_RATE_METER6 0x281e0
404 #define CIR_REF_CNT_MASK 0x7ffff
406 #define CORE_STAT_GREEN_CNTR 0x28200
407 #define CORE_STAT_YELLOW_CNTR 0x28210
408 #define CORE_STAT_RED_CNTR 0x28220
410 #define CORE_CFP_CTL_REG 0x28400
411 #define CFP_EN_MAP_MASK 0x1ff
413 /* IPv4 slices, 3 of them */
414 #define CORE_UDF_0_A_0_8_PORT_0 0x28440
415 #define CFG_UDF_OFFSET_MASK 0x1f
416 #define CFG_UDF_OFFSET_BASE_SHIFT 5
417 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
418 #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT)
419 #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT)
422 #define CORE_UDF_0_B_0_8_PORT_0 0x28500
424 /* IPv6 chained slices */
425 #define CORE_UDF_0_D_0_11_PORT_0 0x28680
427 /* Number of slices for IPv4, IPv6 and non-IP */
428 #define UDF_NUM_SLICES 4
429 #define UDFS_PER_SLICE 9
431 /* Spacing between different slices */
432 #define UDF_SLICE_OFFSET 0x40
434 #define CFP_NUM_RULES 256
436 /* Number of egress queues per port */
437 #define SF2_NUM_EGRESS_QUEUES 8
439 #endif /* __BCM_SF2_REGS_H */