2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
38 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
40 return DSA_TAG_PROTO_BRCM;
43 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
45 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
49 /* Enable the IMP Port to be in the same VLAN as the other ports
50 * on a per-port basis such that we only have Port i and IMP in
53 for (i = 0; i < priv->hw_params.num_ports; i++) {
54 if (!((1 << i) & ds->enabled_port_mask))
57 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
58 reg |= (1 << cpu_port);
59 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
63 static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)
67 /* Resolve which bit controls the Broadcom tag */
83 /* Enable Broadcom tags for IMP port */
84 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
86 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
88 /* Enable reception Broadcom tag for CPU TX (switch RX) to
89 * allow us to tag outgoing frames
91 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
93 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
95 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
96 * allow delivering frames to the per-port net_devices
98 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
100 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
103 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
105 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
109 /* Enable the port memories */
110 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
111 reg &= ~P_TXQ_PSM_VDD(port);
112 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
114 /* Enable forwarding */
115 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
117 /* Enable IMP port in dumb mode */
118 reg = core_readl(priv, CORE_SWITCH_CTRL);
119 reg |= MII_DUMB_FWDG_EN;
120 core_writel(priv, reg, CORE_SWITCH_CTRL);
122 /* Configure Traffic Class to QoS mapping, allow each priority to map
123 * to a different queue number
125 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
126 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
127 reg |= i << (PRT_TO_QID_SHIFT * i);
128 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
130 bcm_sf2_brcm_hdr_setup(priv, port);
133 if (priv->type == BCM7445_DEVICE_ID)
134 offset = CORE_STS_OVERRIDE_IMP;
136 offset = CORE_STS_OVERRIDE_IMP2;
138 /* Force link status for IMP port */
139 reg = core_readl(priv, offset);
140 reg |= (MII_SW_OR | LINK_STS);
141 reg &= ~GMII_SPEED_UP_2G;
142 core_writel(priv, reg, offset);
144 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
145 reg = core_readl(priv, CORE_IMP_CTL);
146 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
147 reg &= ~(RX_DIS | TX_DIS);
148 core_writel(priv, reg, CORE_IMP_CTL);
150 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
151 reg &= ~(RX_DIS | TX_DIS);
152 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
156 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
158 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 reg = core_readl(priv, CORE_EEE_EN_CTRL);
166 core_writel(priv, reg, CORE_EEE_EN_CTRL);
169 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
171 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
174 reg = reg_readl(priv, REG_SPHY_CNTRL);
177 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
178 reg_writel(priv, reg, REG_SPHY_CNTRL);
180 reg = reg_readl(priv, REG_SPHY_CNTRL);
183 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
184 reg_writel(priv, reg, REG_SPHY_CNTRL);
188 reg_writel(priv, reg, REG_SPHY_CNTRL);
190 /* Use PHY-driven LED signaling */
192 reg = reg_readl(priv, REG_LED_CNTRL(0));
193 reg |= SPDLNK_SRC_SEL;
194 reg_writel(priv, reg, REG_LED_CNTRL(0));
198 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
208 /* Port 0 interrupts are located on the first bank */
209 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
212 off = P_IRQ_OFF(port);
216 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
219 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
229 /* Port 0 interrupts are located on the first bank */
230 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
231 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
234 off = P_IRQ_OFF(port);
238 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
239 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
242 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
243 struct phy_device *phy)
245 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246 s8 cpu_port = ds->dst->cpu_dp->index;
250 /* Clear the memory power down */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg &= ~P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
255 /* Disable learning */
256 reg = core_readl(priv, CORE_DIS_LEARN);
258 core_writel(priv, reg, CORE_DIS_LEARN);
260 /* Enable Broadcom tags for that port if requested */
261 if (priv->brcm_tag_mask & BIT(port))
262 bcm_sf2_brcm_hdr_setup(priv, port);
264 /* Configure Traffic Class to QoS mapping, allow each priority to map
265 * to a different queue number
267 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
268 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
269 reg |= i << (PRT_TO_QID_SHIFT * i);
270 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
272 /* Clear the Rx and Tx disable bits and set to no spanning tree */
273 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
275 /* Re-enable the GPHY and re-apply workarounds */
276 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
277 bcm_sf2_gphy_enable_set(ds, true);
279 /* if phy_stop() has been called before, phy
280 * will be in halted state, and phy_start()
283 * the resume path does not configure back
284 * autoneg settings, and since we hard reset
285 * the phy manually here, we need to reset the
286 * state machine also.
288 phy->state = PHY_READY;
293 /* Enable MoCA port interrupts to get notified */
294 if (port == priv->moca_port)
295 bcm_sf2_port_intr_enable(priv, port);
297 /* Set this port, and only this one to be in the default VLAN,
298 * if member of a bridge, restore its membership prior to
299 * bringing down this port.
301 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
302 reg &= ~PORT_VLAN_CTRL_MASK;
304 reg |= priv->dev->ports[port].vlan_ctl_mask;
305 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
307 bcm_sf2_imp_vlan_setup(ds, cpu_port);
309 /* If EEE was enabled, restore it */
310 if (priv->port_sts[port].eee.eee_enabled)
311 bcm_sf2_eee_enable_set(ds, port, true);
316 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
317 struct phy_device *phy)
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
322 if (priv->wol_ports_mask & (1 << port))
325 if (port == priv->moca_port)
326 bcm_sf2_port_intr_disable(priv, port);
328 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
329 bcm_sf2_gphy_enable_set(ds, false);
331 if (dsa_is_cpu_port(ds, port))
334 off = CORE_G_PCTL_PORT(port);
336 reg = core_readl(priv, off);
337 reg |= RX_DIS | TX_DIS;
338 core_writel(priv, reg, off);
340 /* Power down the port memory */
341 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
342 reg |= P_TXQ_PSM_VDD(port);
343 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
346 /* Returns 0 if EEE was not enabled, or 1 otherwise
348 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
349 struct phy_device *phy)
353 ret = phy_init_eee(phy, 0);
357 bcm_sf2_eee_enable_set(ds, port, true);
362 static int bcm_sf2_sw_get_mac_eee(struct dsa_switch *ds, int port,
363 struct ethtool_eee *e)
365 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
366 struct ethtool_eee *p = &priv->port_sts[port].eee;
369 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
370 e->eee_enabled = p->eee_enabled;
371 e->eee_active = !!(reg & (1 << port));
376 static int bcm_sf2_sw_set_mac_eee(struct dsa_switch *ds, int port,
377 struct ethtool_eee *e)
379 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
380 struct ethtool_eee *p = &priv->port_sts[port].eee;
382 p->eee_enabled = e->eee_enabled;
383 bcm_sf2_eee_enable_set(ds, port, e->eee_enabled);
388 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
394 reg = reg_readl(priv, REG_SWITCH_CNTRL);
395 reg |= MDIO_MASTER_SEL;
396 reg_writel(priv, reg, REG_SWITCH_CNTRL);
398 /* Page << 8 | offset */
401 core_writel(priv, addr, reg);
403 /* Page << 8 | offset */
404 reg = 0x80 << 8 | regnum << 1;
408 ret = core_readl(priv, reg);
410 core_writel(priv, val, reg);
412 reg = reg_readl(priv, REG_SWITCH_CNTRL);
413 reg &= ~MDIO_MASTER_SEL;
414 reg_writel(priv, reg, REG_SWITCH_CNTRL);
419 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
421 struct bcm_sf2_priv *priv = bus->priv;
423 /* Intercept reads from Broadcom pseudo-PHY address, else, send
424 * them to our master MDIO bus controller
426 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
427 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
429 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
432 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
435 struct bcm_sf2_priv *priv = bus->priv;
437 /* Intercept writes to the Broadcom pseudo-PHY address, else,
438 * send them to our master MDIO bus controller
440 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
441 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
443 return mdiobus_write_nested(priv->master_mii_bus, addr,
447 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
449 struct bcm_sf2_priv *priv = dev_id;
451 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
453 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
458 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
460 struct bcm_sf2_priv *priv = dev_id;
462 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
464 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
466 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
467 priv->port_sts[7].link = 1;
468 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
469 priv->port_sts[7].link = 0;
474 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
476 unsigned int timeout = 1000;
479 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
480 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
481 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
484 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
485 if (!(reg & SOFTWARE_RESET))
488 usleep_range(1000, 2000);
489 } while (timeout-- > 0);
497 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
499 intrl2_0_mask_set(priv, 0xffffffff);
500 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
501 intrl2_1_mask_set(priv, 0xffffffff);
502 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
505 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
506 struct device_node *dn)
508 struct device_node *port;
510 unsigned int port_num;
512 priv->moca_port = -1;
514 for_each_available_child_of_node(dn, port) {
515 if (of_property_read_u32(port, "reg", &port_num))
518 /* Internal PHYs get assigned a specific 'phy-mode' property
519 * value: "internal" to help flag them before MDIO probing
520 * has completed, since they might be turned off at that
523 mode = of_get_phy_mode(port);
527 if (mode == PHY_INTERFACE_MODE_INTERNAL)
528 priv->int_phy_mask |= 1 << port_num;
530 if (mode == PHY_INTERFACE_MODE_MOCA)
531 priv->moca_port = port_num;
533 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
534 priv->brcm_tag_mask |= 1 << port_num;
538 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
540 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
541 struct device_node *dn;
545 /* Find our integrated MDIO bus node */
546 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
547 priv->master_mii_bus = of_mdio_find_bus(dn);
548 if (!priv->master_mii_bus) {
550 return -EPROBE_DEFER;
553 get_device(&priv->master_mii_bus->dev);
554 priv->master_mii_dn = dn;
556 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
557 if (!priv->slave_mii_bus) {
562 priv->slave_mii_bus->priv = priv;
563 priv->slave_mii_bus->name = "sf2 slave mii";
564 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
565 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
566 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
568 priv->slave_mii_bus->dev.of_node = dn;
570 /* Include the pseudo-PHY address to divert reads towards our
571 * workaround. This is only required for 7445D0, since 7445E0
572 * disconnects the internal switch pseudo-PHY such that we can use the
573 * regular SWITCH_MDIO master controller instead.
575 * Here we flag the pseudo PHY as needing special treatment and would
576 * otherwise make all other PHY read/writes go to the master MDIO bus
577 * controller that comes with this switch backed by the "mdio-unimac"
580 if (of_machine_is_compatible("brcm,bcm7445d0"))
581 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
583 priv->indir_phy_mask = 0;
585 ds->phys_mii_mask = priv->indir_phy_mask;
586 ds->slave_mii_bus = priv->slave_mii_bus;
587 priv->slave_mii_bus->parent = ds->dev->parent;
588 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
591 err = of_mdiobus_register(priv->slave_mii_bus, dn);
593 err = mdiobus_register(priv->slave_mii_bus);
601 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
603 mdiobus_unregister(priv->slave_mii_bus);
604 if (priv->master_mii_dn)
605 of_node_put(priv->master_mii_dn);
608 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
610 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
612 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
613 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
614 * the REG_PHY_REVISION register layout is.
616 if (priv->int_phy_mask & BIT(port))
617 return priv->hw_params.gphy_rev;
622 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
623 struct phy_device *phydev)
625 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
626 struct ethtool_eee *p = &priv->port_sts[port].eee;
627 u32 id_mode_dis = 0, port_mode;
628 u16 lcl_adv = 0, rmt_adv = 0;
629 const char *str = NULL;
633 if (priv->type == BCM7445_DEVICE_ID)
634 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
636 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
638 switch (phydev->interface) {
639 case PHY_INTERFACE_MODE_RGMII:
640 str = "RGMII (no delay)";
642 case PHY_INTERFACE_MODE_RGMII_TXID:
644 str = "RGMII (TX delay)";
645 port_mode = EXT_GPHY;
647 case PHY_INTERFACE_MODE_MII:
649 port_mode = EXT_EPHY;
651 case PHY_INTERFACE_MODE_REVMII:
653 port_mode = EXT_REVMII;
656 /* All other PHYs: internal and MoCA */
660 /* If the link is down, just disable the interface to conserve power */
662 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
663 reg &= ~RGMII_MODE_EN;
664 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
668 /* Clear id_mode_dis bit, and the existing port mode, but
669 * make sure we enable the RGMII block for data to pass
671 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
673 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
674 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
676 reg |= port_mode | RGMII_MODE_EN;
681 if (phydev->asym_pause)
686 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
688 pr_info("Port %d configured for %s\n", port, str);
691 /* Force link settings detected from the PHY */
693 switch (phydev->speed) {
695 reg |= SPDSTS_1000 << SPEED_SHIFT;
698 reg |= SPDSTS_100 << SPEED_SHIFT;
702 if (phydev->duplex == DUPLEX_FULL &&
703 phydev->autoneg == AUTONEG_ENABLE) {
705 rmt_adv = LPA_PAUSE_CAP;
706 if (phydev->asym_pause)
707 rmt_adv |= LPA_PAUSE_ASYM;
708 if (phydev->advertising & ADVERTISED_Pause)
709 lcl_adv = ADVERTISE_PAUSE_CAP;
710 if (phydev->advertising & ADVERTISED_Asym_Pause)
711 lcl_adv |= ADVERTISE_PAUSE_ASYM;
712 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
717 if (phydev->duplex == DUPLEX_FULL)
719 if (flowctrl & FLOW_CTRL_TX)
721 if (flowctrl & FLOW_CTRL_RX)
724 core_writel(priv, reg, offset);
726 if (!phydev->is_pseudo_fixed_link)
727 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
730 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
731 struct fixed_phy_status *status)
733 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
734 u32 duplex, pause, offset;
737 if (priv->type == BCM7445_DEVICE_ID)
738 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
740 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
742 duplex = core_readl(priv, CORE_DUPSTS);
743 pause = core_readl(priv, CORE_PAUSESTS);
747 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
748 * which means that we need to force the link at the port override
749 * level to get the data to flow. We do use what the interrupt handler
750 * did determine before.
752 * For the other ports, we just force the link status, since this is
753 * a fixed PHY device.
755 if (port == priv->moca_port) {
756 status->link = priv->port_sts[port].link;
757 /* For MoCA interfaces, also force a link down notification
758 * since some version of the user-space daemon (mocad) use
759 * cmd->autoneg to force the link, which messes up the PHY
760 * state machine and make it go in PHY_FORCING state instead.
763 netif_carrier_off(ds->ports[port].netdev);
767 status->duplex = !!(duplex & (1 << port));
770 reg = core_readl(priv, offset);
776 core_writel(priv, reg, offset);
778 if ((pause & (1 << port)) &&
779 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
780 status->asym_pause = 1;
784 if (pause & (1 << port))
788 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
790 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
793 bcm_sf2_intr_disable(priv);
795 /* Disable all ports physically present including the IMP
796 * port, the other ones have already been disabled during
799 for (port = 0; port < DSA_MAX_PORTS; port++) {
800 if ((1 << port) & ds->enabled_port_mask ||
801 dsa_is_cpu_port(ds, port))
802 bcm_sf2_port_disable(ds, port, NULL);
808 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
810 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
813 ret = bcm_sf2_sw_rst(priv);
815 pr_err("%s: failed to software reset switch\n", __func__);
819 if (priv->hw_params.num_gphy == 1)
820 bcm_sf2_gphy_enable_set(ds, true);
827 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
828 struct ethtool_wolinfo *wol)
830 struct net_device *p = ds->dst->cpu_dp->netdev;
831 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
832 struct ethtool_wolinfo pwol;
834 /* Get the parent device WoL settings */
835 p->ethtool_ops->get_wol(p, &pwol);
837 /* Advertise the parent device supported settings */
838 wol->supported = pwol.supported;
839 memset(&wol->sopass, 0, sizeof(wol->sopass));
841 if (pwol.wolopts & WAKE_MAGICSECURE)
842 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
844 if (priv->wol_ports_mask & (1 << port))
845 wol->wolopts = pwol.wolopts;
850 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
851 struct ethtool_wolinfo *wol)
853 struct net_device *p = ds->dst->cpu_dp->netdev;
854 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
855 s8 cpu_port = ds->dst->cpu_dp->index;
856 struct ethtool_wolinfo pwol;
858 p->ethtool_ops->get_wol(p, &pwol);
859 if (wol->wolopts & ~pwol.supported)
863 priv->wol_ports_mask |= (1 << port);
865 priv->wol_ports_mask &= ~(1 << port);
867 /* If we have at least one port enabled, make sure the CPU port
868 * is also enabled. If the CPU port is the last one enabled, we disable
869 * it since this configuration does not make sense.
871 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
872 priv->wol_ports_mask |= (1 << cpu_port);
874 priv->wol_ports_mask &= ~(1 << cpu_port);
876 return p->ethtool_ops->set_wol(p, wol);
879 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
881 unsigned int timeout = 10;
885 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
886 if (!(reg & ARLA_VTBL_STDN))
889 usleep_range(1000, 2000);
895 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
897 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
899 return bcm_sf2_vlan_op_wait(priv);
902 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
904 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
907 /* Clear all VLANs */
908 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
910 for (port = 0; port < priv->hw_params.num_ports; port++) {
911 if (!((1 << port) & ds->enabled_port_mask))
914 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
918 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
920 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
923 /* Enable all valid ports and disable those unused */
924 for (port = 0; port < priv->hw_params.num_ports; port++) {
925 /* IMP port receives special treatment */
926 if ((1 << port) & ds->enabled_port_mask)
927 bcm_sf2_port_setup(ds, port, NULL);
928 else if (dsa_is_cpu_port(ds, port))
929 bcm_sf2_imp_setup(ds, port);
931 bcm_sf2_port_disable(ds, port, NULL);
934 bcm_sf2_sw_configure_vlan(ds);
939 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
940 * register basis so we need to translate that into an address that the
941 * bus-glue understands.
943 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
945 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
948 struct bcm_sf2_priv *priv = dev->priv;
950 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
955 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
958 struct bcm_sf2_priv *priv = dev->priv;
960 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
965 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
968 struct bcm_sf2_priv *priv = dev->priv;
970 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
975 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
978 struct bcm_sf2_priv *priv = dev->priv;
980 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
985 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
988 struct bcm_sf2_priv *priv = dev->priv;
990 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
995 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
998 struct bcm_sf2_priv *priv = dev->priv;
1000 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1005 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1008 struct bcm_sf2_priv *priv = dev->priv;
1010 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1015 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1018 struct bcm_sf2_priv *priv = dev->priv;
1020 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1025 static const struct b53_io_ops bcm_sf2_io_ops = {
1026 .read8 = bcm_sf2_core_read8,
1027 .read16 = bcm_sf2_core_read16,
1028 .read32 = bcm_sf2_core_read32,
1029 .read48 = bcm_sf2_core_read64,
1030 .read64 = bcm_sf2_core_read64,
1031 .write8 = bcm_sf2_core_write8,
1032 .write16 = bcm_sf2_core_write16,
1033 .write32 = bcm_sf2_core_write32,
1034 .write48 = bcm_sf2_core_write64,
1035 .write64 = bcm_sf2_core_write64,
1038 static const struct dsa_switch_ops bcm_sf2_ops = {
1039 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
1040 .setup = bcm_sf2_sw_setup,
1041 .get_strings = b53_get_strings,
1042 .get_ethtool_stats = b53_get_ethtool_stats,
1043 .get_sset_count = b53_get_sset_count,
1044 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1045 .adjust_link = bcm_sf2_sw_adjust_link,
1046 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1047 .suspend = bcm_sf2_sw_suspend,
1048 .resume = bcm_sf2_sw_resume,
1049 .get_wol = bcm_sf2_sw_get_wol,
1050 .set_wol = bcm_sf2_sw_set_wol,
1051 .port_enable = bcm_sf2_port_setup,
1052 .port_disable = bcm_sf2_port_disable,
1053 .get_mac_eee = bcm_sf2_sw_get_mac_eee,
1054 .set_mac_eee = bcm_sf2_sw_set_mac_eee,
1055 .port_bridge_join = b53_br_join,
1056 .port_bridge_leave = b53_br_leave,
1057 .port_stp_state_set = b53_br_set_stp_state,
1058 .port_fast_age = b53_br_fast_age,
1059 .port_vlan_filtering = b53_vlan_filtering,
1060 .port_vlan_prepare = b53_vlan_prepare,
1061 .port_vlan_add = b53_vlan_add,
1062 .port_vlan_del = b53_vlan_del,
1063 .port_fdb_dump = b53_fdb_dump,
1064 .port_fdb_add = b53_fdb_add,
1065 .port_fdb_del = b53_fdb_del,
1066 .get_rxnfc = bcm_sf2_get_rxnfc,
1067 .set_rxnfc = bcm_sf2_set_rxnfc,
1068 .port_mirror_add = b53_mirror_add,
1069 .port_mirror_del = b53_mirror_del,
1072 struct bcm_sf2_of_data {
1074 const u16 *reg_offsets;
1075 unsigned int core_reg_align;
1076 unsigned int num_cfp_rules;
1079 /* Register offsets for the SWITCH_REG_* block */
1080 static const u16 bcm_sf2_7445_reg_offsets[] = {
1081 [REG_SWITCH_CNTRL] = 0x00,
1082 [REG_SWITCH_STATUS] = 0x04,
1083 [REG_DIR_DATA_WRITE] = 0x08,
1084 [REG_DIR_DATA_READ] = 0x0C,
1085 [REG_SWITCH_REVISION] = 0x18,
1086 [REG_PHY_REVISION] = 0x1C,
1087 [REG_SPHY_CNTRL] = 0x2C,
1088 [REG_RGMII_0_CNTRL] = 0x34,
1089 [REG_RGMII_1_CNTRL] = 0x40,
1090 [REG_RGMII_2_CNTRL] = 0x4c,
1091 [REG_LED_0_CNTRL] = 0x90,
1092 [REG_LED_1_CNTRL] = 0x94,
1093 [REG_LED_2_CNTRL] = 0x98,
1096 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1097 .type = BCM7445_DEVICE_ID,
1098 .core_reg_align = 0,
1099 .reg_offsets = bcm_sf2_7445_reg_offsets,
1100 .num_cfp_rules = 256,
1103 static const u16 bcm_sf2_7278_reg_offsets[] = {
1104 [REG_SWITCH_CNTRL] = 0x00,
1105 [REG_SWITCH_STATUS] = 0x04,
1106 [REG_DIR_DATA_WRITE] = 0x08,
1107 [REG_DIR_DATA_READ] = 0x0c,
1108 [REG_SWITCH_REVISION] = 0x10,
1109 [REG_PHY_REVISION] = 0x14,
1110 [REG_SPHY_CNTRL] = 0x24,
1111 [REG_RGMII_0_CNTRL] = 0xe0,
1112 [REG_RGMII_1_CNTRL] = 0xec,
1113 [REG_RGMII_2_CNTRL] = 0xf8,
1114 [REG_LED_0_CNTRL] = 0x40,
1115 [REG_LED_1_CNTRL] = 0x4c,
1116 [REG_LED_2_CNTRL] = 0x58,
1119 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1120 .type = BCM7278_DEVICE_ID,
1121 .core_reg_align = 1,
1122 .reg_offsets = bcm_sf2_7278_reg_offsets,
1123 .num_cfp_rules = 128,
1126 static const struct of_device_id bcm_sf2_of_match[] = {
1127 { .compatible = "brcm,bcm7445-switch-v4.0",
1128 .data = &bcm_sf2_7445_data
1130 { .compatible = "brcm,bcm7278-switch-v4.0",
1131 .data = &bcm_sf2_7278_data
1135 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1137 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1139 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1140 struct device_node *dn = pdev->dev.of_node;
1141 const struct of_device_id *of_id = NULL;
1142 const struct bcm_sf2_of_data *data;
1143 struct b53_platform_data *pdata;
1144 struct dsa_switch_ops *ops;
1145 struct device_node *ports;
1146 struct bcm_sf2_priv *priv;
1147 struct b53_device *dev;
1148 struct dsa_switch *ds;
1149 void __iomem **base;
1155 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1159 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1163 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1171 of_id = of_match_node(bcm_sf2_of_match, dn);
1172 if (!of_id || !of_id->data)
1177 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1178 priv->type = data->type;
1179 priv->reg_offsets = data->reg_offsets;
1180 priv->core_reg_align = data->core_reg_align;
1181 priv->num_cfp_rules = data->num_cfp_rules;
1183 /* Auto-detection using standard registers will not work, so
1184 * provide an indication of what kind of device we are for
1185 * b53_common to work with
1187 pdata->chip_id = priv->type;
1192 ds->ops = &bcm_sf2_ops;
1194 /* Advertise the 8 egress queues */
1195 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1197 dev_set_drvdata(&pdev->dev, priv);
1199 spin_lock_init(&priv->indir_lock);
1200 mutex_init(&priv->stats_mutex);
1201 mutex_init(&priv->cfp.lock);
1203 /* CFP rule #0 cannot be used for specific classifications, flag it as
1206 set_bit(0, priv->cfp.used);
1208 /* Balance of_node_put() done by of_find_node_by_name() */
1210 ports = of_find_node_by_name(dn, "ports");
1212 bcm_sf2_identify_ports(priv, ports);
1216 priv->irq0 = irq_of_parse_and_map(dn, 0);
1217 priv->irq1 = irq_of_parse_and_map(dn, 1);
1220 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1221 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1222 *base = devm_ioremap_resource(&pdev->dev, r);
1223 if (IS_ERR(*base)) {
1224 pr_err("unable to find register: %s\n", reg_names[i]);
1225 return PTR_ERR(*base);
1230 ret = bcm_sf2_sw_rst(priv);
1232 pr_err("unable to software reset switch: %d\n", ret);
1236 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1238 ret = bcm_sf2_mdio_register(ds);
1240 pr_err("failed to register MDIO bus\n");
1244 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1246 ret = bcm_sf2_cfp_rst(priv);
1248 pr_err("failed to reset CFP\n");
1252 /* Disable all interrupts and request them */
1253 bcm_sf2_intr_disable(priv);
1255 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1258 pr_err("failed to request switch_0 IRQ\n");
1262 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1265 pr_err("failed to request switch_1 IRQ\n");
1269 /* Reset the MIB counters */
1270 reg = core_readl(priv, CORE_GMNCFGCFG);
1272 core_writel(priv, reg, CORE_GMNCFGCFG);
1273 reg &= ~RST_MIB_CNT;
1274 core_writel(priv, reg, CORE_GMNCFGCFG);
1276 /* Get the maximum number of ports for this switch */
1277 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1278 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1279 priv->hw_params.num_ports = DSA_MAX_PORTS;
1281 /* Assume a single GPHY setup if we can't read that property */
1282 if (of_property_read_u32(dn, "brcm,num-gphy",
1283 &priv->hw_params.num_gphy))
1284 priv->hw_params.num_gphy = 1;
1286 rev = reg_readl(priv, REG_SWITCH_REVISION);
1287 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1288 SWITCH_TOP_REV_MASK;
1289 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1291 rev = reg_readl(priv, REG_PHY_REVISION);
1292 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1294 ret = b53_switch_register(dev);
1298 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1299 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1300 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1301 priv->core, priv->irq0, priv->irq1);
1306 bcm_sf2_mdio_unregister(priv);
1310 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1312 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1314 priv->wol_ports_mask = 0;
1315 dsa_unregister_switch(priv->dev->ds);
1316 /* Disable all ports and interrupts */
1317 bcm_sf2_sw_suspend(priv->dev->ds);
1318 bcm_sf2_mdio_unregister(priv);
1323 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1325 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1327 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1328 * successful MDIO bus scan to occur. If we did turn off the GPHY
1329 * before (e.g: port_disable), this will also power it back on.
1331 * Do not rely on kexec_in_progress, just power the PHY on.
1333 if (priv->hw_params.num_gphy == 1)
1334 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1337 #ifdef CONFIG_PM_SLEEP
1338 static int bcm_sf2_suspend(struct device *dev)
1340 struct platform_device *pdev = to_platform_device(dev);
1341 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1343 return dsa_switch_suspend(priv->dev->ds);
1346 static int bcm_sf2_resume(struct device *dev)
1348 struct platform_device *pdev = to_platform_device(dev);
1349 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1351 return dsa_switch_resume(priv->dev->ds);
1353 #endif /* CONFIG_PM_SLEEP */
1355 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1356 bcm_sf2_suspend, bcm_sf2_resume);
1359 static struct platform_driver bcm_sf2_driver = {
1360 .probe = bcm_sf2_sw_probe,
1361 .remove = bcm_sf2_sw_remove,
1362 .shutdown = bcm_sf2_sw_shutdown,
1365 .of_match_table = bcm_sf2_of_match,
1366 .pm = &bcm_sf2_pm_ops,
1369 module_platform_driver(bcm_sf2_driver);
1371 MODULE_AUTHOR("Broadcom Corporation");
1372 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1373 MODULE_LICENSE("GPL");
1374 MODULE_ALIAS("platform:brcm-sf2");