2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <net/switchdev.h>
32 #include <linux/platform_data/b53.h>
35 #include "bcm_sf2_regs.h"
36 #include "b53/b53_priv.h"
37 #include "b53/b53_regs.h"
39 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
41 return DSA_TAG_PROTO_BRCM;
44 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
46 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
50 /* Enable the IMP Port to be in the same VLAN as the other ports
51 * on a per-port basis such that we only have Port i and IMP in
54 for (i = 0; i < priv->hw_params.num_ports; i++) {
55 if (!((1 << i) & ds->enabled_port_mask))
58 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
59 reg |= (1 << cpu_port);
60 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
64 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
66 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
69 /* Enable the port memories */
70 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
71 reg &= ~P_TXQ_PSM_VDD(port);
72 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
80 /* Enable forwarding */
81 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
83 /* Enable IMP port in dumb mode */
84 reg = core_readl(priv, CORE_SWITCH_CTRL);
85 reg |= MII_DUMB_FWDG_EN;
86 core_writel(priv, reg, CORE_SWITCH_CTRL);
88 /* Resolve which bit controls the Broadcom tag */
104 /* Enable Broadcom tags for IMP port */
105 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
107 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
109 /* Enable reception Broadcom tag for CPU TX (switch RX) to
110 * allow us to tag outgoing frames
112 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
114 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
116 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
117 * allow delivering frames to the per-port net_devices
119 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
121 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
123 /* Force link status for IMP port */
124 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
125 reg |= (MII_SW_OR | LINK_STS);
126 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
129 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
131 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
134 reg = core_readl(priv, CORE_EEE_EN_CTRL);
139 core_writel(priv, reg, CORE_EEE_EN_CTRL);
142 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
144 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
147 reg = reg_readl(priv, REG_SPHY_CNTRL);
150 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
151 reg_writel(priv, reg, REG_SPHY_CNTRL);
153 reg = reg_readl(priv, REG_SPHY_CNTRL);
156 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
157 reg_writel(priv, reg, REG_SPHY_CNTRL);
161 reg_writel(priv, reg, REG_SPHY_CNTRL);
163 /* Use PHY-driven LED signaling */
165 reg = reg_readl(priv, REG_LED_CNTRL(0));
166 reg |= SPDLNK_SRC_SEL;
167 reg_writel(priv, reg, REG_LED_CNTRL(0));
171 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
181 /* Port 0 interrupts are located on the first bank */
182 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
185 off = P_IRQ_OFF(port);
189 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
192 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
202 /* Port 0 interrupts are located on the first bank */
203 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
204 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
207 off = P_IRQ_OFF(port);
211 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
212 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
215 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
216 struct phy_device *phy)
218 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
219 s8 cpu_port = ds->dst[ds->index].cpu_port;
222 /* Clear the memory power down */
223 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
224 reg &= ~P_TXQ_PSM_VDD(port);
225 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
227 /* Disable learning */
228 reg = core_readl(priv, CORE_DIS_LEARN);
230 core_writel(priv, reg, CORE_DIS_LEARN);
232 /* Clear the Rx and Tx disable bits and set to no spanning tree */
233 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
235 /* Re-enable the GPHY and re-apply workarounds */
236 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
237 bcm_sf2_gphy_enable_set(ds, true);
239 /* if phy_stop() has been called before, phy
240 * will be in halted state, and phy_start()
243 * the resume path does not configure back
244 * autoneg settings, and since we hard reset
245 * the phy manually here, we need to reset the
246 * state machine also.
248 phy->state = PHY_READY;
253 /* Enable MoCA port interrupts to get notified */
254 if (port == priv->moca_port)
255 bcm_sf2_port_intr_enable(priv, port);
257 /* Set this port, and only this one to be in the default VLAN,
258 * if member of a bridge, restore its membership prior to
259 * bringing down this port.
261 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
262 reg &= ~PORT_VLAN_CTRL_MASK;
264 reg |= priv->dev->ports[port].vlan_ctl_mask;
265 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
267 bcm_sf2_imp_vlan_setup(ds, cpu_port);
269 /* If EEE was enabled, restore it */
270 if (priv->port_sts[port].eee.eee_enabled)
271 bcm_sf2_eee_enable_set(ds, port, true);
276 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
277 struct phy_device *phy)
279 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
282 if (priv->wol_ports_mask & (1 << port))
285 if (port == priv->moca_port)
286 bcm_sf2_port_intr_disable(priv, port);
288 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
289 bcm_sf2_gphy_enable_set(ds, false);
291 if (dsa_is_cpu_port(ds, port))
294 off = CORE_G_PCTL_PORT(port);
296 reg = core_readl(priv, off);
297 reg |= RX_DIS | TX_DIS;
298 core_writel(priv, reg, off);
300 /* Power down the port memory */
301 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
302 reg |= P_TXQ_PSM_VDD(port);
303 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
306 /* Returns 0 if EEE was not enabled, or 1 otherwise
308 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
309 struct phy_device *phy)
311 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
312 struct ethtool_eee *p = &priv->port_sts[port].eee;
315 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
317 ret = phy_init_eee(phy, 0);
321 bcm_sf2_eee_enable_set(ds, port, true);
326 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
327 struct ethtool_eee *e)
329 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
330 struct ethtool_eee *p = &priv->port_sts[port].eee;
333 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
334 e->eee_enabled = p->eee_enabled;
335 e->eee_active = !!(reg & (1 << port));
340 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
341 struct phy_device *phydev,
342 struct ethtool_eee *e)
344 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
345 struct ethtool_eee *p = &priv->port_sts[port].eee;
347 p->eee_enabled = e->eee_enabled;
349 if (!p->eee_enabled) {
350 bcm_sf2_eee_enable_set(ds, port, false);
352 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
360 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
366 reg = reg_readl(priv, REG_SWITCH_CNTRL);
367 reg |= MDIO_MASTER_SEL;
368 reg_writel(priv, reg, REG_SWITCH_CNTRL);
370 /* Page << 8 | offset */
373 core_writel(priv, addr, reg);
375 /* Page << 8 | offset */
376 reg = 0x80 << 8 | regnum << 1;
380 ret = core_readl(priv, reg);
382 core_writel(priv, val, reg);
384 reg = reg_readl(priv, REG_SWITCH_CNTRL);
385 reg &= ~MDIO_MASTER_SEL;
386 reg_writel(priv, reg, REG_SWITCH_CNTRL);
391 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
393 struct bcm_sf2_priv *priv = bus->priv;
395 /* Intercept reads from Broadcom pseudo-PHY address, else, send
396 * them to our master MDIO bus controller
398 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
399 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
401 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
404 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
407 struct bcm_sf2_priv *priv = bus->priv;
409 /* Intercept writes to the Broadcom pseudo-PHY address, else,
410 * send them to our master MDIO bus controller
412 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
413 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
415 return mdiobus_write_nested(priv->master_mii_bus, addr,
419 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
421 struct bcm_sf2_priv *priv = dev_id;
423 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
425 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
430 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
432 struct bcm_sf2_priv *priv = dev_id;
434 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
436 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
438 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
439 priv->port_sts[7].link = 1;
440 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
441 priv->port_sts[7].link = 0;
446 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
448 unsigned int timeout = 1000;
451 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
452 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
453 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
456 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
457 if (!(reg & SOFTWARE_RESET))
460 usleep_range(1000, 2000);
461 } while (timeout-- > 0);
469 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
471 intrl2_0_mask_set(priv, 0xffffffff);
472 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
473 intrl2_1_mask_set(priv, 0xffffffff);
474 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
477 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
478 struct device_node *dn)
480 struct device_node *port;
481 const char *phy_mode_str;
483 unsigned int port_num;
486 priv->moca_port = -1;
488 for_each_available_child_of_node(dn, port) {
489 if (of_property_read_u32(port, "reg", &port_num))
492 /* Internal PHYs get assigned a specific 'phy-mode' property
493 * value: "internal" to help flag them before MDIO probing
494 * has completed, since they might be turned off at that
497 mode = of_get_phy_mode(port);
499 ret = of_property_read_string(port, "phy-mode",
504 if (!strcasecmp(phy_mode_str, "internal"))
505 priv->int_phy_mask |= 1 << port_num;
508 if (mode == PHY_INTERFACE_MODE_MOCA)
509 priv->moca_port = port_num;
513 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
515 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
516 struct device_node *dn;
520 /* Find our integrated MDIO bus node */
521 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
522 priv->master_mii_bus = of_mdio_find_bus(dn);
523 if (!priv->master_mii_bus) {
525 return -EPROBE_DEFER;
528 get_device(&priv->master_mii_bus->dev);
529 priv->master_mii_dn = dn;
531 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
532 if (!priv->slave_mii_bus) {
537 priv->slave_mii_bus->priv = priv;
538 priv->slave_mii_bus->name = "sf2 slave mii";
539 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
540 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
541 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
543 priv->slave_mii_bus->dev.of_node = dn;
545 /* Include the pseudo-PHY address to divert reads towards our
546 * workaround. This is only required for 7445D0, since 7445E0
547 * disconnects the internal switch pseudo-PHY such that we can use the
548 * regular SWITCH_MDIO master controller instead.
550 * Here we flag the pseudo PHY as needing special treatment and would
551 * otherwise make all other PHY read/writes go to the master MDIO bus
552 * controller that comes with this switch backed by the "mdio-unimac"
555 if (of_machine_is_compatible("brcm,bcm7445d0"))
556 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
558 priv->indir_phy_mask = 0;
560 ds->phys_mii_mask = priv->indir_phy_mask;
561 ds->slave_mii_bus = priv->slave_mii_bus;
562 priv->slave_mii_bus->parent = ds->dev->parent;
563 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
566 err = of_mdiobus_register(priv->slave_mii_bus, dn);
568 err = mdiobus_register(priv->slave_mii_bus);
576 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
578 mdiobus_unregister(priv->slave_mii_bus);
579 if (priv->master_mii_dn)
580 of_node_put(priv->master_mii_dn);
583 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
585 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
587 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
588 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
589 * the REG_PHY_REVISION register layout is.
591 if (priv->int_phy_mask & BIT(port))
592 return priv->hw_params.gphy_rev;
597 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
598 struct phy_device *phydev)
600 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
601 struct ethtool_eee *p = &priv->port_sts[port].eee;
602 u32 id_mode_dis = 0, port_mode;
603 const char *str = NULL;
606 switch (phydev->interface) {
607 case PHY_INTERFACE_MODE_RGMII:
608 str = "RGMII (no delay)";
610 case PHY_INTERFACE_MODE_RGMII_TXID:
612 str = "RGMII (TX delay)";
613 port_mode = EXT_GPHY;
615 case PHY_INTERFACE_MODE_MII:
617 port_mode = EXT_EPHY;
619 case PHY_INTERFACE_MODE_REVMII:
621 port_mode = EXT_REVMII;
624 /* All other PHYs: internal and MoCA */
628 /* If the link is down, just disable the interface to conserve power */
630 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
631 reg &= ~RGMII_MODE_EN;
632 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
636 /* Clear id_mode_dis bit, and the existing port mode, but
637 * make sure we enable the RGMII block for data to pass
639 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
641 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
642 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
644 reg |= port_mode | RGMII_MODE_EN;
649 if (phydev->asym_pause)
654 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
656 pr_info("Port %d configured for %s\n", port, str);
659 /* Force link settings detected from the PHY */
661 switch (phydev->speed) {
663 reg |= SPDSTS_1000 << SPEED_SHIFT;
666 reg |= SPDSTS_100 << SPEED_SHIFT;
672 if (phydev->duplex == DUPLEX_FULL)
675 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
677 if (!phydev->is_pseudo_fixed_link)
678 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
681 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
682 struct fixed_phy_status *status)
684 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
688 duplex = core_readl(priv, CORE_DUPSTS);
689 pause = core_readl(priv, CORE_PAUSESTS);
693 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
694 * which means that we need to force the link at the port override
695 * level to get the data to flow. We do use what the interrupt handler
696 * did determine before.
698 * For the other ports, we just force the link status, since this is
699 * a fixed PHY device.
701 if (port == priv->moca_port) {
702 status->link = priv->port_sts[port].link;
703 /* For MoCA interfaces, also force a link down notification
704 * since some version of the user-space daemon (mocad) use
705 * cmd->autoneg to force the link, which messes up the PHY
706 * state machine and make it go in PHY_FORCING state instead.
709 netif_carrier_off(ds->ports[port].netdev);
713 status->duplex = !!(duplex & (1 << port));
716 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
722 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
724 if ((pause & (1 << port)) &&
725 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
726 status->asym_pause = 1;
730 if (pause & (1 << port))
734 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
736 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
739 bcm_sf2_intr_disable(priv);
741 /* Disable all ports physically present including the IMP
742 * port, the other ones have already been disabled during
745 for (port = 0; port < DSA_MAX_PORTS; port++) {
746 if ((1 << port) & ds->enabled_port_mask ||
747 dsa_is_cpu_port(ds, port))
748 bcm_sf2_port_disable(ds, port, NULL);
754 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
756 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
759 ret = bcm_sf2_sw_rst(priv);
761 pr_err("%s: failed to software reset switch\n", __func__);
765 if (priv->hw_params.num_gphy == 1)
766 bcm_sf2_gphy_enable_set(ds, true);
773 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
774 struct ethtool_wolinfo *wol)
776 struct net_device *p = ds->dst[ds->index].master_netdev;
777 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
778 struct ethtool_wolinfo pwol;
780 /* Get the parent device WoL settings */
781 p->ethtool_ops->get_wol(p, &pwol);
783 /* Advertise the parent device supported settings */
784 wol->supported = pwol.supported;
785 memset(&wol->sopass, 0, sizeof(wol->sopass));
787 if (pwol.wolopts & WAKE_MAGICSECURE)
788 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
790 if (priv->wol_ports_mask & (1 << port))
791 wol->wolopts = pwol.wolopts;
796 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
797 struct ethtool_wolinfo *wol)
799 struct net_device *p = ds->dst[ds->index].master_netdev;
800 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
801 s8 cpu_port = ds->dst[ds->index].cpu_port;
802 struct ethtool_wolinfo pwol;
804 p->ethtool_ops->get_wol(p, &pwol);
805 if (wol->wolopts & ~pwol.supported)
809 priv->wol_ports_mask |= (1 << port);
811 priv->wol_ports_mask &= ~(1 << port);
813 /* If we have at least one port enabled, make sure the CPU port
814 * is also enabled. If the CPU port is the last one enabled, we disable
815 * it since this configuration does not make sense.
817 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
818 priv->wol_ports_mask |= (1 << cpu_port);
820 priv->wol_ports_mask &= ~(1 << cpu_port);
822 return p->ethtool_ops->set_wol(p, wol);
825 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
827 unsigned int timeout = 10;
831 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
832 if (!(reg & ARLA_VTBL_STDN))
835 usleep_range(1000, 2000);
841 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
843 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
845 return bcm_sf2_vlan_op_wait(priv);
848 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
850 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
853 /* Clear all VLANs */
854 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
856 for (port = 0; port < priv->hw_params.num_ports; port++) {
857 if (!((1 << port) & ds->enabled_port_mask))
860 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
864 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
866 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
869 /* Enable all valid ports and disable those unused */
870 for (port = 0; port < priv->hw_params.num_ports; port++) {
871 /* IMP port receives special treatment */
872 if ((1 << port) & ds->enabled_port_mask)
873 bcm_sf2_port_setup(ds, port, NULL);
874 else if (dsa_is_cpu_port(ds, port))
875 bcm_sf2_imp_setup(ds, port);
877 bcm_sf2_port_disable(ds, port, NULL);
880 bcm_sf2_sw_configure_vlan(ds);
885 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
886 * register basis so we need to translate that into an address that the
887 * bus-glue understands.
889 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
891 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
894 struct bcm_sf2_priv *priv = dev->priv;
896 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
901 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
904 struct bcm_sf2_priv *priv = dev->priv;
906 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
911 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
914 struct bcm_sf2_priv *priv = dev->priv;
916 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
921 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
924 struct bcm_sf2_priv *priv = dev->priv;
926 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
931 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
934 struct bcm_sf2_priv *priv = dev->priv;
936 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
941 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
944 struct bcm_sf2_priv *priv = dev->priv;
946 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
951 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
954 struct bcm_sf2_priv *priv = dev->priv;
956 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
961 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
964 struct bcm_sf2_priv *priv = dev->priv;
966 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
971 static struct b53_io_ops bcm_sf2_io_ops = {
972 .read8 = bcm_sf2_core_read8,
973 .read16 = bcm_sf2_core_read16,
974 .read32 = bcm_sf2_core_read32,
975 .read48 = bcm_sf2_core_read64,
976 .read64 = bcm_sf2_core_read64,
977 .write8 = bcm_sf2_core_write8,
978 .write16 = bcm_sf2_core_write16,
979 .write32 = bcm_sf2_core_write32,
980 .write48 = bcm_sf2_core_write64,
981 .write64 = bcm_sf2_core_write64,
984 static int bcm_sf2_sw_probe(struct platform_device *pdev)
986 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
987 struct device_node *dn = pdev->dev.of_node;
988 struct b53_platform_data *pdata;
989 struct dsa_switch_ops *ops;
990 struct device_node *ports;
991 struct bcm_sf2_priv *priv;
992 struct b53_device *dev;
993 struct dsa_switch *ds;
1000 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1004 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1008 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1012 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1016 /* Auto-detection using standard registers will not work, so
1017 * provide an indication of what kind of device we are for
1018 * b53_common to work with
1020 pdata->chip_id = BCM7445_DEVICE_ID;
1026 /* Override the parts that are non-standard wrt. normal b53 devices */
1027 memcpy(ops, ds->ops, sizeof(*ops));
1029 ds->ops->get_tag_protocol = bcm_sf2_sw_get_tag_protocol;
1030 ds->ops->setup = bcm_sf2_sw_setup;
1031 ds->ops->get_phy_flags = bcm_sf2_sw_get_phy_flags;
1032 ds->ops->adjust_link = bcm_sf2_sw_adjust_link;
1033 ds->ops->fixed_link_update = bcm_sf2_sw_fixed_link_update;
1034 ds->ops->suspend = bcm_sf2_sw_suspend;
1035 ds->ops->resume = bcm_sf2_sw_resume;
1036 ds->ops->get_wol = bcm_sf2_sw_get_wol;
1037 ds->ops->set_wol = bcm_sf2_sw_set_wol;
1038 ds->ops->port_enable = bcm_sf2_port_setup;
1039 ds->ops->port_disable = bcm_sf2_port_disable;
1040 ds->ops->get_eee = bcm_sf2_sw_get_eee;
1041 ds->ops->set_eee = bcm_sf2_sw_set_eee;
1043 /* Avoid having DSA free our slave MDIO bus (checking for
1044 * ds->slave_mii_bus and ds->ops->phy_read being non-NULL)
1046 ds->ops->phy_read = NULL;
1048 dev_set_drvdata(&pdev->dev, priv);
1050 spin_lock_init(&priv->indir_lock);
1051 mutex_init(&priv->stats_mutex);
1053 /* Balance of_node_put() done by of_find_node_by_name() */
1055 ports = of_find_node_by_name(dn, "ports");
1057 bcm_sf2_identify_ports(priv, ports);
1061 priv->irq0 = irq_of_parse_and_map(dn, 0);
1062 priv->irq1 = irq_of_parse_and_map(dn, 1);
1065 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1066 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1067 *base = devm_ioremap_resource(&pdev->dev, r);
1068 if (IS_ERR(*base)) {
1069 pr_err("unable to find register: %s\n", reg_names[i]);
1070 return PTR_ERR(*base);
1075 ret = bcm_sf2_sw_rst(priv);
1077 pr_err("unable to software reset switch: %d\n", ret);
1081 ret = bcm_sf2_mdio_register(ds);
1083 pr_err("failed to register MDIO bus\n");
1087 /* Disable all interrupts and request them */
1088 bcm_sf2_intr_disable(priv);
1090 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1093 pr_err("failed to request switch_0 IRQ\n");
1097 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1100 pr_err("failed to request switch_1 IRQ\n");
1104 /* Reset the MIB counters */
1105 reg = core_readl(priv, CORE_GMNCFGCFG);
1107 core_writel(priv, reg, CORE_GMNCFGCFG);
1108 reg &= ~RST_MIB_CNT;
1109 core_writel(priv, reg, CORE_GMNCFGCFG);
1111 /* Get the maximum number of ports for this switch */
1112 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1113 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1114 priv->hw_params.num_ports = DSA_MAX_PORTS;
1116 /* Assume a single GPHY setup if we can't read that property */
1117 if (of_property_read_u32(dn, "brcm,num-gphy",
1118 &priv->hw_params.num_gphy))
1119 priv->hw_params.num_gphy = 1;
1121 rev = reg_readl(priv, REG_SWITCH_REVISION);
1122 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1123 SWITCH_TOP_REV_MASK;
1124 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1126 rev = reg_readl(priv, REG_PHY_REVISION);
1127 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1129 ret = b53_switch_register(dev);
1133 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1134 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1135 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1136 priv->core, priv->irq0, priv->irq1);
1141 bcm_sf2_mdio_unregister(priv);
1145 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1147 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1149 priv->wol_ports_mask = 0;
1150 dsa_unregister_switch(priv->dev->ds);
1151 /* Disable all ports and interrupts */
1152 bcm_sf2_sw_suspend(priv->dev->ds);
1153 bcm_sf2_mdio_unregister(priv);
1158 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1160 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1162 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1163 * successful MDIO bus scan to occur. If we did turn off the GPHY
1164 * before (e.g: port_disable), this will also power it back on.
1166 * Do not rely on kexec_in_progress, just power the PHY on.
1168 if (priv->hw_params.num_gphy == 1)
1169 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1172 #ifdef CONFIG_PM_SLEEP
1173 static int bcm_sf2_suspend(struct device *dev)
1175 struct platform_device *pdev = to_platform_device(dev);
1176 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1178 return dsa_switch_suspend(priv->dev->ds);
1181 static int bcm_sf2_resume(struct device *dev)
1183 struct platform_device *pdev = to_platform_device(dev);
1184 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1186 return dsa_switch_resume(priv->dev->ds);
1188 #endif /* CONFIG_PM_SLEEP */
1190 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1191 bcm_sf2_suspend, bcm_sf2_resume);
1193 static const struct of_device_id bcm_sf2_of_match[] = {
1194 { .compatible = "brcm,bcm7445-switch-v4.0" },
1197 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1199 static struct platform_driver bcm_sf2_driver = {
1200 .probe = bcm_sf2_sw_probe,
1201 .remove = bcm_sf2_sw_remove,
1202 .shutdown = bcm_sf2_sw_shutdown,
1205 .of_match_table = bcm_sf2_of_match,
1206 .pm = &bcm_sf2_pm_ops,
1209 module_platform_driver(bcm_sf2_driver);
1211 MODULE_AUTHOR("Broadcom Corporation");
1212 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1213 MODULE_LICENSE("GPL");
1214 MODULE_ALIAS("platform:brcm-sf2");