2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/phylink.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
44 /* Enable the port memories */
45 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
46 reg &= ~P_TXQ_PSM_VDD(port);
47 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
49 /* Enable forwarding */
50 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
52 /* Enable IMP port in dumb mode */
53 reg = core_readl(priv, CORE_SWITCH_CTRL);
54 reg |= MII_DUMB_FWDG_EN;
55 core_writel(priv, reg, CORE_SWITCH_CTRL);
57 /* Configure Traffic Class to QoS mapping, allow each priority to map
58 * to a different queue number
60 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
61 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
62 reg |= i << (PRT_TO_QID_SHIFT * i);
63 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
65 b53_brcm_hdr_setup(ds, port);
68 if (priv->type == BCM7445_DEVICE_ID)
69 offset = CORE_STS_OVERRIDE_IMP;
71 offset = CORE_STS_OVERRIDE_IMP2;
73 /* Force link status for IMP port */
74 reg = core_readl(priv, offset);
75 reg |= (MII_SW_OR | LINK_STS);
76 reg &= ~GMII_SPEED_UP_2G;
77 core_writel(priv, reg, offset);
79 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
80 reg = core_readl(priv, CORE_IMP_CTL);
81 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
82 reg &= ~(RX_DIS | TX_DIS);
83 core_writel(priv, reg, CORE_IMP_CTL);
85 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
86 reg &= ~(RX_DIS | TX_DIS);
87 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
91 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
93 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
96 reg = reg_readl(priv, REG_SPHY_CNTRL);
99 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
100 reg_writel(priv, reg, REG_SPHY_CNTRL);
102 reg = reg_readl(priv, REG_SPHY_CNTRL);
105 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
106 reg_writel(priv, reg, REG_SPHY_CNTRL);
110 reg_writel(priv, reg, REG_SPHY_CNTRL);
112 /* Use PHY-driven LED signaling */
114 reg = reg_readl(priv, REG_LED_CNTRL(0));
115 reg |= SPDLNK_SRC_SEL;
116 reg_writel(priv, reg, REG_LED_CNTRL(0));
120 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
130 /* Port 0 interrupts are located on the first bank */
131 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
134 off = P_IRQ_OFF(port);
138 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
141 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
151 /* Port 0 interrupts are located on the first bank */
152 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
153 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
156 off = P_IRQ_OFF(port);
160 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
161 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
164 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
165 struct phy_device *phy)
167 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
171 /* Clear the memory power down */
172 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
173 reg &= ~P_TXQ_PSM_VDD(port);
174 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
176 /* Enable Broadcom tags for that port if requested */
177 if (priv->brcm_tag_mask & BIT(port))
178 b53_brcm_hdr_setup(ds, port);
180 /* Configure Traffic Class to QoS mapping, allow each priority to map
181 * to a different queue number
183 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
184 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
185 reg |= i << (PRT_TO_QID_SHIFT * i);
186 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
188 /* Re-enable the GPHY and re-apply workarounds */
189 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
190 bcm_sf2_gphy_enable_set(ds, true);
192 /* if phy_stop() has been called before, phy
193 * will be in halted state, and phy_start()
196 * the resume path does not configure back
197 * autoneg settings, and since we hard reset
198 * the phy manually here, we need to reset the
199 * state machine also.
201 phy->state = PHY_READY;
206 /* Enable MoCA port interrupts to get notified */
207 if (port == priv->moca_port)
208 bcm_sf2_port_intr_enable(priv, port);
210 /* Set per-queue pause threshold to 32 */
211 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
213 /* Set ACB threshold to 24 */
214 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
215 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
216 SF2_NUM_EGRESS_QUEUES + i));
217 reg &= ~XOFF_THRESHOLD_MASK;
219 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
220 SF2_NUM_EGRESS_QUEUES + i));
223 return b53_enable_port(ds, port, phy);
226 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
227 struct phy_device *phy)
229 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
232 /* Disable learning while in WoL mode */
233 if (priv->wol_ports_mask & (1 << port)) {
234 reg = core_readl(priv, CORE_DIS_LEARN);
236 core_writel(priv, reg, CORE_DIS_LEARN);
240 if (port == priv->moca_port)
241 bcm_sf2_port_intr_disable(priv, port);
243 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
244 bcm_sf2_gphy_enable_set(ds, false);
246 b53_disable_port(ds, port, phy);
248 /* Power down the port memory */
249 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
250 reg |= P_TXQ_PSM_VDD(port);
251 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
255 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
261 reg = reg_readl(priv, REG_SWITCH_CNTRL);
262 reg |= MDIO_MASTER_SEL;
263 reg_writel(priv, reg, REG_SWITCH_CNTRL);
265 /* Page << 8 | offset */
268 core_writel(priv, addr, reg);
270 /* Page << 8 | offset */
271 reg = 0x80 << 8 | regnum << 1;
275 ret = core_readl(priv, reg);
277 core_writel(priv, val, reg);
279 reg = reg_readl(priv, REG_SWITCH_CNTRL);
280 reg &= ~MDIO_MASTER_SEL;
281 reg_writel(priv, reg, REG_SWITCH_CNTRL);
286 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
288 struct bcm_sf2_priv *priv = bus->priv;
290 /* Intercept reads from Broadcom pseudo-PHY address, else, send
291 * them to our master MDIO bus controller
293 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
294 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
296 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
299 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
302 struct bcm_sf2_priv *priv = bus->priv;
304 /* Intercept writes to the Broadcom pseudo-PHY address, else,
305 * send them to our master MDIO bus controller
307 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
308 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
310 return mdiobus_write_nested(priv->master_mii_bus, addr,
314 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
316 struct dsa_switch *ds = dev_id;
317 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
319 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
321 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
326 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
328 struct dsa_switch *ds = dev_id;
329 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
331 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
333 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
335 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
336 priv->port_sts[7].link = true;
337 dsa_port_phylink_mac_change(ds, 7, true);
339 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
340 priv->port_sts[7].link = false;
341 dsa_port_phylink_mac_change(ds, 7, false);
347 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
349 unsigned int timeout = 1000;
352 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
353 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
354 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
357 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
358 if (!(reg & SOFTWARE_RESET))
361 usleep_range(1000, 2000);
362 } while (timeout-- > 0);
370 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
372 intrl2_0_mask_set(priv, 0xffffffff);
373 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
374 intrl2_1_mask_set(priv, 0xffffffff);
375 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
378 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
379 struct device_node *dn)
381 struct device_node *port;
383 unsigned int port_num;
385 priv->moca_port = -1;
387 for_each_available_child_of_node(dn, port) {
388 if (of_property_read_u32(port, "reg", &port_num))
391 /* Internal PHYs get assigned a specific 'phy-mode' property
392 * value: "internal" to help flag them before MDIO probing
393 * has completed, since they might be turned off at that
396 mode = of_get_phy_mode(port);
400 if (mode == PHY_INTERFACE_MODE_INTERNAL)
401 priv->int_phy_mask |= 1 << port_num;
403 if (mode == PHY_INTERFACE_MODE_MOCA)
404 priv->moca_port = port_num;
406 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
407 priv->brcm_tag_mask |= 1 << port_num;
411 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
413 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
414 struct device_node *dn;
418 /* Find our integrated MDIO bus node */
419 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
420 priv->master_mii_bus = of_mdio_find_bus(dn);
421 if (!priv->master_mii_bus) {
423 return -EPROBE_DEFER;
426 get_device(&priv->master_mii_bus->dev);
427 priv->master_mii_dn = dn;
429 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
430 if (!priv->slave_mii_bus) {
435 priv->slave_mii_bus->priv = priv;
436 priv->slave_mii_bus->name = "sf2 slave mii";
437 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
438 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
439 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
441 priv->slave_mii_bus->dev.of_node = dn;
443 /* Include the pseudo-PHY address to divert reads towards our
444 * workaround. This is only required for 7445D0, since 7445E0
445 * disconnects the internal switch pseudo-PHY such that we can use the
446 * regular SWITCH_MDIO master controller instead.
448 * Here we flag the pseudo PHY as needing special treatment and would
449 * otherwise make all other PHY read/writes go to the master MDIO bus
450 * controller that comes with this switch backed by the "mdio-unimac"
453 if (of_machine_is_compatible("brcm,bcm7445d0"))
454 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
456 priv->indir_phy_mask = 0;
458 ds->phys_mii_mask = priv->indir_phy_mask;
459 ds->slave_mii_bus = priv->slave_mii_bus;
460 priv->slave_mii_bus->parent = ds->dev->parent;
461 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
463 err = mdiobus_register(priv->slave_mii_bus);
470 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
472 mdiobus_unregister(priv->slave_mii_bus);
473 if (priv->master_mii_dn)
474 of_node_put(priv->master_mii_dn);
477 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
479 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
481 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
482 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
483 * the REG_PHY_REVISION register layout is.
485 if (priv->int_phy_mask & BIT(port))
486 return priv->hw_params.gphy_rev;
491 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
492 unsigned long *supported,
493 struct phylink_link_state *state)
495 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
497 if (!phy_interface_mode_is_rgmii(state->interface) &&
498 state->interface != PHY_INTERFACE_MODE_MII &&
499 state->interface != PHY_INTERFACE_MODE_REVMII &&
500 state->interface != PHY_INTERFACE_MODE_GMII &&
501 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
502 state->interface != PHY_INTERFACE_MODE_MOCA) {
503 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
505 "Unsupported interface: %d\n", state->interface);
509 /* Allow all the expected bits */
510 phylink_set(mask, Autoneg);
511 phylink_set_port_modes(mask);
512 phylink_set(mask, Pause);
513 phylink_set(mask, Asym_Pause);
515 /* With the exclusion of MII and Reverse MII, we support Gigabit,
516 * including Half duplex
518 if (state->interface != PHY_INTERFACE_MODE_MII &&
519 state->interface != PHY_INTERFACE_MODE_REVMII) {
520 phylink_set(mask, 1000baseT_Full);
521 phylink_set(mask, 1000baseT_Half);
524 phylink_set(mask, 10baseT_Half);
525 phylink_set(mask, 10baseT_Full);
526 phylink_set(mask, 100baseT_Half);
527 phylink_set(mask, 100baseT_Full);
529 bitmap_and(supported, supported, mask,
530 __ETHTOOL_LINK_MODE_MASK_NBITS);
531 bitmap_and(state->advertising, state->advertising, mask,
532 __ETHTOOL_LINK_MODE_MASK_NBITS);
535 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
537 const struct phylink_link_state *state)
539 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
540 u32 id_mode_dis = 0, port_mode;
543 if (priv->type == BCM7445_DEVICE_ID)
544 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
546 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
548 switch (state->interface) {
549 case PHY_INTERFACE_MODE_RGMII:
552 case PHY_INTERFACE_MODE_RGMII_TXID:
553 port_mode = EXT_GPHY;
555 case PHY_INTERFACE_MODE_MII:
556 port_mode = EXT_EPHY;
558 case PHY_INTERFACE_MODE_REVMII:
559 port_mode = EXT_REVMII;
562 /* all other PHYs: internal and MoCA */
566 /* Clear id_mode_dis bit, and the existing port mode, let
567 * RGMII_MODE_EN bet set by mac_link_{up,down}
569 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
571 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
572 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
578 if (state->pause & MLO_PAUSE_TXRX_MASK) {
579 if (state->pause & MLO_PAUSE_TX)
584 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
587 /* Force link settings detected from the PHY */
589 switch (state->speed) {
591 reg |= SPDSTS_1000 << SPEED_SHIFT;
594 reg |= SPDSTS_100 << SPEED_SHIFT;
600 if (state->duplex == DUPLEX_FULL)
603 core_writel(priv, reg, offset);
606 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
607 phy_interface_t interface, bool link)
609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
612 if (!phy_interface_mode_is_rgmii(interface) &&
613 interface != PHY_INTERFACE_MODE_MII &&
614 interface != PHY_INTERFACE_MODE_REVMII)
617 /* If the link is down, just disable the interface to conserve power */
618 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
620 reg |= RGMII_MODE_EN;
622 reg &= ~RGMII_MODE_EN;
623 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
626 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
628 phy_interface_t interface)
630 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
633 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
635 phy_interface_t interface,
636 struct phy_device *phydev)
638 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
639 struct ethtool_eee *p = &priv->dev->ports[port].eee;
641 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
643 if (mode == MLO_AN_PHY && phydev)
644 p->eee_enabled = b53_eee_init(ds, port, phydev);
647 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
648 struct phylink_link_state *status)
650 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
652 status->link = false;
654 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
655 * which means that we need to force the link at the port override
656 * level to get the data to flow. We do use what the interrupt handler
657 * did determine before.
659 * For the other ports, we just force the link status, since this is
660 * a fixed PHY device.
662 if (port == priv->moca_port) {
663 status->link = priv->port_sts[port].link;
664 /* For MoCA interfaces, also force a link down notification
665 * since some version of the user-space daemon (mocad) use
666 * cmd->autoneg to force the link, which messes up the PHY
667 * state machine and make it go in PHY_FORCING state instead.
670 netif_carrier_off(ds->ports[port].slave);
671 status->duplex = DUPLEX_FULL;
677 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
679 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
682 /* Enable ACB globally */
683 reg = acb_readl(priv, ACB_CONTROL);
684 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
685 acb_writel(priv, reg, ACB_CONTROL);
686 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
687 reg |= ACB_EN | ACB_ALGORITHM;
688 acb_writel(priv, reg, ACB_CONTROL);
691 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
693 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
696 bcm_sf2_intr_disable(priv);
698 /* Disable all ports physically present including the IMP
699 * port, the other ones have already been disabled during
702 for (port = 0; port < ds->num_ports; port++) {
703 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
704 bcm_sf2_port_disable(ds, port, NULL);
710 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
712 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
715 ret = bcm_sf2_sw_rst(priv);
717 pr_err("%s: failed to software reset switch\n", __func__);
721 if (priv->hw_params.num_gphy == 1)
722 bcm_sf2_gphy_enable_set(ds, true);
729 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
730 struct ethtool_wolinfo *wol)
732 struct net_device *p = ds->ports[port].cpu_dp->master;
733 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
734 struct ethtool_wolinfo pwol = { };
736 /* Get the parent device WoL settings */
737 if (p->ethtool_ops->get_wol)
738 p->ethtool_ops->get_wol(p, &pwol);
740 /* Advertise the parent device supported settings */
741 wol->supported = pwol.supported;
742 memset(&wol->sopass, 0, sizeof(wol->sopass));
744 if (pwol.wolopts & WAKE_MAGICSECURE)
745 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
747 if (priv->wol_ports_mask & (1 << port))
748 wol->wolopts = pwol.wolopts;
753 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
754 struct ethtool_wolinfo *wol)
756 struct net_device *p = ds->ports[port].cpu_dp->master;
757 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
758 s8 cpu_port = ds->ports[port].cpu_dp->index;
759 struct ethtool_wolinfo pwol = { };
761 if (p->ethtool_ops->get_wol)
762 p->ethtool_ops->get_wol(p, &pwol);
763 if (wol->wolopts & ~pwol.supported)
767 priv->wol_ports_mask |= (1 << port);
769 priv->wol_ports_mask &= ~(1 << port);
771 /* If we have at least one port enabled, make sure the CPU port
772 * is also enabled. If the CPU port is the last one enabled, we disable
773 * it since this configuration does not make sense.
775 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
776 priv->wol_ports_mask |= (1 << cpu_port);
778 priv->wol_ports_mask &= ~(1 << cpu_port);
780 return p->ethtool_ops->set_wol(p, wol);
783 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
785 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
788 /* Enable all valid ports and disable those unused */
789 for (port = 0; port < priv->hw_params.num_ports; port++) {
790 /* IMP port receives special treatment */
791 if (dsa_is_user_port(ds, port))
792 bcm_sf2_port_setup(ds, port, NULL);
793 else if (dsa_is_cpu_port(ds, port))
794 bcm_sf2_imp_setup(ds, port);
796 bcm_sf2_port_disable(ds, port, NULL);
799 b53_configure_vlan(ds);
800 bcm_sf2_enable_acb(ds);
805 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
806 * register basis so we need to translate that into an address that the
807 * bus-glue understands.
809 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
811 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
814 struct bcm_sf2_priv *priv = dev->priv;
816 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
821 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
824 struct bcm_sf2_priv *priv = dev->priv;
826 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
831 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
834 struct bcm_sf2_priv *priv = dev->priv;
836 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
841 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
844 struct bcm_sf2_priv *priv = dev->priv;
846 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
851 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
854 struct bcm_sf2_priv *priv = dev->priv;
856 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
861 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
864 struct bcm_sf2_priv *priv = dev->priv;
866 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
871 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
874 struct bcm_sf2_priv *priv = dev->priv;
876 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
881 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
884 struct bcm_sf2_priv *priv = dev->priv;
886 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
891 static const struct b53_io_ops bcm_sf2_io_ops = {
892 .read8 = bcm_sf2_core_read8,
893 .read16 = bcm_sf2_core_read16,
894 .read32 = bcm_sf2_core_read32,
895 .read48 = bcm_sf2_core_read64,
896 .read64 = bcm_sf2_core_read64,
897 .write8 = bcm_sf2_core_write8,
898 .write16 = bcm_sf2_core_write16,
899 .write32 = bcm_sf2_core_write32,
900 .write48 = bcm_sf2_core_write64,
901 .write64 = bcm_sf2_core_write64,
904 static const struct dsa_switch_ops bcm_sf2_ops = {
905 .get_tag_protocol = b53_get_tag_protocol,
906 .setup = bcm_sf2_sw_setup,
907 .get_strings = b53_get_strings,
908 .get_ethtool_stats = b53_get_ethtool_stats,
909 .get_sset_count = b53_get_sset_count,
910 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
911 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
912 .phylink_validate = bcm_sf2_sw_validate,
913 .phylink_mac_config = bcm_sf2_sw_mac_config,
914 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
915 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
916 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
917 .suspend = bcm_sf2_sw_suspend,
918 .resume = bcm_sf2_sw_resume,
919 .get_wol = bcm_sf2_sw_get_wol,
920 .set_wol = bcm_sf2_sw_set_wol,
921 .port_enable = bcm_sf2_port_setup,
922 .port_disable = bcm_sf2_port_disable,
923 .get_mac_eee = b53_get_mac_eee,
924 .set_mac_eee = b53_set_mac_eee,
925 .port_bridge_join = b53_br_join,
926 .port_bridge_leave = b53_br_leave,
927 .port_stp_state_set = b53_br_set_stp_state,
928 .port_fast_age = b53_br_fast_age,
929 .port_vlan_filtering = b53_vlan_filtering,
930 .port_vlan_prepare = b53_vlan_prepare,
931 .port_vlan_add = b53_vlan_add,
932 .port_vlan_del = b53_vlan_del,
933 .port_fdb_dump = b53_fdb_dump,
934 .port_fdb_add = b53_fdb_add,
935 .port_fdb_del = b53_fdb_del,
936 .get_rxnfc = bcm_sf2_get_rxnfc,
937 .set_rxnfc = bcm_sf2_set_rxnfc,
938 .port_mirror_add = b53_mirror_add,
939 .port_mirror_del = b53_mirror_del,
942 struct bcm_sf2_of_data {
944 const u16 *reg_offsets;
945 unsigned int core_reg_align;
946 unsigned int num_cfp_rules;
949 /* Register offsets for the SWITCH_REG_* block */
950 static const u16 bcm_sf2_7445_reg_offsets[] = {
951 [REG_SWITCH_CNTRL] = 0x00,
952 [REG_SWITCH_STATUS] = 0x04,
953 [REG_DIR_DATA_WRITE] = 0x08,
954 [REG_DIR_DATA_READ] = 0x0C,
955 [REG_SWITCH_REVISION] = 0x18,
956 [REG_PHY_REVISION] = 0x1C,
957 [REG_SPHY_CNTRL] = 0x2C,
958 [REG_RGMII_0_CNTRL] = 0x34,
959 [REG_RGMII_1_CNTRL] = 0x40,
960 [REG_RGMII_2_CNTRL] = 0x4c,
961 [REG_LED_0_CNTRL] = 0x90,
962 [REG_LED_1_CNTRL] = 0x94,
963 [REG_LED_2_CNTRL] = 0x98,
966 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
967 .type = BCM7445_DEVICE_ID,
969 .reg_offsets = bcm_sf2_7445_reg_offsets,
970 .num_cfp_rules = 256,
973 static const u16 bcm_sf2_7278_reg_offsets[] = {
974 [REG_SWITCH_CNTRL] = 0x00,
975 [REG_SWITCH_STATUS] = 0x04,
976 [REG_DIR_DATA_WRITE] = 0x08,
977 [REG_DIR_DATA_READ] = 0x0c,
978 [REG_SWITCH_REVISION] = 0x10,
979 [REG_PHY_REVISION] = 0x14,
980 [REG_SPHY_CNTRL] = 0x24,
981 [REG_RGMII_0_CNTRL] = 0xe0,
982 [REG_RGMII_1_CNTRL] = 0xec,
983 [REG_RGMII_2_CNTRL] = 0xf8,
984 [REG_LED_0_CNTRL] = 0x40,
985 [REG_LED_1_CNTRL] = 0x4c,
986 [REG_LED_2_CNTRL] = 0x58,
989 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
990 .type = BCM7278_DEVICE_ID,
992 .reg_offsets = bcm_sf2_7278_reg_offsets,
993 .num_cfp_rules = 128,
996 static const struct of_device_id bcm_sf2_of_match[] = {
997 { .compatible = "brcm,bcm7445-switch-v4.0",
998 .data = &bcm_sf2_7445_data
1000 { .compatible = "brcm,bcm7278-switch-v4.0",
1001 .data = &bcm_sf2_7278_data
1003 { .compatible = "brcm,bcm7278-switch-v4.8",
1004 .data = &bcm_sf2_7278_data
1008 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1010 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1012 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1013 struct device_node *dn = pdev->dev.of_node;
1014 const struct of_device_id *of_id = NULL;
1015 const struct bcm_sf2_of_data *data;
1016 struct b53_platform_data *pdata;
1017 struct dsa_switch_ops *ops;
1018 struct device_node *ports;
1019 struct bcm_sf2_priv *priv;
1020 struct b53_device *dev;
1021 struct dsa_switch *ds;
1022 void __iomem **base;
1028 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1032 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1036 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1040 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1044 of_id = of_match_node(bcm_sf2_of_match, dn);
1045 if (!of_id || !of_id->data)
1050 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1051 priv->type = data->type;
1052 priv->reg_offsets = data->reg_offsets;
1053 priv->core_reg_align = data->core_reg_align;
1054 priv->num_cfp_rules = data->num_cfp_rules;
1056 /* Auto-detection using standard registers will not work, so
1057 * provide an indication of what kind of device we are for
1058 * b53_common to work with
1060 pdata->chip_id = priv->type;
1065 ds->ops = &bcm_sf2_ops;
1067 /* Advertise the 8 egress queues */
1068 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1070 dev_set_drvdata(&pdev->dev, priv);
1072 spin_lock_init(&priv->indir_lock);
1073 mutex_init(&priv->stats_mutex);
1074 mutex_init(&priv->cfp.lock);
1076 /* CFP rule #0 cannot be used for specific classifications, flag it as
1079 set_bit(0, priv->cfp.used);
1080 set_bit(0, priv->cfp.unique);
1082 /* Balance of_node_put() done by of_find_node_by_name() */
1084 ports = of_find_node_by_name(dn, "ports");
1086 bcm_sf2_identify_ports(priv, ports);
1090 priv->irq0 = irq_of_parse_and_map(dn, 0);
1091 priv->irq1 = irq_of_parse_and_map(dn, 1);
1094 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1095 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1096 *base = devm_ioremap_resource(&pdev->dev, r);
1097 if (IS_ERR(*base)) {
1098 pr_err("unable to find register: %s\n", reg_names[i]);
1099 return PTR_ERR(*base);
1104 ret = bcm_sf2_sw_rst(priv);
1106 pr_err("unable to software reset switch: %d\n", ret);
1110 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1112 ret = bcm_sf2_mdio_register(ds);
1114 pr_err("failed to register MDIO bus\n");
1118 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1120 ret = bcm_sf2_cfp_rst(priv);
1122 pr_err("failed to reset CFP\n");
1126 /* Disable all interrupts and request them */
1127 bcm_sf2_intr_disable(priv);
1129 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1132 pr_err("failed to request switch_0 IRQ\n");
1136 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1139 pr_err("failed to request switch_1 IRQ\n");
1143 /* Reset the MIB counters */
1144 reg = core_readl(priv, CORE_GMNCFGCFG);
1146 core_writel(priv, reg, CORE_GMNCFGCFG);
1147 reg &= ~RST_MIB_CNT;
1148 core_writel(priv, reg, CORE_GMNCFGCFG);
1150 /* Get the maximum number of ports for this switch */
1151 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1152 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1153 priv->hw_params.num_ports = DSA_MAX_PORTS;
1155 /* Assume a single GPHY setup if we can't read that property */
1156 if (of_property_read_u32(dn, "brcm,num-gphy",
1157 &priv->hw_params.num_gphy))
1158 priv->hw_params.num_gphy = 1;
1160 rev = reg_readl(priv, REG_SWITCH_REVISION);
1161 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1162 SWITCH_TOP_REV_MASK;
1163 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1165 rev = reg_readl(priv, REG_PHY_REVISION);
1166 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1168 ret = b53_switch_register(dev);
1172 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1173 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1174 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1175 priv->core, priv->irq0, priv->irq1);
1180 bcm_sf2_mdio_unregister(priv);
1184 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1186 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1188 priv->wol_ports_mask = 0;
1189 dsa_unregister_switch(priv->dev->ds);
1190 /* Disable all ports and interrupts */
1191 bcm_sf2_sw_suspend(priv->dev->ds);
1192 bcm_sf2_mdio_unregister(priv);
1197 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1199 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1201 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1202 * successful MDIO bus scan to occur. If we did turn off the GPHY
1203 * before (e.g: port_disable), this will also power it back on.
1205 * Do not rely on kexec_in_progress, just power the PHY on.
1207 if (priv->hw_params.num_gphy == 1)
1208 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1211 #ifdef CONFIG_PM_SLEEP
1212 static int bcm_sf2_suspend(struct device *dev)
1214 struct platform_device *pdev = to_platform_device(dev);
1215 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1217 return dsa_switch_suspend(priv->dev->ds);
1220 static int bcm_sf2_resume(struct device *dev)
1222 struct platform_device *pdev = to_platform_device(dev);
1223 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1225 return dsa_switch_resume(priv->dev->ds);
1227 #endif /* CONFIG_PM_SLEEP */
1229 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1230 bcm_sf2_suspend, bcm_sf2_resume);
1233 static struct platform_driver bcm_sf2_driver = {
1234 .probe = bcm_sf2_sw_probe,
1235 .remove = bcm_sf2_sw_remove,
1236 .shutdown = bcm_sf2_sw_shutdown,
1239 .of_match_table = bcm_sf2_of_match,
1240 .pm = &bcm_sf2_pm_ops,
1243 module_platform_driver(bcm_sf2_driver);
1245 MODULE_AUTHOR("Broadcom Corporation");
1246 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1247 MODULE_LICENSE("GPL");
1248 MODULE_ALIAS("platform:brcm-sf2");