drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/export.h>
  22 #include <linux/gpio.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_data/b53.h>
  26 #include <linux/phy.h>
  27 #include <linux/phylink.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/if_bridge.h>
  30 #include <net/dsa.h>
  31
  32 #include "b53_regs.h"
  33 #include "b53_priv.h"
  34
  35 struct b53_mib_desc {
  36         u8 size;
  37         u8 offset;
  38         const char *name;
  39 };
  40
  41 /* BCM5365 MIB counters */
  42 static const struct b53_mib_desc b53_mibs_65[] = {
  43         { 8, 0x00, "TxOctets" },
  44         { 4, 0x08, "TxDropPkts" },
  45         { 4, 0x10, "TxBroadcastPkts" },
  46         { 4, 0x14, "TxMulticastPkts" },
  47         { 4, 0x18, "TxUnicastPkts" },
  48         { 4, 0x1c, "TxCollisions" },
  49         { 4, 0x20, "TxSingleCollision" },
  50         { 4, 0x24, "TxMultipleCollision" },
  51         { 4, 0x28, "TxDeferredTransmit" },
  52         { 4, 0x2c, "TxLateCollision" },
  53         { 4, 0x30, "TxExcessiveCollision" },
  54         { 4, 0x38, "TxPausePkts" },
  55         { 8, 0x44, "RxOctets" },
  56         { 4, 0x4c, "RxUndersizePkts" },
  57         { 4, 0x50, "RxPausePkts" },
  58         { 4, 0x54, "Pkts64Octets" },
  59         { 4, 0x58, "Pkts65to127Octets" },
  60         { 4, 0x5c, "Pkts128to255Octets" },
  61         { 4, 0x60, "Pkts256to511Octets" },
  62         { 4, 0x64, "Pkts512to1023Octets" },
  63         { 4, 0x68, "Pkts1024to1522Octets" },
  64         { 4, 0x6c, "RxOversizePkts" },
  65         { 4, 0x70, "RxJabbers" },
  66         { 4, 0x74, "RxAlignmentErrors" },
  67         { 4, 0x78, "RxFCSErrors" },
  68         { 8, 0x7c, "RxGoodOctets" },
  69         { 4, 0x84, "RxDropPkts" },
  70         { 4, 0x88, "RxUnicastPkts" },
  71         { 4, 0x8c, "RxMulticastPkts" },
  72         { 4, 0x90, "RxBroadcastPkts" },
  73         { 4, 0x94, "RxSAChanges" },
  74         { 4, 0x98, "RxFragments" },
  75 };
  76
  77 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  78
  79 /* BCM63xx MIB counters */
  80 static const struct b53_mib_desc b53_mibs_63xx[] = {
  81         { 8, 0x00, "TxOctets" },
  82         { 4, 0x08, "TxDropPkts" },
  83         { 4, 0x0c, "TxQoSPkts" },
  84         { 4, 0x10, "TxBroadcastPkts" },
  85         { 4, 0x14, "TxMulticastPkts" },
  86         { 4, 0x18, "TxUnicastPkts" },
  87         { 4, 0x1c, "TxCollisions" },
  88         { 4, 0x20, "TxSingleCollision" },
  89         { 4, 0x24, "TxMultipleCollision" },
  90         { 4, 0x28, "TxDeferredTransmit" },
  91         { 4, 0x2c, "TxLateCollision" },
  92         { 4, 0x30, "TxExcessiveCollision" },
  93         { 4, 0x38, "TxPausePkts" },
  94         { 8, 0x3c, "TxQoSOctets" },
  95         { 8, 0x44, "RxOctets" },
  96         { 4, 0x4c, "RxUndersizePkts" },
  97         { 4, 0x50, "RxPausePkts" },
  98         { 4, 0x54, "Pkts64Octets" },
  99         { 4, 0x58, "Pkts65to127Octets" },
 100         { 4, 0x5c, "Pkts128to255Octets" },
 101         { 4, 0x60, "Pkts256to511Octets" },
 102         { 4, 0x64, "Pkts512to1023Octets" },
 103         { 4, 0x68, "Pkts1024to1522Octets" },
 104         { 4, 0x6c, "RxOversizePkts" },
 105         { 4, 0x70, "RxJabbers" },
 106         { 4, 0x74, "RxAlignmentErrors" },
 107         { 4, 0x78, "RxFCSErrors" },
 108         { 8, 0x7c, "RxGoodOctets" },
 109         { 4, 0x84, "RxDropPkts" },
 110         { 4, 0x88, "RxUnicastPkts" },
 111         { 4, 0x8c, "RxMulticastPkts" },
 112         { 4, 0x90, "RxBroadcastPkts" },
 113         { 4, 0x94, "RxSAChanges" },
 114         { 4, 0x98, "RxFragments" },
 115         { 4, 0xa0, "RxSymbolErrors" },
 116         { 4, 0xa4, "RxQoSPkts" },
 117         { 8, 0xa8, "RxQoSOctets" },
 118         { 4, 0xb0, "Pkts1523to2047Octets" },
 119         { 4, 0xb4, "Pkts2048to4095Octets" },
 120         { 4, 0xb8, "Pkts4096to8191Octets" },
 121         { 4, 0xbc, "Pkts8192to9728Octets" },
 122         { 4, 0xc0, "RxDiscarded" },
 123 };
 124
 125 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 126
 127 /* MIB counters */
 128 static const struct b53_mib_desc b53_mibs[] = {
 129         { 8, 0x00, "TxOctets" },
 130         { 4, 0x08, "TxDropPkts" },
 131         { 4, 0x10, "TxBroadcastPkts" },
 132         { 4, 0x14, "TxMulticastPkts" },
 133         { 4, 0x18, "TxUnicastPkts" },
 134         { 4, 0x1c, "TxCollisions" },
 135         { 4, 0x20, "TxSingleCollision" },
 136         { 4, 0x24, "TxMultipleCollision" },
 137         { 4, 0x28, "TxDeferredTransmit" },
 138         { 4, 0x2c, "TxLateCollision" },
 139         { 4, 0x30, "TxExcessiveCollision" },
 140         { 4, 0x38, "TxPausePkts" },
 141         { 8, 0x50, "RxOctets" },
 142         { 4, 0x58, "RxUndersizePkts" },
 143         { 4, 0x5c, "RxPausePkts" },
 144         { 4, 0x60, "Pkts64Octets" },
 145         { 4, 0x64, "Pkts65to127Octets" },
 146         { 4, 0x68, "Pkts128to255Octets" },
 147         { 4, 0x6c, "Pkts256to511Octets" },
 148         { 4, 0x70, "Pkts512to1023Octets" },
 149         { 4, 0x74, "Pkts1024to1522Octets" },
 150         { 4, 0x78, "RxOversizePkts" },
 151         { 4, 0x7c, "RxJabbers" },
 152         { 4, 0x80, "RxAlignmentErrors" },
 153         { 4, 0x84, "RxFCSErrors" },
 154         { 8, 0x88, "RxGoodOctets" },
 155         { 4, 0x90, "RxDropPkts" },
 156         { 4, 0x94, "RxUnicastPkts" },
 157         { 4, 0x98, "RxMulticastPkts" },
 158         { 4, 0x9c, "RxBroadcastPkts" },
 159         { 4, 0xa0, "RxSAChanges" },
 160         { 4, 0xa4, "RxFragments" },
 161         { 4, 0xa8, "RxJumboPkts" },
 162         { 4, 0xac, "RxSymbolErrors" },
 163         { 4, 0xc0, "RxDiscarded" },
 164 };
 165
 166 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 167
 168 static const struct b53_mib_desc b53_mibs_58xx[] = {
 169         { 8, 0x00, "TxOctets" },
 170         { 4, 0x08, "TxDropPkts" },
 171         { 4, 0x0c, "TxQPKTQ0" },
 172         { 4, 0x10, "TxBroadcastPkts" },
 173         { 4, 0x14, "TxMulticastPkts" },
 174         { 4, 0x18, "TxUnicastPKts" },
 175         { 4, 0x1c, "TxCollisions" },
 176         { 4, 0x20, "TxSingleCollision" },
 177         { 4, 0x24, "TxMultipleCollision" },
 178         { 4, 0x28, "TxDeferredCollision" },
 179         { 4, 0x2c, "TxLateCollision" },
 180         { 4, 0x30, "TxExcessiveCollision" },
 181         { 4, 0x34, "TxFrameInDisc" },
 182         { 4, 0x38, "TxPausePkts" },
 183         { 4, 0x3c, "TxQPKTQ1" },
 184         { 4, 0x40, "TxQPKTQ2" },
 185         { 4, 0x44, "TxQPKTQ3" },
 186         { 4, 0x48, "TxQPKTQ4" },
 187         { 4, 0x4c, "TxQPKTQ5" },
 188         { 8, 0x50, "RxOctets" },
 189         { 4, 0x58, "RxUndersizePkts" },
 190         { 4, 0x5c, "RxPausePkts" },
 191         { 4, 0x60, "RxPkts64Octets" },
 192         { 4, 0x64, "RxPkts65to127Octets" },
 193         { 4, 0x68, "RxPkts128to255Octets" },
 194         { 4, 0x6c, "RxPkts256to511Octets" },
 195         { 4, 0x70, "RxPkts512to1023Octets" },
 196         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 197         { 4, 0x78, "RxOversizePkts" },
 198         { 4, 0x7c, "RxJabbers" },
 199         { 4, 0x80, "RxAlignmentErrors" },
 200         { 4, 0x84, "RxFCSErrors" },
 201         { 8, 0x88, "RxGoodOctets" },
 202         { 4, 0x90, "RxDropPkts" },
 203         { 4, 0x94, "RxUnicastPkts" },
 204         { 4, 0x98, "RxMulticastPkts" },
 205         { 4, 0x9c, "RxBroadcastPkts" },
 206         { 4, 0xa0, "RxSAChanges" },
 207         { 4, 0xa4, "RxFragments" },
 208         { 4, 0xa8, "RxJumboPkt" },
 209         { 4, 0xac, "RxSymblErr" },
 210         { 4, 0xb0, "InRangeErrCount" },
 211         { 4, 0xb4, "OutRangeErrCount" },
 212         { 4, 0xb8, "EEELpiEvent" },
 213         { 4, 0xbc, "EEELpiDuration" },
 214         { 4, 0xc0, "RxDiscard" },
 215         { 4, 0xc8, "TxQPKTQ6" },
 216         { 4, 0xcc, "TxQPKTQ7" },
 217         { 4, 0xd0, "TxPkts64Octets" },
 218         { 4, 0xd4, "TxPkts65to127Octets" },
 219         { 4, 0xd8, "TxPkts128to255Octets" },
 220         { 4, 0xdc, "TxPkts256to511Ocets" },
 221         { 4, 0xe0, "TxPkts512to1023Ocets" },
 222         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 223 };
 224
 225 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 226
 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 228 {
 229         unsigned int i;
 230
 231         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 232
 233         for (i = 0; i < 10; i++) {
 234                 u8 vta;
 235
 236                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 237                 if (!(vta & VTA_START_CMD))
 238                         return 0;
 239
 240                 usleep_range(100, 200);
 241         }
 242
 243         return -EIO;
 244 }
 245
 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 247                                struct b53_vlan *vlan)
 248 {
 249         if (is5325(dev)) {
 250                 u32 entry = 0;
 251
 252                 if (vlan->members) {
 253                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 254                                  VA_UNTAG_S_25) | vlan->members;
 255                         if (dev->core_rev >= 3)
 256                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 257                         else
 258                                 entry |= VA_VALID_25;
 259                 }
 260
 261                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 262                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 263                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 264         } else if (is5365(dev)) {
 265                 u16 entry = 0;
 266
 267                 if (vlan->members)
 268                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 269                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 270
 271                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 272                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 273                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 274         } else {
 275                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 276                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 277                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 278
 279                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 280         }
 281
 282         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 283                 vid, vlan->members, vlan->untag);
 284 }
 285
 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 287                                struct b53_vlan *vlan)
 288 {
 289         if (is5325(dev)) {
 290                 u32 entry = 0;
 291
 292                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 293                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 294                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 295
 296                 if (dev->core_rev >= 3)
 297                         vlan->valid = !!(entry & VA_VALID_25_R4);
 298                 else
 299                         vlan->valid = !!(entry & VA_VALID_25);
 300                 vlan->members = entry & VA_MEMBER_MASK;
 301                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 302
 303         } else if (is5365(dev)) {
 304                 u16 entry = 0;
 305
 306                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 307                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 308                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 309
 310                 vlan->valid = !!(entry & VA_VALID_65);
 311                 vlan->members = entry & VA_MEMBER_MASK;
 312                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 313         } else {
 314                 u32 entry = 0;
 315
 316                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 317                 b53_do_vlan_op(dev, VTA_CMD_READ);
 318                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 319                 vlan->members = entry & VTE_MEMBERS;
 320                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 321                 vlan->valid = true;
 322         }
 323 }
 324
 325 static void b53_set_forwarding(struct b53_device *dev, int enable)
 326 {
 327         u8 mgmt;
 328
 329         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 330
 331         if (enable)
 332                 mgmt |= SM_SW_FWD_EN;
 333         else
 334                 mgmt &= ~SM_SW_FWD_EN;
 335
 336         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 337
 338         /* Include IMP port in dumb forwarding mode
 339          */
 340         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 341         mgmt |= B53_MII_DUMB_FWDG_EN;
 342         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 343
 344         /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
 345          * frames should be flooded or not.
 346          */
 347         b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
 348         mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
 349         b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
 350 }
 351
 352 static void b53_enable_vlan(struct b53_device *dev, bool enable,
 353                             bool enable_filtering)
 354 {
 355         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 356
 357         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 358         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 359         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 360
 361         if (is5325(dev) || is5365(dev)) {
 362                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 364         } else if (is63xx(dev)) {
 365                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 366                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 367         } else {
 368                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 369                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 370         }
 371
 372         if (enable) {
 373                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 374                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 375                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 376                 if (enable_filtering) {
 377                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 378                         vc5 |= VC5_DROP_VTABLE_MISS;
 379                 } else {
 380                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 381                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 382                 }
 383
 384                 if (is5325(dev))
 385                         vc0 &= ~VC0_RESERVED_1;
 386
 387                 if (is5325(dev) || is5365(dev))
 388                         vc1 |= VC1_RX_MCST_TAG_EN;
 389
 390         } else {
 391                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 392                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 393                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 394                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 395
 396                 if (is5325(dev) || is5365(dev))
 397                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 398                 else
 399                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 400
 401                 if (is5325(dev) || is5365(dev))
 402                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 403         }
 404
 405         if (!is5325(dev) && !is5365(dev))
 406                 vc5 &= ~VC5_VID_FFF_EN;
 407
 408         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 409         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 410
 411         if (is5325(dev) || is5365(dev)) {
 412                 /* enable the high 8 bit vid check on 5325 */
 413                 if (is5325(dev) && enable)
 414                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 415                                    VC3_HIGH_8BIT_EN);
 416                 else
 417                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 418
 419                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 420                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 421         } else if (is63xx(dev)) {
 422                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 425         } else {
 426                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 427                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 428                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 429         }
 430
 431         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 432
 433         dev->vlan_enabled = enable;
 434 }
 435
 436 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 437 {
 438         u32 port_mask = 0;
 439         u16 max_size = JMS_MIN_SIZE;
 440
 441         if (is5325(dev) || is5365(dev))
 442                 return -EINVAL;
 443
 444         if (enable) {
 445                 port_mask = dev->enabled_ports;
 446                 max_size = JMS_MAX_SIZE;
 447                 if (allow_10_100)
 448                         port_mask |= JPM_10_100_JUMBO_EN;
 449         }
 450
 451         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 452         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 453 }
 454
 455 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 456 {
 457         unsigned int i;
 458
 459         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 460                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 461
 462         for (i = 0; i < 10; i++) {
 463                 u8 fast_age_ctrl;
 464
 465                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 466                           &fast_age_ctrl);
 467
 468                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 469                         goto out;
 470
 471                 msleep(1);
 472         }
 473
 474         return -ETIMEDOUT;
 475 out:
 476         /* Only age dynamic entries (default behavior) */
 477         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 478         return 0;
 479 }
 480
 481 static int b53_fast_age_port(struct b53_device *dev, int port)
 482 {
 483         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 484
 485         return b53_flush_arl(dev, FAST_AGE_PORT);
 486 }
 487
 488 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 489 {
 490         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 491
 492         return b53_flush_arl(dev, FAST_AGE_VLAN);
 493 }
 494
 495 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 496 {
 497         struct b53_device *dev = ds->priv;
 498         unsigned int i;
 499         u16 pvlan;
 500
 501         /* Enable the IMP port to be in the same VLAN as the other ports
 502          * on a per-port basis such that we only have Port i and IMP in
 503          * the same VLAN.
 504          */
 505         b53_for_each_port(dev, i) {
 506                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 507                 pvlan |= BIT(cpu_port);
 508                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 509         }
 510 }
 511 EXPORT_SYMBOL(b53_imp_vlan_setup);
 512
 513 static void b53_port_set_learning(struct b53_device *dev, int port,
 514                                   bool learning)
 515 {
 516         u16 reg;
 517
 518         b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
 519         if (learning)
 520                 reg &= ~BIT(port);
 521         else
 522                 reg |= BIT(port);
 523         b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
 524 }
 525
 526 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 527 {
 528         struct b53_device *dev = ds->priv;
 529         unsigned int cpu_port;
 530         int ret = 0;
 531         u16 pvlan;
 532
 533         if (!dsa_is_user_port(ds, port))
 534                 return 0;
 535
 536         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
 537
 538         b53_br_egress_floods(ds, port, true, true);
 539         b53_port_set_learning(dev, port, false);
 540
 541         if (dev->ops->irq_enable)
 542                 ret = dev->ops->irq_enable(dev, port);
 543         if (ret)
 544                 return ret;
 545
 546         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 547         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 548
 549         /* Set this port, and only this one to be in the default VLAN,
 550          * if member of a bridge, restore its membership prior to
 551          * bringing down this port.
 552          */
 553         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 554         pvlan &= ~0x1ff;
 555         pvlan |= BIT(port);
 556         pvlan |= dev->ports[port].vlan_ctl_mask;
 557         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 558
 559         b53_imp_vlan_setup(ds, cpu_port);
 560
 561         /* If EEE was enabled, restore it */
 562         if (dev->ports[port].eee.eee_enabled)
 563                 b53_eee_enable_set(ds, port, true);
 564
 565         return 0;
 566 }
 567 EXPORT_SYMBOL(b53_enable_port);
 568
 569 void b53_disable_port(struct dsa_switch *ds, int port)
 570 {
 571         struct b53_device *dev = ds->priv;
 572         u8 reg;
 573
 574         /* Disable Tx/Rx for the port */
 575         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 576         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 577         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 578
 579         if (dev->ops->irq_disable)
 580                 dev->ops->irq_disable(dev, port);
 581 }
 582 EXPORT_SYMBOL(b53_disable_port);
 583
 584 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 585 {
 586         struct b53_device *dev = ds->priv;
 587         bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
 588         u8 hdr_ctl, val;
 589         u16 reg;
 590
 591         /* Resolve which bit controls the Broadcom tag */
 592         switch (port) {
 593         case 8:
 594                 val = BRCM_HDR_P8_EN;
 595                 break;
 596         case 7:
 597                 val = BRCM_HDR_P7_EN;
 598                 break;
 599         case 5:
 600                 val = BRCM_HDR_P5_EN;
 601                 break;
 602         default:
 603                 val = 0;
 604                 break;
 605         }
 606
 607         /* Enable management mode if tagging is requested */
 608         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
 609         if (tag_en)
 610                 hdr_ctl |= SM_SW_FWD_MODE;
 611         else
 612                 hdr_ctl &= ~SM_SW_FWD_MODE;
 613         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
 614
 615         /* Configure the appropriate IMP port */
 616         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
 617         if (port == 8)
 618                 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
 619         else if (port == 5)
 620                 hdr_ctl |= GC_FRM_MGMT_PORT_M;
 621         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
 622
 623         /* Enable Broadcom tags for IMP port */
 624         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 625         if (tag_en)
 626                 hdr_ctl |= val;
 627         else
 628                 hdr_ctl &= ~val;
 629         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 630
 631         /* Registers below are only accessible on newer devices */
 632         if (!is58xx(dev))
 633                 return;
 634
 635         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 636          * allow us to tag outgoing frames
 637          */
 638         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 639         if (tag_en)
 640                 reg &= ~BIT(port);
 641         else
 642                 reg |= BIT(port);
 643         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 644
 645         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 646          * allow delivering frames to the per-port net_devices
 647          */
 648         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 649         if (tag_en)
 650                 reg &= ~BIT(port);
 651         else
 652                 reg |= BIT(port);
 653         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 654 }
 655 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 656
 657 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 658 {
 659         u8 port_ctrl;
 660
 661         /* BCM5325 CPU port is at 8 */
 662         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 663                 port = B53_CPU_PORT;
 664
 665         port_ctrl = PORT_CTRL_RX_BCST_EN |
 666                     PORT_CTRL_RX_MCST_EN |
 667                     PORT_CTRL_RX_UCST_EN;
 668         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 669
 670         b53_brcm_hdr_setup(dev->ds, port);
 671
 672         b53_br_egress_floods(dev->ds, port, true, true);
 673         b53_port_set_learning(dev, port, false);
 674 }
 675
 676 static void b53_enable_mib(struct b53_device *dev)
 677 {
 678         u8 gc;
 679
 680         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 681         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 682         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 683 }
 684
 685 static u16 b53_default_pvid(struct b53_device *dev)
 686 {
 687         if (is5325(dev) || is5365(dev))
 688                 return 1;
 689         else
 690                 return 0;
 691 }
 692
 693 int b53_configure_vlan(struct dsa_switch *ds)
 694 {
 695         struct b53_device *dev = ds->priv;
 696         struct b53_vlan vl = { 0 };
 697         struct b53_vlan *v;
 698         int i, def_vid;
 699         u16 vid;
 700
 701         def_vid = b53_default_pvid(dev);
 702
 703         /* clear all vlan entries */
 704         if (is5325(dev) || is5365(dev)) {
 705                 for (i = def_vid; i < dev->num_vlans; i++)
 706                         b53_set_vlan_entry(dev, i, &vl);
 707         } else {
 708                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 709         }
 710
 711         b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);
 712
 713         b53_for_each_port(dev, i)
 714                 b53_write16(dev, B53_VLAN_PAGE,
 715                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 716
 717         /* Upon initial call we have not set-up any VLANs, but upon
 718          * system resume, we need to restore all VLAN entries.
 719          */
 720         for (vid = def_vid; vid < dev->num_vlans; vid++) {
 721                 v = &dev->vlans[vid];
 722
 723                 if (!v->members)
 724                         continue;
 725
 726                 b53_set_vlan_entry(dev, vid, v);
 727                 b53_fast_age_vlan(dev, vid);
 728         }
 729
 730         return 0;
 731 }
 732 EXPORT_SYMBOL(b53_configure_vlan);
 733
 734 static void b53_switch_reset_gpio(struct b53_device *dev)
 735 {
 736         int gpio = dev->reset_gpio;
 737
 738         if (gpio < 0)
 739                 return;
 740
 741         /* Reset sequence: RESET low(50ms)->high(20ms)
 742          */
 743         gpio_set_value(gpio, 0);
 744         mdelay(50);
 745
 746         gpio_set_value(gpio, 1);
 747         mdelay(20);
 748
 749         dev->current_page = 0xff;
 750 }
 751
 752 static int b53_switch_reset(struct b53_device *dev)
 753 {
 754         unsigned int timeout = 1000;
 755         u8 mgmt, reg;
 756
 757         b53_switch_reset_gpio(dev);
 758
 759         if (is539x(dev)) {
 760                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 761                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 762         }
 763
 764         /* This is specific to 58xx devices here, do not use is58xx() which
 765          * covers the larger Starfigther 2 family, including 7445/7278 which
 766          * still use this driver as a library and need to perform the reset
 767          * earlier.
 768          */
 769         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 770             dev->chip_id == BCM583XX_DEVICE_ID) {
 771                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 772                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 773                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 774
 775                 do {
 776                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 777                         if (!(reg & SW_RST))
 778                                 break;
 779
 780                         usleep_range(1000, 2000);
 781                 } while (timeout-- > 0);
 782
 783                 if (timeout == 0) {
 784                         dev_err(dev->dev,
 785                                 "Timeout waiting for SW_RST to clear!\n");
 786                         return -ETIMEDOUT;
 787                 }
 788         }
 789
 790         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 791
 792         if (!(mgmt & SM_SW_FWD_EN)) {
 793                 mgmt &= ~SM_SW_FWD_MODE;
 794                 mgmt |= SM_SW_FWD_EN;
 795
 796                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 797                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 798
 799                 if (!(mgmt & SM_SW_FWD_EN)) {
 800                         dev_err(dev->dev, "Failed to enable switch!\n");
 801                         return -EINVAL;
 802                 }
 803         }
 804
 805         b53_enable_mib(dev);
 806
 807         return b53_flush_arl(dev, FAST_AGE_STATIC);
 808 }
 809
 810 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 811 {
 812         struct b53_device *priv = ds->priv;
 813         u16 value = 0;
 814         int ret;
 815
 816         if (priv->ops->phy_read16)
 817                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 818         else
 819                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 820                                  reg * 2, &value);
 821
 822         return ret ? ret : value;
 823 }
 824
 825 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 826 {
 827         struct b53_device *priv = ds->priv;
 828
 829         if (priv->ops->phy_write16)
 830                 return priv->ops->phy_write16(priv, addr, reg, val);
 831
 832         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 833 }
 834
 835 static int b53_reset_switch(struct b53_device *priv)
 836 {
 837         /* reset vlans */
 838         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 839         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 840
 841         priv->serdes_lane = B53_INVALID_LANE;
 842
 843         return b53_switch_reset(priv);
 844 }
 845
 846 static int b53_apply_config(struct b53_device *priv)
 847 {
 848         /* disable switching */
 849         b53_set_forwarding(priv, 0);
 850
 851         b53_configure_vlan(priv->ds);
 852
 853         /* enable switching */
 854         b53_set_forwarding(priv, 1);
 855
 856         return 0;
 857 }
 858
 859 static void b53_reset_mib(struct b53_device *priv)
 860 {
 861         u8 gc;
 862
 863         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 864
 865         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 866         msleep(1);
 867         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 868         msleep(1);
 869 }
 870
 871 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 872 {
 873         if (is5365(dev))
 874                 return b53_mibs_65;
 875         else if (is63xx(dev))
 876                 return b53_mibs_63xx;
 877         else if (is58xx(dev))
 878                 return b53_mibs_58xx;
 879         else
 880                 return b53_mibs;
 881 }
 882
 883 static unsigned int b53_get_mib_size(struct b53_device *dev)
 884 {
 885         if (is5365(dev))
 886                 return B53_MIBS_65_SIZE;
 887         else if (is63xx(dev))
 888                 return B53_MIBS_63XX_SIZE;
 889         else if (is58xx(dev))
 890                 return B53_MIBS_58XX_SIZE;
 891         else
 892                 return B53_MIBS_SIZE;
 893 }
 894
 895 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 896 {
 897         /* These ports typically do not have built-in PHYs */
 898         switch (port) {
 899         case B53_CPU_PORT_25:
 900         case 7:
 901         case B53_CPU_PORT:
 902                 return NULL;
 903         }
 904
 905         return mdiobus_get_phy(ds->slave_mii_bus, port);
 906 }
 907
 908 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 909                      uint8_t *data)
 910 {
 911         struct b53_device *dev = ds->priv;
 912         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 913         unsigned int mib_size = b53_get_mib_size(dev);
 914         struct phy_device *phydev;
 915         unsigned int i;
 916
 917         if (stringset == ETH_SS_STATS) {
 918                 for (i = 0; i < mib_size; i++)
 919                         strlcpy(data + i * ETH_GSTRING_LEN,
 920                                 mibs[i].name, ETH_GSTRING_LEN);
 921         } else if (stringset == ETH_SS_PHY_STATS) {
 922                 phydev = b53_get_phy_device(ds, port);
 923                 if (!phydev)
 924                         return;
 925
 926                 phy_ethtool_get_strings(phydev, data);
 927         }
 928 }
 929 EXPORT_SYMBOL(b53_get_strings);
 930
 931 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 932 {
 933         struct b53_device *dev = ds->priv;
 934         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 935         unsigned int mib_size = b53_get_mib_size(dev);
 936         const struct b53_mib_desc *s;
 937         unsigned int i;
 938         u64 val = 0;
 939
 940         if (is5365(dev) && port == 5)
 941                 port = 8;
 942
 943         mutex_lock(&dev->stats_mutex);
 944
 945         for (i = 0; i < mib_size; i++) {
 946                 s = &mibs[i];
 947
 948                 if (s->size == 8) {
 949                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 950                 } else {
 951                         u32 val32;
 952
 953                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 954                                    &val32);
 955                         val = val32;
 956                 }
 957                 data[i] = (u64)val;
 958         }
 959
 960         mutex_unlock(&dev->stats_mutex);
 961 }
 962 EXPORT_SYMBOL(b53_get_ethtool_stats);
 963
 964 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 965 {
 966         struct phy_device *phydev;
 967
 968         phydev = b53_get_phy_device(ds, port);
 969         if (!phydev)
 970                 return;
 971
 972         phy_ethtool_get_stats(phydev, NULL, data);
 973 }
 974 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 975
 976 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 977 {
 978         struct b53_device *dev = ds->priv;
 979         struct phy_device *phydev;
 980
 981         if (sset == ETH_SS_STATS) {
 982                 return b53_get_mib_size(dev);
 983         } else if (sset == ETH_SS_PHY_STATS) {
 984                 phydev = b53_get_phy_device(ds, port);
 985                 if (!phydev)
 986                         return 0;
 987
 988                 return phy_ethtool_get_sset_count(phydev);
 989         }
 990
 991         return 0;
 992 }
 993 EXPORT_SYMBOL(b53_get_sset_count);
 994
 995 enum b53_devlink_resource_id {
 996         B53_DEVLINK_PARAM_ID_VLAN_TABLE,
 997 };
 998
 999 static u64 b53_devlink_vlan_table_get(void *priv)
1000 {
1001         struct b53_device *dev = priv;
1002         struct b53_vlan *vl;
1003         unsigned int i;
1004         u64 count = 0;
1005
1006         for (i = 0; i < dev->num_vlans; i++) {
1007                 vl = &dev->vlans[i];
1008                 if (vl->members)
1009                         count++;
1010         }
1011
1012         return count;
1013 }
1014
1015 int b53_setup_devlink_resources(struct dsa_switch *ds)
1016 {
1017         struct devlink_resource_size_params size_params;
1018         struct b53_device *dev = ds->priv;
1019         int err;
1020
1021         devlink_resource_size_params_init(&size_params, dev->num_vlans,
1022                                           dev->num_vlans,
1023                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
1024
1025         err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1026                                             B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1027                                             DEVLINK_RESOURCE_ID_PARENT_TOP,
1028                                             &size_params);
1029         if (err)
1030                 goto out;
1031
1032         dsa_devlink_resource_occ_get_register(ds,
1033                                               B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1034                                               b53_devlink_vlan_table_get, dev);
1035
1036         return 0;
1037 out:
1038         dsa_devlink_resources_unregister(ds);
1039         return err;
1040 }
1041 EXPORT_SYMBOL(b53_setup_devlink_resources);
1042
1043 static int b53_setup(struct dsa_switch *ds)
1044 {
1045         struct b53_device *dev = ds->priv;
1046         unsigned int port;
1047         int ret;
1048
1049         ret = b53_reset_switch(dev);
1050         if (ret) {
1051                 dev_err(ds->dev, "failed to reset switch\n");
1052                 return ret;
1053         }
1054
1055         b53_reset_mib(dev);
1056
1057         ret = b53_apply_config(dev);
1058         if (ret) {
1059                 dev_err(ds->dev, "failed to apply configuration\n");
1060                 return ret;
1061         }
1062
1063         /* Configure IMP/CPU port, disable all other ports. Enabled
1064          * ports will be configured with .port_enable
1065          */
1066         for (port = 0; port < dev->num_ports; port++) {
1067                 if (dsa_is_cpu_port(ds, port))
1068                         b53_enable_cpu_port(dev, port);
1069                 else
1070                         b53_disable_port(ds, port);
1071         }
1072
1073         return b53_setup_devlink_resources(ds);
1074 }
1075
1076 static void b53_teardown(struct dsa_switch *ds)
1077 {
1078         dsa_devlink_resources_unregister(ds);
1079 }
1080
1081 static void b53_force_link(struct b53_device *dev, int port, int link)
1082 {
1083         u8 reg, val, off;
1084
1085         /* Override the port settings */
1086         if (port == dev->imp_port) {
1087                 off = B53_PORT_OVERRIDE_CTRL;
1088                 val = PORT_OVERRIDE_EN;
1089         } else {
1090                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1091                 val = GMII_PO_EN;
1092         }
1093
1094         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1095         reg |= val;
1096         if (link)
1097                 reg |= PORT_OVERRIDE_LINK;
1098         else
1099                 reg &= ~PORT_OVERRIDE_LINK;
1100         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1101 }
1102
1103 static void b53_force_port_config(struct b53_device *dev, int port,
1104                                   int speed, int duplex,
1105                                   bool tx_pause, bool rx_pause)
1106 {
1107         u8 reg, val, off;
1108
1109         /* Override the port settings */
1110         if (port == dev->imp_port) {
1111                 off = B53_PORT_OVERRIDE_CTRL;
1112                 val = PORT_OVERRIDE_EN;
1113         } else {
1114                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1115                 val = GMII_PO_EN;
1116         }
1117
1118         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1119         reg |= val;
1120         if (duplex == DUPLEX_FULL)
1121                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1122         else
1123                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1124
1125         switch (speed) {
1126         case 2000:
1127                 reg |= PORT_OVERRIDE_SPEED_2000M;
1128                 fallthrough;
1129         case SPEED_1000:
1130                 reg |= PORT_OVERRIDE_SPEED_1000M;
1131                 break;
1132         case SPEED_100:
1133                 reg |= PORT_OVERRIDE_SPEED_100M;
1134                 break;
1135         case SPEED_10:
1136                 reg |= PORT_OVERRIDE_SPEED_10M;
1137                 break;
1138         default:
1139                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1140                 return;
1141         }
1142
1143         if (rx_pause)
1144                 reg |= PORT_OVERRIDE_RX_FLOW;
1145         if (tx_pause)
1146                 reg |= PORT_OVERRIDE_TX_FLOW;
1147
1148         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1149 }
1150
1151 static void b53_adjust_link(struct dsa_switch *ds, int port,
1152                             struct phy_device *phydev)
1153 {
1154         struct b53_device *dev = ds->priv;
1155         struct ethtool_eee *p = &dev->ports[port].eee;
1156         u8 rgmii_ctrl = 0, reg = 0, off;
1157         bool tx_pause = false;
1158         bool rx_pause = false;
1159
1160         if (!phy_is_pseudo_fixed_link(phydev))
1161                 return;
1162
1163         /* Enable flow control on BCM5301x's CPU port */
1164         if (is5301x(dev) && port == dev->cpu_port)
1165                 tx_pause = rx_pause = true;
1166
1167         if (phydev->pause) {
1168                 if (phydev->asym_pause)
1169                         tx_pause = true;
1170                 rx_pause = true;
1171         }
1172
1173         b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1174                               tx_pause, rx_pause);
1175         b53_force_link(dev, port, phydev->link);
1176
1177         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1178                 if (port == dev->imp_port)
1179                         off = B53_RGMII_CTRL_IMP;
1180                 else
1181                         off = B53_RGMII_CTRL_P(port);
1182
1183                 /* Configure the port RGMII clock delay by DLL disabled and
1184                  * tx_clk aligned timing (restoring to reset defaults)
1185                  */
1186                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1187                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1188                                 RGMII_CTRL_TIMING_SEL);
1189
1190                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1191                  * sure that we enable the port TX clock internal delay to
1192                  * account for this internal delay that is inserted, otherwise
1193                  * the switch won't be able to receive correctly.
1194                  *
1195                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1196                  * any delay neither on transmission nor reception, so the
1197                  * BCM53125 must also be configured accordingly to account for
1198                  * the lack of delay and introduce
1199                  *
1200                  * The BCM53125 switch has its RX clock and TX clock control
1201                  * swapped, hence the reason why we modify the TX clock path in
1202                  * the "RGMII" case
1203                  */
1204                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1205                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1206                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1207                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1208                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1209                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1210
1211                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1212                          phy_modes(phydev->interface));
1213         }
1214
1215         /* configure MII port if necessary */
1216         if (is5325(dev)) {
1217                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1218                           &reg);
1219
1220                 /* reverse mii needs to be enabled */
1221                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1222                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1223                                    reg | PORT_OVERRIDE_RV_MII_25);
1224                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1225                                   &reg);
1226
1227                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1228                                 dev_err(ds->dev,
1229                                         "Failed to enable reverse MII mode\n");
1230                                 return;
1231                         }
1232                 }
1233         } else if (is5301x(dev)) {
1234                 if (port != dev->cpu_port) {
1235                         b53_force_port_config(dev, dev->cpu_port, 2000,
1236                                               DUPLEX_FULL, true, true);
1237                         b53_force_link(dev, dev->cpu_port, 1);
1238                 }
1239         }
1240
1241         /* Re-negotiate EEE if it was enabled already */
1242         p->eee_enabled = b53_eee_init(ds, port, phydev);
1243 }
1244
1245 void b53_port_event(struct dsa_switch *ds, int port)
1246 {
1247         struct b53_device *dev = ds->priv;
1248         bool link;
1249         u16 sts;
1250
1251         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1252         link = !!(sts & BIT(port));
1253         dsa_port_phylink_mac_change(ds, port, link);
1254 }
1255 EXPORT_SYMBOL(b53_port_event);
1256
1257 void b53_phylink_validate(struct dsa_switch *ds, int port,
1258                           unsigned long *supported,
1259                           struct phylink_link_state *state)
1260 {
1261         struct b53_device *dev = ds->priv;
1262         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1263
1264         if (dev->ops->serdes_phylink_validate)
1265                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1266
1267         /* Allow all the expected bits */
1268         phylink_set(mask, Autoneg);
1269         phylink_set_port_modes(mask);
1270         phylink_set(mask, Pause);
1271         phylink_set(mask, Asym_Pause);
1272
1273         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1274          * support Gigabit, including Half duplex.
1275          */
1276         if (state->interface != PHY_INTERFACE_MODE_MII &&
1277             state->interface != PHY_INTERFACE_MODE_REVMII &&
1278             !phy_interface_mode_is_8023z(state->interface) &&
1279             !(is5325(dev) || is5365(dev))) {
1280                 phylink_set(mask, 1000baseT_Full);
1281                 phylink_set(mask, 1000baseT_Half);
1282         }
1283
1284         if (!phy_interface_mode_is_8023z(state->interface)) {
1285                 phylink_set(mask, 10baseT_Half);
1286                 phylink_set(mask, 10baseT_Full);
1287                 phylink_set(mask, 100baseT_Half);
1288                 phylink_set(mask, 100baseT_Full);
1289         }
1290
1291         bitmap_and(supported, supported, mask,
1292                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1293         bitmap_and(state->advertising, state->advertising, mask,
1294                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1295
1296         phylink_helper_basex_speed(state);
1297 }
1298 EXPORT_SYMBOL(b53_phylink_validate);
1299
1300 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1301                                struct phylink_link_state *state)
1302 {
1303         struct b53_device *dev = ds->priv;
1304         int ret = -EOPNOTSUPP;
1305
1306         if ((phy_interface_mode_is_8023z(state->interface) ||
1307              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1308              dev->ops->serdes_link_state)
1309                 ret = dev->ops->serdes_link_state(dev, port, state);
1310
1311         return ret;
1312 }
1313 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1314
1315 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1316                             unsigned int mode,
1317                             const struct phylink_link_state *state)
1318 {
1319         struct b53_device *dev = ds->priv;
1320
1321         if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
1322                 return;
1323
1324         if ((phy_interface_mode_is_8023z(state->interface) ||
1325              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1326              dev->ops->serdes_config)
1327                 dev->ops->serdes_config(dev, port, mode, state);
1328 }
1329 EXPORT_SYMBOL(b53_phylink_mac_config);
1330
1331 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1332 {
1333         struct b53_device *dev = ds->priv;
1334
1335         if (dev->ops->serdes_an_restart)
1336                 dev->ops->serdes_an_restart(dev, port);
1337 }
1338 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1339
1340 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1341                                unsigned int mode,
1342                                phy_interface_t interface)
1343 {
1344         struct b53_device *dev = ds->priv;
1345
1346         if (mode == MLO_AN_PHY)
1347                 return;
1348
1349         if (mode == MLO_AN_FIXED) {
1350                 b53_force_link(dev, port, false);
1351                 return;
1352         }
1353
1354         if (phy_interface_mode_is_8023z(interface) &&
1355             dev->ops->serdes_link_set)
1356                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1357 }
1358 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1359
1360 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1361                              unsigned int mode,
1362                              phy_interface_t interface,
1363                              struct phy_device *phydev,
1364                              int speed, int duplex,
1365                              bool tx_pause, bool rx_pause)
1366 {
1367         struct b53_device *dev = ds->priv;
1368
1369         if (mode == MLO_AN_PHY)
1370                 return;
1371
1372         if (mode == MLO_AN_FIXED) {
1373                 b53_force_port_config(dev, port, speed, duplex,
1374                                       tx_pause, rx_pause);
1375                 b53_force_link(dev, port, true);
1376                 return;
1377         }
1378
1379         if (phy_interface_mode_is_8023z(interface) &&
1380             dev->ops->serdes_link_set)
1381                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1382 }
1383 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1384
1385 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1386                        struct switchdev_trans *trans)
1387 {
1388         struct b53_device *dev = ds->priv;
1389
1390         if (switchdev_trans_ph_prepare(trans))
1391                 return 0;
1392
1393         b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1394
1395         return 0;
1396 }
1397 EXPORT_SYMBOL(b53_vlan_filtering);
1398
1399 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1400                      const struct switchdev_obj_port_vlan *vlan)
1401 {
1402         struct b53_device *dev = ds->priv;
1403
1404         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1405                 return -EOPNOTSUPP;
1406
1407         /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1408          * receiving VLAN tagged frames at all, we can still allow the port to
1409          * be configured for egress untagged.
1410          */
1411         if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1412             !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1413                 return -EINVAL;
1414
1415         if (vlan->vid_end >= dev->num_vlans)
1416                 return -ERANGE;
1417
1418         b53_enable_vlan(dev, true, ds->vlan_filtering);
1419
1420         return 0;
1421 }
1422 EXPORT_SYMBOL(b53_vlan_prepare);
1423
1424 void b53_vlan_add(struct dsa_switch *ds, int port,
1425                   const struct switchdev_obj_port_vlan *vlan)
1426 {
1427         struct b53_device *dev = ds->priv;
1428         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1429         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1430         struct b53_vlan *vl;
1431         u16 vid;
1432
1433         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1434                 vl = &dev->vlans[vid];
1435
1436                 b53_get_vlan_entry(dev, vid, vl);
1437
1438                 if (vid == 0 && vid == b53_default_pvid(dev))
1439                         untagged = true;
1440
1441                 vl->members |= BIT(port);
1442                 if (untagged && !dsa_is_cpu_port(ds, port))
1443                         vl->untag |= BIT(port);
1444                 else
1445                         vl->untag &= ~BIT(port);
1446
1447                 b53_set_vlan_entry(dev, vid, vl);
1448                 b53_fast_age_vlan(dev, vid);
1449         }
1450
1451         if (pvid && !dsa_is_cpu_port(ds, port)) {
1452                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1453                             vlan->vid_end);
1454                 b53_fast_age_vlan(dev, vid);
1455         }
1456 }
1457 EXPORT_SYMBOL(b53_vlan_add);
1458
1459 int b53_vlan_del(struct dsa_switch *ds, int port,
1460                  const struct switchdev_obj_port_vlan *vlan)
1461 {
1462         struct b53_device *dev = ds->priv;
1463         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1464         struct b53_vlan *vl;
1465         u16 vid;
1466         u16 pvid;
1467
1468         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1469
1470         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1471                 vl = &dev->vlans[vid];
1472
1473                 b53_get_vlan_entry(dev, vid, vl);
1474
1475                 vl->members &= ~BIT(port);
1476
1477                 if (pvid == vid)
1478                         pvid = b53_default_pvid(dev);
1479
1480                 if (untagged && !dsa_is_cpu_port(ds, port))
1481                         vl->untag &= ~(BIT(port));
1482
1483                 b53_set_vlan_entry(dev, vid, vl);
1484                 b53_fast_age_vlan(dev, vid);
1485         }
1486
1487         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1488         b53_fast_age_vlan(dev, pvid);
1489
1490         return 0;
1491 }
1492 EXPORT_SYMBOL(b53_vlan_del);
1493
1494 /* Address Resolution Logic routines */
1495 static int b53_arl_op_wait(struct b53_device *dev)
1496 {
1497         unsigned int timeout = 10;
1498         u8 reg;
1499
1500         do {
1501                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1502                 if (!(reg & ARLTBL_START_DONE))
1503                         return 0;
1504
1505                 usleep_range(1000, 2000);
1506         } while (timeout--);
1507
1508         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1509
1510         return -ETIMEDOUT;
1511 }
1512
1513 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1514 {
1515         u8 reg;
1516
1517         if (op > ARLTBL_RW)
1518                 return -EINVAL;
1519
1520         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1521         reg |= ARLTBL_START_DONE;
1522         if (op)
1523                 reg |= ARLTBL_RW;
1524         else
1525                 reg &= ~ARLTBL_RW;
1526         if (dev->vlan_enabled)
1527                 reg &= ~ARLTBL_IVL_SVL_SELECT;
1528         else
1529                 reg |= ARLTBL_IVL_SVL_SELECT;
1530         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1531
1532         return b53_arl_op_wait(dev);
1533 }
1534
1535 static int b53_arl_read(struct b53_device *dev, u64 mac,
1536                         u16 vid, struct b53_arl_entry *ent, u8 *idx)
1537 {
1538         DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1539         unsigned int i;
1540         int ret;
1541
1542         ret = b53_arl_op_wait(dev);
1543         if (ret)
1544                 return ret;
1545
1546         bitmap_zero(free_bins, dev->num_arl_bins);
1547
1548         /* Read the bins */
1549         for (i = 0; i < dev->num_arl_bins; i++) {
1550                 u64 mac_vid;
1551                 u32 fwd_entry;
1552
1553                 b53_read64(dev, B53_ARLIO_PAGE,
1554                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1555                 b53_read32(dev, B53_ARLIO_PAGE,
1556                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1557                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1558
1559                 if (!(fwd_entry & ARLTBL_VALID)) {
1560                         set_bit(i, free_bins);
1561                         continue;
1562                 }
1563                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1564                         continue;
1565                 if (dev->vlan_enabled &&
1566                     ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1567                         continue;
1568                 *idx = i;
1569                 return 0;
1570         }
1571
1572         if (bitmap_weight(free_bins, dev->num_arl_bins) == 0)
1573                 return -ENOSPC;
1574
1575         *idx = find_first_bit(free_bins, dev->num_arl_bins);
1576
1577         return -ENOENT;
1578 }
1579
1580 static int b53_arl_op(struct b53_device *dev, int op, int port,
1581                       const unsigned char *addr, u16 vid, bool is_valid)
1582 {
1583         struct b53_arl_entry ent;
1584         u32 fwd_entry;
1585         u64 mac, mac_vid = 0;
1586         u8 idx = 0;
1587         int ret;
1588
1589         /* Convert the array into a 64-bit MAC */
1590         mac = ether_addr_to_u64(addr);
1591
1592         /* Perform a read for the given MAC and VID */
1593         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1594         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1595
1596         /* Issue a read operation for this MAC */
1597         ret = b53_arl_rw_op(dev, 1);
1598         if (ret)
1599                 return ret;
1600
1601         ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1602
1603         /* If this is a read, just finish now */
1604         if (op)
1605                 return ret;
1606
1607         switch (ret) {
1608         case -ETIMEDOUT:
1609                 return ret;
1610         case -ENOSPC:
1611                 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1612                         addr, vid);
1613                 return is_valid ? ret : 0;
1614         case -ENOENT:
1615                 /* We could not find a matching MAC, so reset to a new entry */
1616                 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1617                         addr, vid, idx);
1618                 fwd_entry = 0;
1619                 break;
1620         default:
1621                 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1622                         addr, vid, idx);
1623                 break;
1624         }
1625
1626         /* For multicast address, the port is a bitmask and the validity
1627          * is determined by having at least one port being still active
1628          */
1629         if (!is_multicast_ether_addr(addr)) {
1630                 ent.port = port;
1631                 ent.is_valid = is_valid;
1632         } else {
1633                 if (is_valid)
1634                         ent.port |= BIT(port);
1635                 else
1636                         ent.port &= ~BIT(port);
1637
1638                 ent.is_valid = !!(ent.port);
1639         }
1640
1641         ent.vid = vid;
1642         ent.is_static = true;
1643         ent.is_age = false;
1644         memcpy(ent.mac, addr, ETH_ALEN);
1645         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1646
1647         b53_write64(dev, B53_ARLIO_PAGE,
1648                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1649         b53_write32(dev, B53_ARLIO_PAGE,
1650                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1651
1652         return b53_arl_rw_op(dev, 0);
1653 }
1654
1655 int b53_fdb_add(struct dsa_switch *ds, int port,
1656                 const unsigned char *addr, u16 vid)
1657 {
1658         struct b53_device *priv = ds->priv;
1659
1660         /* 5325 and 5365 require some more massaging, but could
1661          * be supported eventually
1662          */
1663         if (is5325(priv) || is5365(priv))
1664                 return -EOPNOTSUPP;
1665
1666         return b53_arl_op(priv, 0, port, addr, vid, true);
1667 }
1668 EXPORT_SYMBOL(b53_fdb_add);
1669
1670 int b53_fdb_del(struct dsa_switch *ds, int port,
1671                 const unsigned char *addr, u16 vid)
1672 {
1673         struct b53_device *priv = ds->priv;
1674
1675         return b53_arl_op(priv, 0, port, addr, vid, false);
1676 }
1677 EXPORT_SYMBOL(b53_fdb_del);
1678
1679 static int b53_arl_search_wait(struct b53_device *dev)
1680 {
1681         unsigned int timeout = 1000;
1682         u8 reg;
1683
1684         do {
1685                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1686                 if (!(reg & ARL_SRCH_STDN))
1687                         return 0;
1688
1689                 if (reg & ARL_SRCH_VLID)
1690                         return 0;
1691
1692                 usleep_range(1000, 2000);
1693         } while (timeout--);
1694
1695         return -ETIMEDOUT;
1696 }
1697
1698 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1699                               struct b53_arl_entry *ent)
1700 {
1701         u64 mac_vid;
1702         u32 fwd_entry;
1703
1704         b53_read64(dev, B53_ARLIO_PAGE,
1705                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1706         b53_read32(dev, B53_ARLIO_PAGE,
1707                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1708         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1709 }
1710
1711 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1712                         dsa_fdb_dump_cb_t *cb, void *data)
1713 {
1714         if (!ent->is_valid)
1715                 return 0;
1716
1717         if (port != ent->port)
1718                 return 0;
1719
1720         return cb(ent->mac, ent->vid, ent->is_static, data);
1721 }
1722
1723 int b53_fdb_dump(struct dsa_switch *ds, int port,
1724                  dsa_fdb_dump_cb_t *cb, void *data)
1725 {
1726         struct b53_device *priv = ds->priv;
1727         struct b53_arl_entry results[2];
1728         unsigned int count = 0;
1729         int ret;
1730         u8 reg;
1731
1732         /* Start search operation */
1733         reg = ARL_SRCH_STDN;
1734         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1735
1736         do {
1737                 ret = b53_arl_search_wait(priv);
1738                 if (ret)
1739                         return ret;
1740
1741                 b53_arl_search_rd(priv, 0, &results[0]);
1742                 ret = b53_fdb_copy(port, &results[0], cb, data);
1743                 if (ret)
1744                         return ret;
1745
1746                 if (priv->num_arl_bins > 2) {
1747                         b53_arl_search_rd(priv, 1, &results[1]);
1748                         ret = b53_fdb_copy(port, &results[1], cb, data);
1749                         if (ret)
1750                                 return ret;
1751
1752                         if (!results[0].is_valid && !results[1].is_valid)
1753                                 break;
1754                 }
1755
1756         } while (count++ < b53_max_arl_entries(priv) / 2);
1757
1758         return 0;
1759 }
1760 EXPORT_SYMBOL(b53_fdb_dump);
1761
1762 int b53_mdb_prepare(struct dsa_switch *ds, int port,
1763                     const struct switchdev_obj_port_mdb *mdb)
1764 {
1765         struct b53_device *priv = ds->priv;
1766
1767         /* 5325 and 5365 require some more massaging, but could
1768          * be supported eventually
1769          */
1770         if (is5325(priv) || is5365(priv))
1771                 return -EOPNOTSUPP;
1772
1773         return 0;
1774 }
1775 EXPORT_SYMBOL(b53_mdb_prepare);
1776
1777 void b53_mdb_add(struct dsa_switch *ds, int port,
1778                  const struct switchdev_obj_port_mdb *mdb)
1779 {
1780         struct b53_device *priv = ds->priv;
1781         int ret;
1782
1783         ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1784         if (ret)
1785                 dev_err(ds->dev, "failed to add MDB entry\n");
1786 }
1787 EXPORT_SYMBOL(b53_mdb_add);
1788
1789 int b53_mdb_del(struct dsa_switch *ds, int port,
1790                 const struct switchdev_obj_port_mdb *mdb)
1791 {
1792         struct b53_device *priv = ds->priv;
1793         int ret;
1794
1795         ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1796         if (ret)
1797                 dev_err(ds->dev, "failed to delete MDB entry\n");
1798
1799         return ret;
1800 }
1801 EXPORT_SYMBOL(b53_mdb_del);
1802
1803 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1804 {
1805         struct b53_device *dev = ds->priv;
1806         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1807         u16 pvlan, reg;
1808         unsigned int i;
1809
1810         /* On 7278, port 7 which connects to the ASP should only receive
1811          * traffic from matching CFP rules.
1812          */
1813         if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1814                 return -EINVAL;
1815
1816         /* Make this port leave the all VLANs join since we will have proper
1817          * VLAN entries from now on
1818          */
1819         if (is58xx(dev)) {
1820                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1821                 reg &= ~BIT(port);
1822                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1823                         reg &= ~BIT(cpu_port);
1824                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1825         }
1826
1827         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1828
1829         b53_for_each_port(dev, i) {
1830                 if (dsa_to_port(ds, i)->bridge_dev != br)
1831                         continue;
1832
1833                 /* Add this local port to the remote port VLAN control
1834                  * membership and update the remote port bitmask
1835                  */
1836                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1837                 reg |= BIT(port);
1838                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1839                 dev->ports[i].vlan_ctl_mask = reg;
1840
1841                 pvlan |= BIT(i);
1842         }
1843
1844         /* Configure the local port VLAN control membership to include
1845          * remote ports and update the local port bitmask
1846          */
1847         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1848         dev->ports[port].vlan_ctl_mask = pvlan;
1849
1850         b53_port_set_learning(dev, port, true);
1851
1852         return 0;
1853 }
1854 EXPORT_SYMBOL(b53_br_join);
1855
1856 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1857 {
1858         struct b53_device *dev = ds->priv;
1859         struct b53_vlan *vl = &dev->vlans[0];
1860         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1861         unsigned int i;
1862         u16 pvlan, reg, pvid;
1863
1864         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1865
1866         b53_for_each_port(dev, i) {
1867                 /* Don't touch the remaining ports */
1868                 if (dsa_to_port(ds, i)->bridge_dev != br)
1869                         continue;
1870
1871                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1872                 reg &= ~BIT(port);
1873                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1874                 dev->ports[port].vlan_ctl_mask = reg;
1875
1876                 /* Prevent self removal to preserve isolation */
1877                 if (port != i)
1878                         pvlan &= ~BIT(i);
1879         }
1880
1881         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1882         dev->ports[port].vlan_ctl_mask = pvlan;
1883
1884         pvid = b53_default_pvid(dev);
1885
1886         /* Make this port join all VLANs without VLAN entries */
1887         if (is58xx(dev)) {
1888                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1889                 reg |= BIT(port);
1890                 if (!(reg & BIT(cpu_port)))
1891                         reg |= BIT(cpu_port);
1892                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1893         } else {
1894                 b53_get_vlan_entry(dev, pvid, vl);
1895                 vl->members |= BIT(port) | BIT(cpu_port);
1896                 vl->untag |= BIT(port) | BIT(cpu_port);
1897                 b53_set_vlan_entry(dev, pvid, vl);
1898         }
1899         b53_port_set_learning(dev, port, false);
1900 }
1901 EXPORT_SYMBOL(b53_br_leave);
1902
1903 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1904 {
1905         struct b53_device *dev = ds->priv;
1906         u8 hw_state;
1907         u8 reg;
1908
1909         switch (state) {
1910         case BR_STATE_DISABLED:
1911                 hw_state = PORT_CTRL_DIS_STATE;
1912                 break;
1913         case BR_STATE_LISTENING:
1914                 hw_state = PORT_CTRL_LISTEN_STATE;
1915                 break;
1916         case BR_STATE_LEARNING:
1917                 hw_state = PORT_CTRL_LEARN_STATE;
1918                 break;
1919         case BR_STATE_FORWARDING:
1920                 hw_state = PORT_CTRL_FWD_STATE;
1921                 break;
1922         case BR_STATE_BLOCKING:
1923                 hw_state = PORT_CTRL_BLOCK_STATE;
1924                 break;
1925         default:
1926                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1927                 return;
1928         }
1929
1930         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1931         reg &= ~PORT_CTRL_STP_STATE_MASK;
1932         reg |= hw_state;
1933         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1934 }
1935 EXPORT_SYMBOL(b53_br_set_stp_state);
1936
1937 void b53_br_fast_age(struct dsa_switch *ds, int port)
1938 {
1939         struct b53_device *dev = ds->priv;
1940
1941         if (b53_fast_age_port(dev, port))
1942                 dev_err(ds->dev, "fast ageing failed\n");
1943 }
1944 EXPORT_SYMBOL(b53_br_fast_age);
1945
1946 int b53_br_egress_floods(struct dsa_switch *ds, int port,
1947                          bool unicast, bool multicast)
1948 {
1949         struct b53_device *dev = ds->priv;
1950         u16 uc, mc;
1951
1952         b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
1953         if (unicast)
1954                 uc |= BIT(port);
1955         else
1956                 uc &= ~BIT(port);
1957         b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
1958
1959         b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
1960         if (multicast)
1961                 mc |= BIT(port);
1962         else
1963                 mc &= ~BIT(port);
1964         b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
1965
1966         b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
1967         if (multicast)
1968                 mc |= BIT(port);
1969         else
1970                 mc &= ~BIT(port);
1971         b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
1972
1973         return 0;
1974
1975 }
1976 EXPORT_SYMBOL(b53_br_egress_floods);
1977
1978 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1979 {
1980         /* Broadcom switches will accept enabling Broadcom tags on the
1981          * following ports: 5, 7 and 8, any other port is not supported
1982          */
1983         switch (port) {
1984         case B53_CPU_PORT_25:
1985         case 7:
1986         case B53_CPU_PORT:
1987                 return true;
1988         }
1989
1990         return false;
1991 }
1992
1993 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
1994                                      enum dsa_tag_protocol tag_protocol)
1995 {
1996         bool ret = b53_possible_cpu_port(ds, port);
1997
1998         if (!ret) {
1999                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2000                          port);
2001                 return ret;
2002         }
2003
2004         switch (tag_protocol) {
2005         case DSA_TAG_PROTO_BRCM:
2006         case DSA_TAG_PROTO_BRCM_PREPEND:
2007                 dev_warn(ds->dev,
2008                          "Port %d is stacked to Broadcom tag switch\n", port);
2009                 ret = false;
2010                 break;
2011         default:
2012                 ret = true;
2013                 break;
2014         }
2015
2016         return ret;
2017 }
2018
2019 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2020                                            enum dsa_tag_protocol mprot)
2021 {
2022         struct b53_device *dev = ds->priv;
2023
2024         /* Older models (5325, 5365) support a different tag format that we do
2025          * not support in net/dsa/tag_brcm.c yet.
2026          */
2027         if (is5325(dev) || is5365(dev) ||
2028             !b53_can_enable_brcm_tags(ds, port, mprot)) {
2029                 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2030                 goto out;
2031         }
2032
2033         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2034          * which requires us to use the prepended Broadcom tag type
2035          */
2036         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2037                 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2038                 goto out;
2039         }
2040
2041         dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2042 out:
2043         return dev->tag_protocol;
2044 }
2045 EXPORT_SYMBOL(b53_get_tag_protocol);
2046
2047 int b53_mirror_add(struct dsa_switch *ds, int port,
2048                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
2049 {
2050         struct b53_device *dev = ds->priv;
2051         u16 reg, loc;
2052
2053         if (ingress)
2054                 loc = B53_IG_MIR_CTL;
2055         else
2056                 loc = B53_EG_MIR_CTL;
2057
2058         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2059         reg |= BIT(port);
2060         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2061
2062         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2063         reg &= ~CAP_PORT_MASK;
2064         reg |= mirror->to_local_port;
2065         reg |= MIRROR_EN;
2066         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2067
2068         return 0;
2069 }
2070 EXPORT_SYMBOL(b53_mirror_add);
2071
2072 void b53_mirror_del(struct dsa_switch *ds, int port,
2073                     struct dsa_mall_mirror_tc_entry *mirror)
2074 {
2075         struct b53_device *dev = ds->priv;
2076         bool loc_disable = false, other_loc_disable = false;
2077         u16 reg, loc;
2078
2079         if (mirror->ingress)
2080                 loc = B53_IG_MIR_CTL;
2081         else
2082                 loc = B53_EG_MIR_CTL;
2083
2084         /* Update the desired ingress/egress register */
2085         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2086         reg &= ~BIT(port);
2087         if (!(reg & MIRROR_MASK))
2088                 loc_disable = true;
2089         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2090
2091         /* Now look at the other one to know if we can disable mirroring
2092          * entirely
2093          */
2094         if (mirror->ingress)
2095                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2096         else
2097                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2098         if (!(reg & MIRROR_MASK))
2099                 other_loc_disable = true;
2100
2101         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2102         /* Both no longer have ports, let's disable mirroring */
2103         if (loc_disable && other_loc_disable) {
2104                 reg &= ~MIRROR_EN;
2105                 reg &= ~mirror->to_local_port;
2106         }
2107         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2108 }
2109 EXPORT_SYMBOL(b53_mirror_del);
2110
2111 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2112 {
2113         struct b53_device *dev = ds->priv;
2114         u16 reg;
2115
2116         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
2117         if (enable)
2118                 reg |= BIT(port);
2119         else
2120                 reg &= ~BIT(port);
2121         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2122 }
2123 EXPORT_SYMBOL(b53_eee_enable_set);
2124
2125
2126 /* Returns 0 if EEE was not enabled, or 1 otherwise
2127  */
2128 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2129 {
2130         int ret;
2131
2132         ret = phy_init_eee(phy, 0);
2133         if (ret)
2134                 return 0;
2135
2136         b53_eee_enable_set(ds, port, true);
2137
2138         return 1;
2139 }
2140 EXPORT_SYMBOL(b53_eee_init);
2141
2142 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2143 {
2144         struct b53_device *dev = ds->priv;
2145         struct ethtool_eee *p = &dev->ports[port].eee;
2146         u16 reg;
2147
2148         if (is5325(dev) || is5365(dev))
2149                 return -EOPNOTSUPP;
2150
2151         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
2152         e->eee_enabled = p->eee_enabled;
2153         e->eee_active = !!(reg & BIT(port));
2154
2155         return 0;
2156 }
2157 EXPORT_SYMBOL(b53_get_mac_eee);
2158
2159 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2160 {
2161         struct b53_device *dev = ds->priv;
2162         struct ethtool_eee *p = &dev->ports[port].eee;
2163
2164         if (is5325(dev) || is5365(dev))
2165                 return -EOPNOTSUPP;
2166
2167         p->eee_enabled = e->eee_enabled;
2168         b53_eee_enable_set(ds, port, e->eee_enabled);
2169
2170         return 0;
2171 }
2172 EXPORT_SYMBOL(b53_set_mac_eee);
2173
2174 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2175 {
2176         struct b53_device *dev = ds->priv;
2177         bool enable_jumbo;
2178         bool allow_10_100;
2179
2180         if (is5325(dev) || is5365(dev))
2181                 return -EOPNOTSUPP;
2182
2183         enable_jumbo = (mtu >= JMS_MIN_SIZE);
2184         allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2185
2186         return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2187 }
2188
2189 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2190 {
2191         return JMS_MAX_SIZE;
2192 }
2193
2194 static const struct dsa_switch_ops b53_switch_ops = {
2195         .get_tag_protocol       = b53_get_tag_protocol,
2196         .setup                  = b53_setup,
2197         .teardown               = b53_teardown,
2198         .get_strings            = b53_get_strings,
2199         .get_ethtool_stats      = b53_get_ethtool_stats,
2200         .get_sset_count         = b53_get_sset_count,
2201         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
2202         .phy_read               = b53_phy_read16,
2203         .phy_write              = b53_phy_write16,
2204         .adjust_link            = b53_adjust_link,
2205         .phylink_validate       = b53_phylink_validate,
2206         .phylink_mac_link_state = b53_phylink_mac_link_state,
2207         .phylink_mac_config     = b53_phylink_mac_config,
2208         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2209         .phylink_mac_link_down  = b53_phylink_mac_link_down,
2210         .phylink_mac_link_up    = b53_phylink_mac_link_up,
2211         .port_enable            = b53_enable_port,
2212         .port_disable           = b53_disable_port,
2213         .get_mac_eee            = b53_get_mac_eee,
2214         .set_mac_eee            = b53_set_mac_eee,
2215         .port_bridge_join       = b53_br_join,
2216         .port_bridge_leave      = b53_br_leave,
2217         .port_stp_state_set     = b53_br_set_stp_state,
2218         .port_fast_age          = b53_br_fast_age,
2219         .port_egress_floods     = b53_br_egress_floods,
2220         .port_vlan_filtering    = b53_vlan_filtering,
2221         .port_vlan_prepare      = b53_vlan_prepare,
2222         .port_vlan_add          = b53_vlan_add,
2223         .port_vlan_del          = b53_vlan_del,
2224         .port_fdb_dump          = b53_fdb_dump,
2225         .port_fdb_add           = b53_fdb_add,
2226         .port_fdb_del           = b53_fdb_del,
2227         .port_mirror_add        = b53_mirror_add,
2228         .port_mirror_del        = b53_mirror_del,
2229         .port_mdb_prepare       = b53_mdb_prepare,
2230         .port_mdb_add           = b53_mdb_add,
2231         .port_mdb_del           = b53_mdb_del,
2232         .port_max_mtu           = b53_get_max_mtu,
2233         .port_change_mtu        = b53_change_mtu,
2234 };
2235
2236 struct b53_chip_data {
2237         u32 chip_id;
2238         const char *dev_name;
2239         u16 vlans;
2240         u16 enabled_ports;
2241         u8 imp_port;
2242         u8 cpu_port;
2243         u8 vta_regs[3];
2244         u8 arl_bins;
2245         u16 arl_buckets;
2246         u8 duplex_reg;
2247         u8 jumbo_pm_reg;
2248         u8 jumbo_size_reg;
2249 };
2250
2251 #define B53_VTA_REGS    \
2252         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2253 #define B53_VTA_REGS_9798 \
2254         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2255 #define B53_VTA_REGS_63XX \
2256         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2257
2258 static const struct b53_chip_data b53_switch_chips[] = {
2259         {
2260                 .chip_id = BCM5325_DEVICE_ID,
2261                 .dev_name = "BCM5325",
2262                 .vlans = 16,
2263                 .enabled_ports = 0x1f,
2264                 .arl_bins = 2,
2265                 .arl_buckets = 1024,
2266                 .imp_port = 5,
2267                 .cpu_port = B53_CPU_PORT_25,
2268                 .duplex_reg = B53_DUPLEX_STAT_FE,
2269         },
2270         {
2271                 .chip_id = BCM5365_DEVICE_ID,
2272                 .dev_name = "BCM5365",
2273                 .vlans = 256,
2274                 .enabled_ports = 0x1f,
2275                 .arl_bins = 2,
2276                 .arl_buckets = 1024,
2277                 .imp_port = 5,
2278                 .cpu_port = B53_CPU_PORT_25,
2279                 .duplex_reg = B53_DUPLEX_STAT_FE,
2280         },
2281         {
2282                 .chip_id = BCM5389_DEVICE_ID,
2283                 .dev_name = "BCM5389",
2284                 .vlans = 4096,
2285                 .enabled_ports = 0x1f,
2286                 .arl_bins = 4,
2287                 .arl_buckets = 1024,
2288                 .imp_port = 8,
2289                 .cpu_port = B53_CPU_PORT,
2290                 .vta_regs = B53_VTA_REGS,
2291                 .duplex_reg = B53_DUPLEX_STAT_GE,
2292                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2293                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2294         },
2295         {
2296                 .chip_id = BCM5395_DEVICE_ID,
2297                 .dev_name = "BCM5395",
2298                 .vlans = 4096,
2299                 .enabled_ports = 0x1f,
2300                 .arl_bins = 4,
2301                 .arl_buckets = 1024,
2302                 .imp_port = 8,
2303                 .cpu_port = B53_CPU_PORT,
2304                 .vta_regs = B53_VTA_REGS,
2305                 .duplex_reg = B53_DUPLEX_STAT_GE,
2306                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2307                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2308         },
2309         {
2310                 .chip_id = BCM5397_DEVICE_ID,
2311                 .dev_name = "BCM5397",
2312                 .vlans = 4096,
2313                 .enabled_ports = 0x1f,
2314                 .arl_bins = 4,
2315                 .arl_buckets = 1024,
2316                 .imp_port = 8,
2317                 .cpu_port = B53_CPU_PORT,
2318                 .vta_regs = B53_VTA_REGS_9798,
2319                 .duplex_reg = B53_DUPLEX_STAT_GE,
2320                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2321                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2322         },
2323         {
2324                 .chip_id = BCM5398_DEVICE_ID,
2325                 .dev_name = "BCM5398",
2326                 .vlans = 4096,
2327                 .enabled_ports = 0x7f,
2328                 .arl_bins = 4,
2329                 .arl_buckets = 1024,
2330                 .imp_port = 8,
2331                 .cpu_port = B53_CPU_PORT,
2332                 .vta_regs = B53_VTA_REGS_9798,
2333                 .duplex_reg = B53_DUPLEX_STAT_GE,
2334                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2335                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2336         },
2337         {
2338                 .chip_id = BCM53115_DEVICE_ID,
2339                 .dev_name = "BCM53115",
2340                 .vlans = 4096,
2341                 .enabled_ports = 0x1f,
2342                 .arl_bins = 4,
2343                 .arl_buckets = 1024,
2344                 .vta_regs = B53_VTA_REGS,
2345                 .imp_port = 8,
2346                 .cpu_port = B53_CPU_PORT,
2347                 .duplex_reg = B53_DUPLEX_STAT_GE,
2348                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2349                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2350         },
2351         {
2352                 .chip_id = BCM53125_DEVICE_ID,
2353                 .dev_name = "BCM53125",
2354                 .vlans = 4096,
2355                 .enabled_ports = 0xff,
2356                 .arl_bins = 4,
2357                 .arl_buckets = 1024,
2358                 .imp_port = 8,
2359                 .cpu_port = B53_CPU_PORT,
2360                 .vta_regs = B53_VTA_REGS,
2361                 .duplex_reg = B53_DUPLEX_STAT_GE,
2362                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2363                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2364         },
2365         {
2366                 .chip_id = BCM53128_DEVICE_ID,
2367                 .dev_name = "BCM53128",
2368                 .vlans = 4096,
2369                 .enabled_ports = 0x1ff,
2370                 .arl_bins = 4,
2371                 .arl_buckets = 1024,
2372                 .imp_port = 8,
2373                 .cpu_port = B53_CPU_PORT,
2374                 .vta_regs = B53_VTA_REGS,
2375                 .duplex_reg = B53_DUPLEX_STAT_GE,
2376                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2377                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2378         },
2379         {
2380                 .chip_id = BCM63XX_DEVICE_ID,
2381                 .dev_name = "BCM63xx",
2382                 .vlans = 4096,
2383                 .enabled_ports = 0, /* pdata must provide them */
2384                 .arl_bins = 4,
2385                 .arl_buckets = 1024,
2386                 .imp_port = 8,
2387                 .cpu_port = B53_CPU_PORT,
2388                 .vta_regs = B53_VTA_REGS_63XX,
2389                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2390                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2391                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2392         },
2393         {
2394                 .chip_id = BCM53010_DEVICE_ID,
2395                 .dev_name = "BCM53010",
2396                 .vlans = 4096,
2397                 .enabled_ports = 0x1f,
2398                 .arl_bins = 4,
2399                 .arl_buckets = 1024,
2400                 .imp_port = 8,
2401                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2402                 .vta_regs = B53_VTA_REGS,
2403                 .duplex_reg = B53_DUPLEX_STAT_GE,
2404                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2405                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2406         },
2407         {
2408                 .chip_id = BCM53011_DEVICE_ID,
2409                 .dev_name = "BCM53011",
2410                 .vlans = 4096,
2411                 .enabled_ports = 0x1bf,
2412                 .arl_bins = 4,
2413                 .arl_buckets = 1024,
2414                 .imp_port = 8,
2415                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2416                 .vta_regs = B53_VTA_REGS,
2417                 .duplex_reg = B53_DUPLEX_STAT_GE,
2418                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2419                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2420         },
2421         {
2422                 .chip_id = BCM53012_DEVICE_ID,
2423                 .dev_name = "BCM53012",
2424                 .vlans = 4096,
2425                 .enabled_ports = 0x1bf,
2426                 .arl_bins = 4,
2427                 .arl_buckets = 1024,
2428                 .imp_port = 8,
2429                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2430                 .vta_regs = B53_VTA_REGS,
2431                 .duplex_reg = B53_DUPLEX_STAT_GE,
2432                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2433                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2434         },
2435         {
2436                 .chip_id = BCM53018_DEVICE_ID,
2437                 .dev_name = "BCM53018",
2438                 .vlans = 4096,
2439                 .enabled_ports = 0x1f,
2440                 .arl_bins = 4,
2441                 .arl_buckets = 1024,
2442                 .imp_port = 8,
2443                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2444                 .vta_regs = B53_VTA_REGS,
2445                 .duplex_reg = B53_DUPLEX_STAT_GE,
2446                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2447                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2448         },
2449         {
2450                 .chip_id = BCM53019_DEVICE_ID,
2451                 .dev_name = "BCM53019",
2452                 .vlans = 4096,
2453                 .enabled_ports = 0x1f,
2454                 .arl_bins = 4,
2455                 .arl_buckets = 1024,
2456                 .imp_port = 8,
2457                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2458                 .vta_regs = B53_VTA_REGS,
2459                 .duplex_reg = B53_DUPLEX_STAT_GE,
2460                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2461                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2462         },
2463         {
2464                 .chip_id = BCM58XX_DEVICE_ID,
2465                 .dev_name = "BCM585xx/586xx/88312",
2466                 .vlans  = 4096,
2467                 .enabled_ports = 0x1ff,
2468                 .arl_bins = 4,
2469                 .arl_buckets = 1024,
2470                 .imp_port = 8,
2471                 .cpu_port = B53_CPU_PORT,
2472                 .vta_regs = B53_VTA_REGS,
2473                 .duplex_reg = B53_DUPLEX_STAT_GE,
2474                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2475                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2476         },
2477         {
2478                 .chip_id = BCM583XX_DEVICE_ID,
2479                 .dev_name = "BCM583xx/11360",
2480                 .vlans = 4096,
2481                 .enabled_ports = 0x103,
2482                 .arl_bins = 4,
2483                 .arl_buckets = 1024,
2484                 .imp_port = 8,
2485                 .cpu_port = B53_CPU_PORT,
2486                 .vta_regs = B53_VTA_REGS,
2487                 .duplex_reg = B53_DUPLEX_STAT_GE,
2488                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2489                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2490         },
2491         {
2492                 .chip_id = BCM7445_DEVICE_ID,
2493                 .dev_name = "BCM7445",
2494                 .vlans  = 4096,
2495                 .enabled_ports = 0x1ff,
2496                 .arl_bins = 4,
2497                 .arl_buckets = 1024,
2498                 .imp_port = 8,
2499                 .cpu_port = B53_CPU_PORT,
2500                 .vta_regs = B53_VTA_REGS,
2501                 .duplex_reg = B53_DUPLEX_STAT_GE,
2502                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2503                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2504         },
2505         {
2506                 .chip_id = BCM7278_DEVICE_ID,
2507                 .dev_name = "BCM7278",
2508                 .vlans = 4096,
2509                 .enabled_ports = 0x1ff,
2510                 .arl_bins = 4,
2511                 .arl_buckets = 256,
2512                 .imp_port = 8,
2513                 .cpu_port = B53_CPU_PORT,
2514                 .vta_regs = B53_VTA_REGS,
2515                 .duplex_reg = B53_DUPLEX_STAT_GE,
2516                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2517                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2518         },
2519 };
2520
2521 static int b53_switch_init(struct b53_device *dev)
2522 {
2523         unsigned int i;
2524         int ret;
2525
2526         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2527                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2528
2529                 if (chip->chip_id == dev->chip_id) {
2530                         if (!dev->enabled_ports)
2531                                 dev->enabled_ports = chip->enabled_ports;
2532                         dev->name = chip->dev_name;
2533                         dev->duplex_reg = chip->duplex_reg;
2534                         dev->vta_regs[0] = chip->vta_regs[0];
2535                         dev->vta_regs[1] = chip->vta_regs[1];
2536                         dev->vta_regs[2] = chip->vta_regs[2];
2537                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2538                         dev->imp_port = chip->imp_port;
2539                         dev->cpu_port = chip->cpu_port;
2540                         dev->num_vlans = chip->vlans;
2541                         dev->num_arl_bins = chip->arl_bins;
2542                         dev->num_arl_buckets = chip->arl_buckets;
2543                         break;
2544                 }
2545         }
2546
2547         /* check which BCM5325x version we have */
2548         if (is5325(dev)) {
2549                 u8 vc4;
2550
2551                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2552
2553                 /* check reserved bits */
2554                 switch (vc4 & 3) {
2555                 case 1:
2556                         /* BCM5325E */
2557                         break;
2558                 case 3:
2559                         /* BCM5325F - do not use port 4 */
2560                         dev->enabled_ports &= ~BIT(4);
2561                         break;
2562                 default:
2563 /* On the BCM47XX SoCs this is the supported internal switch.*/
2564 #ifndef CONFIG_BCM47XX
2565                         /* BCM5325M */
2566                         return -EINVAL;
2567 #else
2568                         break;
2569 #endif
2570                 }
2571         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2572                 u64 strap_value;
2573
2574                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2575                 /* use second IMP port if GMII is enabled */
2576                 if (strap_value & SV_GMII_CTRL_115)
2577                         dev->cpu_port = 5;
2578         }
2579
2580         dev->enabled_ports |= BIT(dev->cpu_port);
2581         dev->num_ports = fls(dev->enabled_ports);
2582
2583         dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2584
2585         /* Include non standard CPU port built-in PHYs to be probed */
2586         if (is539x(dev) || is531x5(dev)) {
2587                 for (i = 0; i < dev->num_ports; i++) {
2588                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2589                             !b53_possible_cpu_port(dev->ds, i))
2590                                 dev->ds->phys_mii_mask |= BIT(i);
2591                 }
2592         }
2593
2594         dev->ports = devm_kcalloc(dev->dev,
2595                                   dev->num_ports, sizeof(struct b53_port),
2596                                   GFP_KERNEL);
2597         if (!dev->ports)
2598                 return -ENOMEM;
2599
2600         dev->vlans = devm_kcalloc(dev->dev,
2601                                   dev->num_vlans, sizeof(struct b53_vlan),
2602                                   GFP_KERNEL);
2603         if (!dev->vlans)
2604                 return -ENOMEM;
2605
2606         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2607         if (dev->reset_gpio >= 0) {
2608                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2609                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2610                 if (ret)
2611                         return ret;
2612         }
2613
2614         return 0;
2615 }
2616
2617 struct b53_device *b53_switch_alloc(struct device *base,
2618                                     const struct b53_io_ops *ops,
2619                                     void *priv)
2620 {
2621         struct dsa_switch *ds;
2622         struct b53_device *dev;
2623
2624         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2625         if (!ds)
2626                 return NULL;
2627
2628         ds->dev = base;
2629
2630         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2631         if (!dev)
2632                 return NULL;
2633
2634         ds->priv = dev;
2635         dev->dev = base;
2636
2637         dev->ds = ds;
2638         dev->priv = priv;
2639         dev->ops = ops;
2640         ds->ops = &b53_switch_ops;
2641         ds->configure_vlan_while_not_filtering = true;
2642         ds->untag_bridge_pvid = true;
2643         dev->vlan_enabled = ds->configure_vlan_while_not_filtering;
2644         /* Let DSA handle the case were multiple bridges span the same switch
2645          * device and different VLAN awareness settings are requested, which
2646          * would be breaking filtering semantics for any of the other bridge
2647          * devices. (not hardware supported)
2648          */
2649         ds->vlan_filtering_is_global = true;
2650
2651         mutex_init(&dev->reg_mutex);
2652         mutex_init(&dev->stats_mutex);
2653
2654         return dev;
2655 }
2656 EXPORT_SYMBOL(b53_switch_alloc);
2657
2658 int b53_switch_detect(struct b53_device *dev)
2659 {
2660         u32 id32;
2661         u16 tmp;
2662         u8 id8;
2663         int ret;
2664
2665         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2666         if (ret)
2667                 return ret;
2668
2669         switch (id8) {
2670         case 0:
2671                 /* BCM5325 and BCM5365 do not have this register so reads
2672                  * return 0. But the read operation did succeed, so assume this
2673                  * is one of them.
2674                  *
2675                  * Next check if we can write to the 5325's VTA register; for
2676                  * 5365 it is read only.
2677                  */
2678                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2679                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2680
2681                 if (tmp == 0xf)
2682                         dev->chip_id = BCM5325_DEVICE_ID;
2683                 else
2684                         dev->chip_id = BCM5365_DEVICE_ID;
2685                 break;
2686         case BCM5389_DEVICE_ID:
2687         case BCM5395_DEVICE_ID:
2688         case BCM5397_DEVICE_ID:
2689         case BCM5398_DEVICE_ID:
2690                 dev->chip_id = id8;
2691                 break;
2692         default:
2693                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2694                 if (ret)
2695                         return ret;
2696
2697                 switch (id32) {
2698                 case BCM53115_DEVICE_ID:
2699                 case BCM53125_DEVICE_ID:
2700                 case BCM53128_DEVICE_ID:
2701                 case BCM53010_DEVICE_ID:
2702                 case BCM53011_DEVICE_ID:
2703                 case BCM53012_DEVICE_ID:
2704                 case BCM53018_DEVICE_ID:
2705                 case BCM53019_DEVICE_ID:
2706                         dev->chip_id = id32;
2707                         break;
2708                 default:
2709                         dev_err(dev->dev,
2710                                 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2711                                 id8, id32);
2712                         return -ENODEV;
2713                 }
2714         }
2715
2716         if (dev->chip_id == BCM5325_DEVICE_ID)
2717                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2718                                  &dev->core_rev);
2719         else
2720                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2721                                  &dev->core_rev);
2722 }
2723 EXPORT_SYMBOL(b53_switch_detect);
2724
2725 int b53_switch_register(struct b53_device *dev)
2726 {
2727         int ret;
2728
2729         if (dev->pdata) {
2730                 dev->chip_id = dev->pdata->chip_id;
2731                 dev->enabled_ports = dev->pdata->enabled_ports;
2732         }
2733
2734         if (!dev->chip_id && b53_switch_detect(dev))
2735                 return -EINVAL;
2736
2737         ret = b53_switch_init(dev);
2738         if (ret)
2739                 return ret;
2740
2741         dev_info(dev->dev, "found switch: %s, rev %i\n",
2742                  dev->name, dev->core_rev);
2743
2744         return dsa_register_switch(dev->ds);
2745 }
2746 EXPORT_SYMBOL(b53_switch_register);
2747
2748 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2749 MODULE_DESCRIPTION("B53 switch library");
2750 MODULE_LICENSE("Dual BSD/GPL");