2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234 for (i = 0; i < 10; i++) {
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
241 usleep_range(100, 200);
247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 entry |= VA_VALID_25;
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304 } else if (is5365(dev)) {
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
326 static void b53_set_forwarding(struct b53_device *dev, int enable)
328 struct dsa_switch *ds = dev->ds;
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
334 mgmt |= SM_SW_FWD_EN;
336 mgmt &= ~SM_SW_FWD_EN;
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
350 static void b53_enable_vlan(struct b53_device *dev, bool enable)
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
369 mgmt &= ~SM_SW_FWD_MODE;
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
379 vc0 &= ~VC0_RESERVED_1;
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
428 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
431 u16 max_size = JMS_MIN_SIZE;
433 if (is5325(dev) || is5365(dev))
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
440 port_mask |= JPM_10_100_JUMBO_EN;
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
447 static int b53_flush_arl(struct b53_device *dev, u8 mask)
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
454 for (i = 0; i < 10; i++) {
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
473 static int b53_fast_age_port(struct b53_device *dev, int port)
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
477 return b53_flush_arl(dev, FAST_AGE_PORT);
480 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
487 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
489 struct b53_device *dev = ds->priv;
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
504 static void b53_port_set_learning(struct b53_device *dev, int port,
509 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
514 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
517 static int b53_enable_port(struct dsa_switch *ds, int port,
518 struct phy_device *phy)
520 struct b53_device *dev = ds->priv;
521 unsigned int cpu_port = dev->cpu_port;
524 b53_port_set_learning(dev, port, false);
526 /* Clear the Rx and Tx disable bits and set to no spanning tree */
527 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
529 /* Set this port, and only this one to be in the default VLAN,
530 * if member of a bridge, restore its membership prior to
531 * bringing down this port.
533 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
536 pvlan |= dev->ports[port].vlan_ctl_mask;
537 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
539 b53_imp_vlan_setup(ds, cpu_port);
544 static void b53_disable_port(struct dsa_switch *ds, int port,
545 struct phy_device *phy)
547 struct b53_device *dev = ds->priv;
550 /* Disable Tx/Rx for the port */
551 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
552 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
553 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
556 static void b53_enable_cpu_port(struct b53_device *dev)
558 unsigned int cpu_port = dev->cpu_port;
561 /* BCM5325 CPU port is at 8 */
562 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
563 cpu_port = B53_CPU_PORT;
565 port_ctrl = PORT_CTRL_RX_BCST_EN |
566 PORT_CTRL_RX_MCST_EN |
567 PORT_CTRL_RX_UCST_EN;
568 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
570 b53_port_set_learning(dev, cpu_port, false);
573 static void b53_enable_mib(struct b53_device *dev)
577 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
578 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
579 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
582 static int b53_configure_vlan(struct b53_device *dev)
584 struct b53_vlan vl = { 0 };
587 /* clear all vlan entries */
588 if (is5325(dev) || is5365(dev)) {
589 for (i = 1; i < dev->num_vlans; i++)
590 b53_set_vlan_entry(dev, i, &vl);
592 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
595 b53_enable_vlan(dev, false);
597 b53_for_each_port(dev, i)
598 b53_write16(dev, B53_VLAN_PAGE,
599 B53_VLAN_PORT_DEF_TAG(i), 1);
601 if (!is5325(dev) && !is5365(dev))
602 b53_set_jumbo(dev, dev->enable_jumbo, false);
607 static void b53_switch_reset_gpio(struct b53_device *dev)
609 int gpio = dev->reset_gpio;
614 /* Reset sequence: RESET low(50ms)->high(20ms)
616 gpio_set_value(gpio, 0);
619 gpio_set_value(gpio, 1);
622 dev->current_page = 0xff;
625 static int b53_switch_reset(struct b53_device *dev)
627 unsigned int timeout = 1000;
630 b53_switch_reset_gpio(dev);
633 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
634 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
637 /* This is specific to 58xx devices here, do not use is58xx() which
638 * covers the larger Starfigther 2 family, including 7445/7278 which
639 * still use this driver as a library and need to perform the reset
642 if (dev->chip_id == BCM58XX_DEVICE_ID) {
643 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
644 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
645 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
648 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
652 usleep_range(1000, 2000);
653 } while (timeout-- > 0);
659 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
661 if (!(mgmt & SM_SW_FWD_EN)) {
662 mgmt &= ~SM_SW_FWD_MODE;
663 mgmt |= SM_SW_FWD_EN;
665 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
666 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
668 if (!(mgmt & SM_SW_FWD_EN)) {
669 dev_err(dev->dev, "Failed to enable switch!\n");
676 return b53_flush_arl(dev, FAST_AGE_STATIC);
679 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
681 struct b53_device *priv = ds->priv;
685 if (priv->ops->phy_read16)
686 ret = priv->ops->phy_read16(priv, addr, reg, &value);
688 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
691 return ret ? ret : value;
694 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
696 struct b53_device *priv = ds->priv;
698 if (priv->ops->phy_write16)
699 return priv->ops->phy_write16(priv, addr, reg, val);
701 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
704 static int b53_reset_switch(struct b53_device *priv)
707 priv->enable_jumbo = false;
709 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
710 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
712 return b53_switch_reset(priv);
715 static int b53_apply_config(struct b53_device *priv)
717 /* disable switching */
718 b53_set_forwarding(priv, 0);
720 b53_configure_vlan(priv);
722 /* enable switching */
723 b53_set_forwarding(priv, 1);
728 static void b53_reset_mib(struct b53_device *priv)
732 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
734 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
736 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
740 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
744 else if (is63xx(dev))
745 return b53_mibs_63xx;
746 else if (is58xx(dev))
747 return b53_mibs_58xx;
752 static unsigned int b53_get_mib_size(struct b53_device *dev)
755 return B53_MIBS_65_SIZE;
756 else if (is63xx(dev))
757 return B53_MIBS_63XX_SIZE;
758 else if (is58xx(dev))
759 return B53_MIBS_58XX_SIZE;
761 return B53_MIBS_SIZE;
764 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
766 struct b53_device *dev = ds->priv;
767 const struct b53_mib_desc *mibs = b53_get_mib(dev);
768 unsigned int mib_size = b53_get_mib_size(dev);
771 for (i = 0; i < mib_size; i++)
772 memcpy(data + i * ETH_GSTRING_LEN,
773 mibs[i].name, ETH_GSTRING_LEN);
775 EXPORT_SYMBOL(b53_get_strings);
777 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
779 struct b53_device *dev = ds->priv;
780 const struct b53_mib_desc *mibs = b53_get_mib(dev);
781 unsigned int mib_size = b53_get_mib_size(dev);
782 const struct b53_mib_desc *s;
786 if (is5365(dev) && port == 5)
789 mutex_lock(&dev->stats_mutex);
791 for (i = 0; i < mib_size; i++) {
795 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
799 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
806 mutex_unlock(&dev->stats_mutex);
808 EXPORT_SYMBOL(b53_get_ethtool_stats);
810 int b53_get_sset_count(struct dsa_switch *ds)
812 struct b53_device *dev = ds->priv;
814 return b53_get_mib_size(dev);
816 EXPORT_SYMBOL(b53_get_sset_count);
818 static int b53_setup(struct dsa_switch *ds)
820 struct b53_device *dev = ds->priv;
824 ret = b53_reset_switch(dev);
826 dev_err(ds->dev, "failed to reset switch\n");
832 ret = b53_apply_config(dev);
834 dev_err(ds->dev, "failed to apply configuration\n");
836 for (port = 0; port < dev->num_ports; port++) {
837 if (BIT(port) & ds->enabled_port_mask)
838 b53_enable_port(ds, port, NULL);
839 else if (dsa_is_cpu_port(ds, port))
840 b53_enable_cpu_port(dev);
842 b53_disable_port(ds, port, NULL);
848 static void b53_adjust_link(struct dsa_switch *ds, int port,
849 struct phy_device *phydev)
851 struct b53_device *dev = ds->priv;
852 u8 rgmii_ctrl = 0, reg = 0, off;
854 if (!phy_is_pseudo_fixed_link(phydev))
857 /* Override the port settings */
858 if (port == dev->cpu_port) {
859 off = B53_PORT_OVERRIDE_CTRL;
860 reg = PORT_OVERRIDE_EN;
862 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
866 /* Set the link UP */
868 reg |= PORT_OVERRIDE_LINK;
870 if (phydev->duplex == DUPLEX_FULL)
871 reg |= PORT_OVERRIDE_FULL_DUPLEX;
873 switch (phydev->speed) {
875 reg |= PORT_OVERRIDE_SPEED_2000M;
878 reg |= PORT_OVERRIDE_SPEED_1000M;
881 reg |= PORT_OVERRIDE_SPEED_100M;
884 reg |= PORT_OVERRIDE_SPEED_10M;
887 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
891 /* Enable flow control on BCM5301x's CPU port */
892 if (is5301x(dev) && port == dev->cpu_port)
893 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
896 if (phydev->asym_pause)
897 reg |= PORT_OVERRIDE_TX_FLOW;
898 reg |= PORT_OVERRIDE_RX_FLOW;
901 b53_write8(dev, B53_CTRL_PAGE, off, reg);
903 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
905 off = B53_RGMII_CTRL_IMP;
907 off = B53_RGMII_CTRL_P(port);
909 /* Configure the port RGMII clock delay by DLL disabled and
910 * tx_clk aligned timing (restoring to reset defaults)
912 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
913 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
914 RGMII_CTRL_TIMING_SEL);
916 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
917 * sure that we enable the port TX clock internal delay to
918 * account for this internal delay that is inserted, otherwise
919 * the switch won't be able to receive correctly.
921 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
922 * any delay neither on transmission nor reception, so the
923 * BCM53125 must also be configured accordingly to account for
924 * the lack of delay and introduce
926 * The BCM53125 switch has its RX clock and TX clock control
927 * swapped, hence the reason why we modify the TX clock path in
930 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
931 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
932 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
933 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
934 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
935 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
937 dev_info(ds->dev, "Configured port %d for %s\n", port,
938 phy_modes(phydev->interface));
941 /* configure MII port if necessary */
943 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
946 /* reverse mii needs to be enabled */
947 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
948 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
949 reg | PORT_OVERRIDE_RV_MII_25);
950 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
953 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
955 "Failed to enable reverse MII mode\n");
959 } else if (is5301x(dev)) {
960 if (port != dev->cpu_port) {
961 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
964 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
965 gmii_po |= GMII_PO_LINK |
970 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
975 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
979 EXPORT_SYMBOL(b53_vlan_filtering);
981 int b53_vlan_prepare(struct dsa_switch *ds, int port,
982 const struct switchdev_obj_port_vlan *vlan,
983 struct switchdev_trans *trans)
985 struct b53_device *dev = ds->priv;
987 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
990 if (vlan->vid_end >= dev->num_vlans)
993 b53_enable_vlan(dev, true);
997 EXPORT_SYMBOL(b53_vlan_prepare);
999 void b53_vlan_add(struct dsa_switch *ds, int port,
1000 const struct switchdev_obj_port_vlan *vlan,
1001 struct switchdev_trans *trans)
1003 struct b53_device *dev = ds->priv;
1004 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1005 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1006 unsigned int cpu_port = dev->cpu_port;
1007 struct b53_vlan *vl;
1010 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1011 vl = &dev->vlans[vid];
1013 b53_get_vlan_entry(dev, vid, vl);
1015 vl->members |= BIT(port) | BIT(cpu_port);
1017 vl->untag |= BIT(port);
1019 vl->untag &= ~BIT(port);
1020 vl->untag &= ~BIT(cpu_port);
1022 b53_set_vlan_entry(dev, vid, vl);
1023 b53_fast_age_vlan(dev, vid);
1027 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1029 b53_fast_age_vlan(dev, vid);
1032 EXPORT_SYMBOL(b53_vlan_add);
1034 int b53_vlan_del(struct dsa_switch *ds, int port,
1035 const struct switchdev_obj_port_vlan *vlan)
1037 struct b53_device *dev = ds->priv;
1038 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1039 struct b53_vlan *vl;
1043 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1045 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1046 vl = &dev->vlans[vid];
1048 b53_get_vlan_entry(dev, vid, vl);
1050 vl->members &= ~BIT(port);
1053 if (is5325(dev) || is5365(dev))
1060 vl->untag &= ~(BIT(port));
1062 b53_set_vlan_entry(dev, vid, vl);
1063 b53_fast_age_vlan(dev, vid);
1066 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1067 b53_fast_age_vlan(dev, pvid);
1071 EXPORT_SYMBOL(b53_vlan_del);
1073 /* Address Resolution Logic routines */
1074 static int b53_arl_op_wait(struct b53_device *dev)
1076 unsigned int timeout = 10;
1080 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1081 if (!(reg & ARLTBL_START_DONE))
1084 usleep_range(1000, 2000);
1085 } while (timeout--);
1087 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1092 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1099 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1100 reg |= ARLTBL_START_DONE;
1105 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1107 return b53_arl_op_wait(dev);
1110 static int b53_arl_read(struct b53_device *dev, u64 mac,
1111 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1114 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1118 ret = b53_arl_op_wait(dev);
1122 bitmap_zero(free_bins, dev->num_arl_entries);
1125 for (i = 0; i < dev->num_arl_entries; i++) {
1129 b53_read64(dev, B53_ARLIO_PAGE,
1130 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1131 b53_read32(dev, B53_ARLIO_PAGE,
1132 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1133 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1135 if (!(fwd_entry & ARLTBL_VALID)) {
1136 set_bit(i, free_bins);
1139 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1145 if (bitmap_weight(free_bins, dev->num_arl_entries) == 0)
1148 *idx = find_first_bit(free_bins, dev->num_arl_entries);
1153 static int b53_arl_op(struct b53_device *dev, int op, int port,
1154 const unsigned char *addr, u16 vid, bool is_valid)
1156 struct b53_arl_entry ent;
1158 u64 mac, mac_vid = 0;
1162 /* Convert the array into a 64-bit MAC */
1163 mac = ether_addr_to_u64(addr);
1165 /* Perform a read for the given MAC and VID */
1166 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1167 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1169 /* Issue a read operation for this MAC */
1170 ret = b53_arl_rw_op(dev, 1);
1174 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1175 /* If this is a read, just finish now */
1183 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1185 return is_valid ? ret : 0;
1187 /* We could not find a matching MAC, so reset to a new entry */
1188 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1193 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1198 memset(&ent, 0, sizeof(ent));
1200 ent.is_valid = is_valid;
1202 ent.is_static = true;
1203 memcpy(ent.mac, addr, ETH_ALEN);
1204 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1206 b53_write64(dev, B53_ARLIO_PAGE,
1207 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1208 b53_write32(dev, B53_ARLIO_PAGE,
1209 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1211 return b53_arl_rw_op(dev, 0);
1214 int b53_fdb_add(struct dsa_switch *ds, int port,
1215 const unsigned char *addr, u16 vid)
1217 struct b53_device *priv = ds->priv;
1219 /* 5325 and 5365 require some more massaging, but could
1220 * be supported eventually
1222 if (is5325(priv) || is5365(priv))
1225 return b53_arl_op(priv, 0, port, addr, vid, true);
1227 EXPORT_SYMBOL(b53_fdb_add);
1229 int b53_fdb_del(struct dsa_switch *ds, int port,
1230 const unsigned char *addr, u16 vid)
1232 struct b53_device *priv = ds->priv;
1234 return b53_arl_op(priv, 0, port, addr, vid, false);
1236 EXPORT_SYMBOL(b53_fdb_del);
1238 static int b53_arl_search_wait(struct b53_device *dev)
1240 unsigned int timeout = 1000;
1244 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1245 if (!(reg & ARL_SRCH_STDN))
1248 if (reg & ARL_SRCH_VLID)
1251 usleep_range(1000, 2000);
1252 } while (timeout--);
1257 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1258 struct b53_arl_entry *ent)
1263 b53_read64(dev, B53_ARLIO_PAGE,
1264 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1265 b53_read32(dev, B53_ARLIO_PAGE,
1266 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1267 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1270 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1271 dsa_fdb_dump_cb_t *cb, void *data)
1276 if (port != ent->port)
1279 return cb(ent->mac, ent->vid, ent->is_static, data);
1282 int b53_fdb_dump(struct dsa_switch *ds, int port,
1283 dsa_fdb_dump_cb_t *cb, void *data)
1285 struct b53_device *priv = ds->priv;
1286 struct b53_arl_entry results[2];
1287 unsigned int count = 0;
1291 /* Start search operation */
1292 reg = ARL_SRCH_STDN;
1293 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1296 ret = b53_arl_search_wait(priv);
1300 b53_arl_search_rd(priv, 0, &results[0]);
1301 ret = b53_fdb_copy(port, &results[0], cb, data);
1305 if (priv->num_arl_entries > 2) {
1306 b53_arl_search_rd(priv, 1, &results[1]);
1307 ret = b53_fdb_copy(port, &results[1], cb, data);
1311 if (!results[0].is_valid && !results[1].is_valid)
1315 } while (count++ < 1024);
1319 EXPORT_SYMBOL(b53_fdb_dump);
1321 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1323 struct b53_device *dev = ds->priv;
1324 s8 cpu_port = ds->dst->cpu_dp->index;
1328 /* Make this port leave the all VLANs join since we will have proper
1329 * VLAN entries from now on
1332 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1334 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1335 reg &= ~BIT(cpu_port);
1336 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1339 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1341 b53_for_each_port(dev, i) {
1342 if (ds->ports[i].bridge_dev != br)
1345 /* Add this local port to the remote port VLAN control
1346 * membership and update the remote port bitmask
1348 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1350 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1351 dev->ports[i].vlan_ctl_mask = reg;
1356 /* Configure the local port VLAN control membership to include
1357 * remote ports and update the local port bitmask
1359 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1360 dev->ports[port].vlan_ctl_mask = pvlan;
1362 b53_port_set_learning(dev, port, true);
1366 EXPORT_SYMBOL(b53_br_join);
1368 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1370 struct b53_device *dev = ds->priv;
1371 struct b53_vlan *vl = &dev->vlans[0];
1372 s8 cpu_port = ds->dst->cpu_dp->index;
1374 u16 pvlan, reg, pvid;
1376 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1378 b53_for_each_port(dev, i) {
1379 /* Don't touch the remaining ports */
1380 if (ds->ports[i].bridge_dev != br)
1383 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1385 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1386 dev->ports[port].vlan_ctl_mask = reg;
1388 /* Prevent self removal to preserve isolation */
1393 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1394 dev->ports[port].vlan_ctl_mask = pvlan;
1396 if (is5325(dev) || is5365(dev))
1401 /* Make this port join all VLANs without VLAN entries */
1403 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1405 if (!(reg & BIT(cpu_port)))
1406 reg |= BIT(cpu_port);
1407 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1409 b53_get_vlan_entry(dev, pvid, vl);
1410 vl->members |= BIT(port) | BIT(dev->cpu_port);
1411 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1412 b53_set_vlan_entry(dev, pvid, vl);
1414 b53_port_set_learning(dev, port, false);
1416 EXPORT_SYMBOL(b53_br_leave);
1418 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1420 struct b53_device *dev = ds->priv;
1425 case BR_STATE_DISABLED:
1426 hw_state = PORT_CTRL_DIS_STATE;
1428 case BR_STATE_LISTENING:
1429 hw_state = PORT_CTRL_LISTEN_STATE;
1431 case BR_STATE_LEARNING:
1432 hw_state = PORT_CTRL_LEARN_STATE;
1434 case BR_STATE_FORWARDING:
1435 hw_state = PORT_CTRL_FWD_STATE;
1437 case BR_STATE_BLOCKING:
1438 hw_state = PORT_CTRL_BLOCK_STATE;
1441 dev_err(ds->dev, "invalid STP state: %d\n", state);
1445 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1446 reg &= ~PORT_CTRL_STP_STATE_MASK;
1448 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1450 EXPORT_SYMBOL(b53_br_set_stp_state);
1452 void b53_br_fast_age(struct dsa_switch *ds, int port)
1454 struct b53_device *dev = ds->priv;
1456 if (b53_fast_age_port(dev, port))
1457 dev_err(ds->dev, "fast ageing failed\n");
1459 EXPORT_SYMBOL(b53_br_fast_age);
1461 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1463 return DSA_TAG_PROTO_NONE;
1466 int b53_mirror_add(struct dsa_switch *ds, int port,
1467 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1469 struct b53_device *dev = ds->priv;
1473 loc = B53_IG_MIR_CTL;
1475 loc = B53_EG_MIR_CTL;
1477 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1479 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1481 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1482 reg &= ~CAP_PORT_MASK;
1483 reg |= mirror->to_local_port;
1485 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1489 EXPORT_SYMBOL(b53_mirror_add);
1491 void b53_mirror_del(struct dsa_switch *ds, int port,
1492 struct dsa_mall_mirror_tc_entry *mirror)
1494 struct b53_device *dev = ds->priv;
1495 bool loc_disable = false, other_loc_disable = false;
1498 if (mirror->ingress)
1499 loc = B53_IG_MIR_CTL;
1501 loc = B53_EG_MIR_CTL;
1503 /* Update the desired ingress/egress register */
1504 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1506 if (!(reg & MIRROR_MASK))
1508 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1510 /* Now look at the other one to know if we can disable mirroring
1513 if (mirror->ingress)
1514 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
1516 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
1517 if (!(reg & MIRROR_MASK))
1518 other_loc_disable = true;
1520 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1521 /* Both no longer have ports, let's disable mirroring */
1522 if (loc_disable && other_loc_disable) {
1524 reg &= ~mirror->to_local_port;
1526 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1528 EXPORT_SYMBOL(b53_mirror_del);
1530 static const struct dsa_switch_ops b53_switch_ops = {
1531 .get_tag_protocol = b53_get_tag_protocol,
1533 .get_strings = b53_get_strings,
1534 .get_ethtool_stats = b53_get_ethtool_stats,
1535 .get_sset_count = b53_get_sset_count,
1536 .phy_read = b53_phy_read16,
1537 .phy_write = b53_phy_write16,
1538 .adjust_link = b53_adjust_link,
1539 .port_enable = b53_enable_port,
1540 .port_disable = b53_disable_port,
1541 .port_bridge_join = b53_br_join,
1542 .port_bridge_leave = b53_br_leave,
1543 .port_stp_state_set = b53_br_set_stp_state,
1544 .port_fast_age = b53_br_fast_age,
1545 .port_vlan_filtering = b53_vlan_filtering,
1546 .port_vlan_prepare = b53_vlan_prepare,
1547 .port_vlan_add = b53_vlan_add,
1548 .port_vlan_del = b53_vlan_del,
1549 .port_fdb_dump = b53_fdb_dump,
1550 .port_fdb_add = b53_fdb_add,
1551 .port_fdb_del = b53_fdb_del,
1552 .port_mirror_add = b53_mirror_add,
1553 .port_mirror_del = b53_mirror_del,
1556 struct b53_chip_data {
1558 const char *dev_name;
1569 #define B53_VTA_REGS \
1570 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1571 #define B53_VTA_REGS_9798 \
1572 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1573 #define B53_VTA_REGS_63XX \
1574 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1576 static const struct b53_chip_data b53_switch_chips[] = {
1578 .chip_id = BCM5325_DEVICE_ID,
1579 .dev_name = "BCM5325",
1581 .enabled_ports = 0x1f,
1583 .cpu_port = B53_CPU_PORT_25,
1584 .duplex_reg = B53_DUPLEX_STAT_FE,
1587 .chip_id = BCM5365_DEVICE_ID,
1588 .dev_name = "BCM5365",
1590 .enabled_ports = 0x1f,
1592 .cpu_port = B53_CPU_PORT_25,
1593 .duplex_reg = B53_DUPLEX_STAT_FE,
1596 .chip_id = BCM5389_DEVICE_ID,
1597 .dev_name = "BCM5389",
1599 .enabled_ports = 0x1f,
1601 .cpu_port = B53_CPU_PORT,
1602 .vta_regs = B53_VTA_REGS,
1603 .duplex_reg = B53_DUPLEX_STAT_GE,
1604 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1605 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1608 .chip_id = BCM5395_DEVICE_ID,
1609 .dev_name = "BCM5395",
1611 .enabled_ports = 0x1f,
1613 .cpu_port = B53_CPU_PORT,
1614 .vta_regs = B53_VTA_REGS,
1615 .duplex_reg = B53_DUPLEX_STAT_GE,
1616 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1617 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1620 .chip_id = BCM5397_DEVICE_ID,
1621 .dev_name = "BCM5397",
1623 .enabled_ports = 0x1f,
1625 .cpu_port = B53_CPU_PORT,
1626 .vta_regs = B53_VTA_REGS_9798,
1627 .duplex_reg = B53_DUPLEX_STAT_GE,
1628 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1629 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1632 .chip_id = BCM5398_DEVICE_ID,
1633 .dev_name = "BCM5398",
1635 .enabled_ports = 0x7f,
1637 .cpu_port = B53_CPU_PORT,
1638 .vta_regs = B53_VTA_REGS_9798,
1639 .duplex_reg = B53_DUPLEX_STAT_GE,
1640 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1641 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1644 .chip_id = BCM53115_DEVICE_ID,
1645 .dev_name = "BCM53115",
1647 .enabled_ports = 0x1f,
1649 .vta_regs = B53_VTA_REGS,
1650 .cpu_port = B53_CPU_PORT,
1651 .duplex_reg = B53_DUPLEX_STAT_GE,
1652 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1653 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1656 .chip_id = BCM53125_DEVICE_ID,
1657 .dev_name = "BCM53125",
1659 .enabled_ports = 0xff,
1661 .cpu_port = B53_CPU_PORT,
1662 .vta_regs = B53_VTA_REGS,
1663 .duplex_reg = B53_DUPLEX_STAT_GE,
1664 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1665 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1668 .chip_id = BCM53128_DEVICE_ID,
1669 .dev_name = "BCM53128",
1671 .enabled_ports = 0x1ff,
1673 .cpu_port = B53_CPU_PORT,
1674 .vta_regs = B53_VTA_REGS,
1675 .duplex_reg = B53_DUPLEX_STAT_GE,
1676 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1677 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1680 .chip_id = BCM63XX_DEVICE_ID,
1681 .dev_name = "BCM63xx",
1683 .enabled_ports = 0, /* pdata must provide them */
1685 .cpu_port = B53_CPU_PORT,
1686 .vta_regs = B53_VTA_REGS_63XX,
1687 .duplex_reg = B53_DUPLEX_STAT_63XX,
1688 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1689 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1692 .chip_id = BCM53010_DEVICE_ID,
1693 .dev_name = "BCM53010",
1695 .enabled_ports = 0x1f,
1697 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1698 .vta_regs = B53_VTA_REGS,
1699 .duplex_reg = B53_DUPLEX_STAT_GE,
1700 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1701 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1704 .chip_id = BCM53011_DEVICE_ID,
1705 .dev_name = "BCM53011",
1707 .enabled_ports = 0x1bf,
1709 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1710 .vta_regs = B53_VTA_REGS,
1711 .duplex_reg = B53_DUPLEX_STAT_GE,
1712 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1713 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1716 .chip_id = BCM53012_DEVICE_ID,
1717 .dev_name = "BCM53012",
1719 .enabled_ports = 0x1bf,
1721 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1722 .vta_regs = B53_VTA_REGS,
1723 .duplex_reg = B53_DUPLEX_STAT_GE,
1724 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1725 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1728 .chip_id = BCM53018_DEVICE_ID,
1729 .dev_name = "BCM53018",
1731 .enabled_ports = 0x1f,
1733 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1734 .vta_regs = B53_VTA_REGS,
1735 .duplex_reg = B53_DUPLEX_STAT_GE,
1736 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1737 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1740 .chip_id = BCM53019_DEVICE_ID,
1741 .dev_name = "BCM53019",
1743 .enabled_ports = 0x1f,
1745 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1746 .vta_regs = B53_VTA_REGS,
1747 .duplex_reg = B53_DUPLEX_STAT_GE,
1748 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1749 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1752 .chip_id = BCM58XX_DEVICE_ID,
1753 .dev_name = "BCM585xx/586xx/88312",
1755 .enabled_ports = 0x1ff,
1757 .cpu_port = B53_CPU_PORT,
1758 .vta_regs = B53_VTA_REGS,
1759 .duplex_reg = B53_DUPLEX_STAT_GE,
1760 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1761 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1764 .chip_id = BCM7445_DEVICE_ID,
1765 .dev_name = "BCM7445",
1767 .enabled_ports = 0x1ff,
1769 .cpu_port = B53_CPU_PORT,
1770 .vta_regs = B53_VTA_REGS,
1771 .duplex_reg = B53_DUPLEX_STAT_GE,
1772 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1773 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1776 .chip_id = BCM7278_DEVICE_ID,
1777 .dev_name = "BCM7278",
1779 .enabled_ports = 0x1ff,
1781 .cpu_port = B53_CPU_PORT,
1782 .vta_regs = B53_VTA_REGS,
1783 .duplex_reg = B53_DUPLEX_STAT_GE,
1784 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1785 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1789 static int b53_switch_init(struct b53_device *dev)
1794 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1795 const struct b53_chip_data *chip = &b53_switch_chips[i];
1797 if (chip->chip_id == dev->chip_id) {
1798 if (!dev->enabled_ports)
1799 dev->enabled_ports = chip->enabled_ports;
1800 dev->name = chip->dev_name;
1801 dev->duplex_reg = chip->duplex_reg;
1802 dev->vta_regs[0] = chip->vta_regs[0];
1803 dev->vta_regs[1] = chip->vta_regs[1];
1804 dev->vta_regs[2] = chip->vta_regs[2];
1805 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1806 dev->cpu_port = chip->cpu_port;
1807 dev->num_vlans = chip->vlans;
1808 dev->num_arl_entries = chip->arl_entries;
1813 /* check which BCM5325x version we have */
1817 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1819 /* check reserved bits */
1825 /* BCM5325F - do not use port 4 */
1826 dev->enabled_ports &= ~BIT(4);
1829 /* On the BCM47XX SoCs this is the supported internal switch.*/
1830 #ifndef CONFIG_BCM47XX
1837 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1840 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1841 /* use second IMP port if GMII is enabled */
1842 if (strap_value & SV_GMII_CTRL_115)
1846 dev->enabled_ports |= BIT(dev->cpu_port);
1847 dev->num_ports = fls(dev->enabled_ports);
1849 dev->ports = devm_kzalloc(dev->dev,
1850 sizeof(struct b53_port) * dev->num_ports,
1855 dev->vlans = devm_kzalloc(dev->dev,
1856 sizeof(struct b53_vlan) * dev->num_vlans,
1861 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1862 if (dev->reset_gpio >= 0) {
1863 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1864 GPIOF_OUT_INIT_HIGH, "robo_reset");
1872 struct b53_device *b53_switch_alloc(struct device *base,
1873 const struct b53_io_ops *ops,
1876 struct dsa_switch *ds;
1877 struct b53_device *dev;
1879 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
1883 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1893 ds->ops = &b53_switch_ops;
1894 mutex_init(&dev->reg_mutex);
1895 mutex_init(&dev->stats_mutex);
1899 EXPORT_SYMBOL(b53_switch_alloc);
1901 int b53_switch_detect(struct b53_device *dev)
1908 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1914 /* BCM5325 and BCM5365 do not have this register so reads
1915 * return 0. But the read operation did succeed, so assume this
1918 * Next check if we can write to the 5325's VTA register; for
1919 * 5365 it is read only.
1921 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1922 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1925 dev->chip_id = BCM5325_DEVICE_ID;
1927 dev->chip_id = BCM5365_DEVICE_ID;
1929 case BCM5389_DEVICE_ID:
1930 case BCM5395_DEVICE_ID:
1931 case BCM5397_DEVICE_ID:
1932 case BCM5398_DEVICE_ID:
1936 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1941 case BCM53115_DEVICE_ID:
1942 case BCM53125_DEVICE_ID:
1943 case BCM53128_DEVICE_ID:
1944 case BCM53010_DEVICE_ID:
1945 case BCM53011_DEVICE_ID:
1946 case BCM53012_DEVICE_ID:
1947 case BCM53018_DEVICE_ID:
1948 case BCM53019_DEVICE_ID:
1949 dev->chip_id = id32;
1952 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1958 if (dev->chip_id == BCM5325_DEVICE_ID)
1959 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1962 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1965 EXPORT_SYMBOL(b53_switch_detect);
1967 int b53_switch_register(struct b53_device *dev)
1972 dev->chip_id = dev->pdata->chip_id;
1973 dev->enabled_ports = dev->pdata->enabled_ports;
1976 if (!dev->chip_id && b53_switch_detect(dev))
1979 ret = b53_switch_init(dev);
1983 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1985 return dsa_register_switch(dev->ds);
1987 EXPORT_SYMBOL(b53_switch_register);
1989 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1990 MODULE_DESCRIPTION("B53 switch library");
1991 MODULE_LICENSE("Dual BSD/GPL");