drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/if_bridge.h>
  31 #include <net/dsa.h>
  32
  33 #include "b53_regs.h"
  34 #include "b53_priv.h"
  35
  36 struct b53_mib_desc {
  37         u8 size;
  38         u8 offset;
  39         const char *name;
  40 };
  41
  42 /* BCM5365 MIB counters */
  43 static const struct b53_mib_desc b53_mibs_65[] = {
  44         { 8, 0x00, "TxOctets" },
  45         { 4, 0x08, "TxDropPkts" },
  46         { 4, 0x10, "TxBroadcastPkts" },
  47         { 4, 0x14, "TxMulticastPkts" },
  48         { 4, 0x18, "TxUnicastPkts" },
  49         { 4, 0x1c, "TxCollisions" },
  50         { 4, 0x20, "TxSingleCollision" },
  51         { 4, 0x24, "TxMultipleCollision" },
  52         { 4, 0x28, "TxDeferredTransmit" },
  53         { 4, 0x2c, "TxLateCollision" },
  54         { 4, 0x30, "TxExcessiveCollision" },
  55         { 4, 0x38, "TxPausePkts" },
  56         { 8, 0x44, "RxOctets" },
  57         { 4, 0x4c, "RxUndersizePkts" },
  58         { 4, 0x50, "RxPausePkts" },
  59         { 4, 0x54, "Pkts64Octets" },
  60         { 4, 0x58, "Pkts65to127Octets" },
  61         { 4, 0x5c, "Pkts128to255Octets" },
  62         { 4, 0x60, "Pkts256to511Octets" },
  63         { 4, 0x64, "Pkts512to1023Octets" },
  64         { 4, 0x68, "Pkts1024to1522Octets" },
  65         { 4, 0x6c, "RxOversizePkts" },
  66         { 4, 0x70, "RxJabbers" },
  67         { 4, 0x74, "RxAlignmentErrors" },
  68         { 4, 0x78, "RxFCSErrors" },
  69         { 8, 0x7c, "RxGoodOctets" },
  70         { 4, 0x84, "RxDropPkts" },
  71         { 4, 0x88, "RxUnicastPkts" },
  72         { 4, 0x8c, "RxMulticastPkts" },
  73         { 4, 0x90, "RxBroadcastPkts" },
  74         { 4, 0x94, "RxSAChanges" },
  75         { 4, 0x98, "RxFragments" },
  76 };
  77
  78 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  79
  80 /* BCM63xx MIB counters */
  81 static const struct b53_mib_desc b53_mibs_63xx[] = {
  82         { 8, 0x00, "TxOctets" },
  83         { 4, 0x08, "TxDropPkts" },
  84         { 4, 0x0c, "TxQoSPkts" },
  85         { 4, 0x10, "TxBroadcastPkts" },
  86         { 4, 0x14, "TxMulticastPkts" },
  87         { 4, 0x18, "TxUnicastPkts" },
  88         { 4, 0x1c, "TxCollisions" },
  89         { 4, 0x20, "TxSingleCollision" },
  90         { 4, 0x24, "TxMultipleCollision" },
  91         { 4, 0x28, "TxDeferredTransmit" },
  92         { 4, 0x2c, "TxLateCollision" },
  93         { 4, 0x30, "TxExcessiveCollision" },
  94         { 4, 0x38, "TxPausePkts" },
  95         { 8, 0x3c, "TxQoSOctets" },
  96         { 8, 0x44, "RxOctets" },
  97         { 4, 0x4c, "RxUndersizePkts" },
  98         { 4, 0x50, "RxPausePkts" },
  99         { 4, 0x54, "Pkts64Octets" },
 100         { 4, 0x58, "Pkts65to127Octets" },
 101         { 4, 0x5c, "Pkts128to255Octets" },
 102         { 4, 0x60, "Pkts256to511Octets" },
 103         { 4, 0x64, "Pkts512to1023Octets" },
 104         { 4, 0x68, "Pkts1024to1522Octets" },
 105         { 4, 0x6c, "RxOversizePkts" },
 106         { 4, 0x70, "RxJabbers" },
 107         { 4, 0x74, "RxAlignmentErrors" },
 108         { 4, 0x78, "RxFCSErrors" },
 109         { 8, 0x7c, "RxGoodOctets" },
 110         { 4, 0x84, "RxDropPkts" },
 111         { 4, 0x88, "RxUnicastPkts" },
 112         { 4, 0x8c, "RxMulticastPkts" },
 113         { 4, 0x90, "RxBroadcastPkts" },
 114         { 4, 0x94, "RxSAChanges" },
 115         { 4, 0x98, "RxFragments" },
 116         { 4, 0xa0, "RxSymbolErrors" },
 117         { 4, 0xa4, "RxQoSPkts" },
 118         { 8, 0xa8, "RxQoSOctets" },
 119         { 4, 0xb0, "Pkts1523to2047Octets" },
 120         { 4, 0xb4, "Pkts2048to4095Octets" },
 121         { 4, 0xb8, "Pkts4096to8191Octets" },
 122         { 4, 0xbc, "Pkts8192to9728Octets" },
 123         { 4, 0xc0, "RxDiscarded" },
 124 };
 125
 126 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 127
 128 /* MIB counters */
 129 static const struct b53_mib_desc b53_mibs[] = {
 130         { 8, 0x00, "TxOctets" },
 131         { 4, 0x08, "TxDropPkts" },
 132         { 4, 0x10, "TxBroadcastPkts" },
 133         { 4, 0x14, "TxMulticastPkts" },
 134         { 4, 0x18, "TxUnicastPkts" },
 135         { 4, 0x1c, "TxCollisions" },
 136         { 4, 0x20, "TxSingleCollision" },
 137         { 4, 0x24, "TxMultipleCollision" },
 138         { 4, 0x28, "TxDeferredTransmit" },
 139         { 4, 0x2c, "TxLateCollision" },
 140         { 4, 0x30, "TxExcessiveCollision" },
 141         { 4, 0x38, "TxPausePkts" },
 142         { 8, 0x50, "RxOctets" },
 143         { 4, 0x58, "RxUndersizePkts" },
 144         { 4, 0x5c, "RxPausePkts" },
 145         { 4, 0x60, "Pkts64Octets" },
 146         { 4, 0x64, "Pkts65to127Octets" },
 147         { 4, 0x68, "Pkts128to255Octets" },
 148         { 4, 0x6c, "Pkts256to511Octets" },
 149         { 4, 0x70, "Pkts512to1023Octets" },
 150         { 4, 0x74, "Pkts1024to1522Octets" },
 151         { 4, 0x78, "RxOversizePkts" },
 152         { 4, 0x7c, "RxJabbers" },
 153         { 4, 0x80, "RxAlignmentErrors" },
 154         { 4, 0x84, "RxFCSErrors" },
 155         { 8, 0x88, "RxGoodOctets" },
 156         { 4, 0x90, "RxDropPkts" },
 157         { 4, 0x94, "RxUnicastPkts" },
 158         { 4, 0x98, "RxMulticastPkts" },
 159         { 4, 0x9c, "RxBroadcastPkts" },
 160         { 4, 0xa0, "RxSAChanges" },
 161         { 4, 0xa4, "RxFragments" },
 162         { 4, 0xa8, "RxJumboPkts" },
 163         { 4, 0xac, "RxSymbolErrors" },
 164         { 4, 0xc0, "RxDiscarded" },
 165 };
 166
 167 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 168
 169 static const struct b53_mib_desc b53_mibs_58xx[] = {
 170         { 8, 0x00, "TxOctets" },
 171         { 4, 0x08, "TxDropPkts" },
 172         { 4, 0x0c, "TxQPKTQ0" },
 173         { 4, 0x10, "TxBroadcastPkts" },
 174         { 4, 0x14, "TxMulticastPkts" },
 175         { 4, 0x18, "TxUnicastPKts" },
 176         { 4, 0x1c, "TxCollisions" },
 177         { 4, 0x20, "TxSingleCollision" },
 178         { 4, 0x24, "TxMultipleCollision" },
 179         { 4, 0x28, "TxDeferredCollision" },
 180         { 4, 0x2c, "TxLateCollision" },
 181         { 4, 0x30, "TxExcessiveCollision" },
 182         { 4, 0x34, "TxFrameInDisc" },
 183         { 4, 0x38, "TxPausePkts" },
 184         { 4, 0x3c, "TxQPKTQ1" },
 185         { 4, 0x40, "TxQPKTQ2" },
 186         { 4, 0x44, "TxQPKTQ3" },
 187         { 4, 0x48, "TxQPKTQ4" },
 188         { 4, 0x4c, "TxQPKTQ5" },
 189         { 8, 0x50, "RxOctets" },
 190         { 4, 0x58, "RxUndersizePkts" },
 191         { 4, 0x5c, "RxPausePkts" },
 192         { 4, 0x60, "RxPkts64Octets" },
 193         { 4, 0x64, "RxPkts65to127Octets" },
 194         { 4, 0x68, "RxPkts128to255Octets" },
 195         { 4, 0x6c, "RxPkts256to511Octets" },
 196         { 4, 0x70, "RxPkts512to1023Octets" },
 197         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 198         { 4, 0x78, "RxOversizePkts" },
 199         { 4, 0x7c, "RxJabbers" },
 200         { 4, 0x80, "RxAlignmentErrors" },
 201         { 4, 0x84, "RxFCSErrors" },
 202         { 8, 0x88, "RxGoodOctets" },
 203         { 4, 0x90, "RxDropPkts" },
 204         { 4, 0x94, "RxUnicastPkts" },
 205         { 4, 0x98, "RxMulticastPkts" },
 206         { 4, 0x9c, "RxBroadcastPkts" },
 207         { 4, 0xa0, "RxSAChanges" },
 208         { 4, 0xa4, "RxFragments" },
 209         { 4, 0xa8, "RxJumboPkt" },
 210         { 4, 0xac, "RxSymblErr" },
 211         { 4, 0xb0, "InRangeErrCount" },
 212         { 4, 0xb4, "OutRangeErrCount" },
 213         { 4, 0xb8, "EEELpiEvent" },
 214         { 4, 0xbc, "EEELpiDuration" },
 215         { 4, 0xc0, "RxDiscard" },
 216         { 4, 0xc8, "TxQPKTQ6" },
 217         { 4, 0xcc, "TxQPKTQ7" },
 218         { 4, 0xd0, "TxPkts64Octets" },
 219         { 4, 0xd4, "TxPkts65to127Octets" },
 220         { 4, 0xd8, "TxPkts128to255Octets" },
 221         { 4, 0xdc, "TxPkts256to511Ocets" },
 222         { 4, 0xe0, "TxPkts512to1023Ocets" },
 223         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 224 };
 225
 226 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 227
 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 229 {
 230         unsigned int i;
 231
 232         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 233
 234         for (i = 0; i < 10; i++) {
 235                 u8 vta;
 236
 237                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 238                 if (!(vta & VTA_START_CMD))
 239                         return 0;
 240
 241                 usleep_range(100, 200);
 242         }
 243
 244         return -EIO;
 245 }
 246
 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 248                                struct b53_vlan *vlan)
 249 {
 250         if (is5325(dev)) {
 251                 u32 entry = 0;
 252
 253                 if (vlan->members) {
 254                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 255                                  VA_UNTAG_S_25) | vlan->members;
 256                         if (dev->core_rev >= 3)
 257                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 258                         else
 259                                 entry |= VA_VALID_25;
 260                 }
 261
 262                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 263                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 264                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 265         } else if (is5365(dev)) {
 266                 u16 entry = 0;
 267
 268                 if (vlan->members)
 269                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 270                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 271
 272                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 274                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 275         } else {
 276                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 277                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 278                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 279
 280                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 281         }
 282
 283         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 284                 vid, vlan->members, vlan->untag);
 285 }
 286
 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 288                                struct b53_vlan *vlan)
 289 {
 290         if (is5325(dev)) {
 291                 u32 entry = 0;
 292
 293                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 294                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 295                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 296
 297                 if (dev->core_rev >= 3)
 298                         vlan->valid = !!(entry & VA_VALID_25_R4);
 299                 else
 300                         vlan->valid = !!(entry & VA_VALID_25);
 301                 vlan->members = entry & VA_MEMBER_MASK;
 302                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 303
 304         } else if (is5365(dev)) {
 305                 u16 entry = 0;
 306
 307                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 308                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 309                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 310
 311                 vlan->valid = !!(entry & VA_VALID_65);
 312                 vlan->members = entry & VA_MEMBER_MASK;
 313                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 314         } else {
 315                 u32 entry = 0;
 316
 317                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 318                 b53_do_vlan_op(dev, VTA_CMD_READ);
 319                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 320                 vlan->members = entry & VTE_MEMBERS;
 321                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 322                 vlan->valid = true;
 323         }
 324 }
 325
 326 static void b53_set_forwarding(struct b53_device *dev, int enable)
 327 {
 328         u8 mgmt;
 329
 330         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 331
 332         if (enable)
 333                 mgmt |= SM_SW_FWD_EN;
 334         else
 335                 mgmt &= ~SM_SW_FWD_EN;
 336
 337         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 338
 339         /* Include IMP port in dumb forwarding mode
 340          */
 341         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 342         mgmt |= B53_MII_DUMB_FWDG_EN;
 343         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 344 }
 345
 346 static void b53_enable_vlan(struct b53_device *dev, bool enable,
 347                             bool enable_filtering)
 348 {
 349         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 350
 351         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 352         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 353         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 354
 355         if (is5325(dev) || is5365(dev)) {
 356                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 357                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 358         } else if (is63xx(dev)) {
 359                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 360                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 361         } else {
 362                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 364         }
 365
 366         mgmt &= ~SM_SW_FWD_MODE;
 367
 368         if (enable) {
 369                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 370                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 371                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 372                 if (enable_filtering) {
 373                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 374                         vc5 |= VC5_DROP_VTABLE_MISS;
 375                 } else {
 376                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 377                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 378                 }
 379
 380                 if (is5325(dev))
 381                         vc0 &= ~VC0_RESERVED_1;
 382
 383                 if (is5325(dev) || is5365(dev))
 384                         vc1 |= VC1_RX_MCST_TAG_EN;
 385
 386         } else {
 387                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 388                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 389                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 390                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 391
 392                 if (is5325(dev) || is5365(dev))
 393                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 394                 else
 395                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 396
 397                 if (is5325(dev) || is5365(dev))
 398                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 399         }
 400
 401         if (!is5325(dev) && !is5365(dev))
 402                 vc5 &= ~VC5_VID_FFF_EN;
 403
 404         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 405         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 406
 407         if (is5325(dev) || is5365(dev)) {
 408                 /* enable the high 8 bit vid check on 5325 */
 409                 if (is5325(dev) && enable)
 410                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 411                                    VC3_HIGH_8BIT_EN);
 412                 else
 413                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 414
 415                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 416                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 417         } else if (is63xx(dev)) {
 418                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 419                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 420                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 421         } else {
 422                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 425         }
 426
 427         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 428
 429         dev->vlan_enabled = enable;
 430         dev->vlan_filtering_enabled = enable_filtering;
 431 }
 432
 433 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 434 {
 435         u32 port_mask = 0;
 436         u16 max_size = JMS_MIN_SIZE;
 437
 438         if (is5325(dev) || is5365(dev))
 439                 return -EINVAL;
 440
 441         if (enable) {
 442                 port_mask = dev->enabled_ports;
 443                 max_size = JMS_MAX_SIZE;
 444                 if (allow_10_100)
 445                         port_mask |= JPM_10_100_JUMBO_EN;
 446         }
 447
 448         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 449         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 450 }
 451
 452 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 453 {
 454         unsigned int i;
 455
 456         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 457                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 458
 459         for (i = 0; i < 10; i++) {
 460                 u8 fast_age_ctrl;
 461
 462                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 463                           &fast_age_ctrl);
 464
 465                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 466                         goto out;
 467
 468                 msleep(1);
 469         }
 470
 471         return -ETIMEDOUT;
 472 out:
 473         /* Only age dynamic entries (default behavior) */
 474         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 475         return 0;
 476 }
 477
 478 static int b53_fast_age_port(struct b53_device *dev, int port)
 479 {
 480         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 481
 482         return b53_flush_arl(dev, FAST_AGE_PORT);
 483 }
 484
 485 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 486 {
 487         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 488
 489         return b53_flush_arl(dev, FAST_AGE_VLAN);
 490 }
 491
 492 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 493 {
 494         struct b53_device *dev = ds->priv;
 495         unsigned int i;
 496         u16 pvlan;
 497
 498         /* Enable the IMP port to be in the same VLAN as the other ports
 499          * on a per-port basis such that we only have Port i and IMP in
 500          * the same VLAN.
 501          */
 502         b53_for_each_port(dev, i) {
 503                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 504                 pvlan |= BIT(cpu_port);
 505                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 506         }
 507 }
 508 EXPORT_SYMBOL(b53_imp_vlan_setup);
 509
 510 static void b53_port_set_learning(struct b53_device *dev, int port,
 511                                   bool learning)
 512 {
 513         u16 reg;
 514
 515         b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
 516         if (learning)
 517                 reg &= ~BIT(port);
 518         else
 519                 reg |= BIT(port);
 520         b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
 521 }
 522
 523 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 524 {
 525         struct b53_device *dev = ds->priv;
 526         unsigned int cpu_port = ds->ports[port].cpu_dp->index;
 527         u16 pvlan;
 528
 529         b53_port_set_learning(dev, port, false);
 530
 531         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 532         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 533
 534         /* Set this port, and only this one to be in the default VLAN,
 535          * if member of a bridge, restore its membership prior to
 536          * bringing down this port.
 537          */
 538         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 539         pvlan &= ~0x1ff;
 540         pvlan |= BIT(port);
 541         pvlan |= dev->ports[port].vlan_ctl_mask;
 542         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 543
 544         b53_imp_vlan_setup(ds, cpu_port);
 545
 546         /* If EEE was enabled, restore it */
 547         if (dev->ports[port].eee.eee_enabled)
 548                 b53_eee_enable_set(ds, port, true);
 549
 550         return 0;
 551 }
 552 EXPORT_SYMBOL(b53_enable_port);
 553
 554 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 555 {
 556         struct b53_device *dev = ds->priv;
 557         u8 reg;
 558
 559         /* Disable Tx/Rx for the port */
 560         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 561         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 562         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 563 }
 564 EXPORT_SYMBOL(b53_disable_port);
 565
 566 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 567 {
 568         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 569                          DSA_TAG_PROTO_NONE);
 570         struct b53_device *dev = ds->priv;
 571         u8 hdr_ctl, val;
 572         u16 reg;
 573
 574         /* Resolve which bit controls the Broadcom tag */
 575         switch (port) {
 576         case 8:
 577                 val = BRCM_HDR_P8_EN;
 578                 break;
 579         case 7:
 580                 val = BRCM_HDR_P7_EN;
 581                 break;
 582         case 5:
 583                 val = BRCM_HDR_P5_EN;
 584                 break;
 585         default:
 586                 val = 0;
 587                 break;
 588         }
 589
 590         /* Enable Broadcom tags for IMP port */
 591         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 592         if (tag_en)
 593                 hdr_ctl |= val;
 594         else
 595                 hdr_ctl &= ~val;
 596         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 597
 598         /* Registers below are only accessible on newer devices */
 599         if (!is58xx(dev))
 600                 return;
 601
 602         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 603          * allow us to tag outgoing frames
 604          */
 605         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 606         if (tag_en)
 607                 reg &= ~BIT(port);
 608         else
 609                 reg |= BIT(port);
 610         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 611
 612         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 613          * allow delivering frames to the per-port net_devices
 614          */
 615         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 616         if (tag_en)
 617                 reg &= ~BIT(port);
 618         else
 619                 reg |= BIT(port);
 620         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 621 }
 622 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 623
 624 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 625 {
 626         u8 port_ctrl;
 627
 628         /* BCM5325 CPU port is at 8 */
 629         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 630                 port = B53_CPU_PORT;
 631
 632         port_ctrl = PORT_CTRL_RX_BCST_EN |
 633                     PORT_CTRL_RX_MCST_EN |
 634                     PORT_CTRL_RX_UCST_EN;
 635         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 636
 637         b53_brcm_hdr_setup(dev->ds, port);
 638         b53_port_set_learning(dev, port, false);
 639 }
 640
 641 static void b53_enable_mib(struct b53_device *dev)
 642 {
 643         u8 gc;
 644
 645         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 646         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 647         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 648 }
 649
 650 static u16 b53_default_pvid(struct b53_device *dev)
 651 {
 652         if (is5325(dev) || is5365(dev))
 653                 return 1;
 654         else
 655                 return 0;
 656 }
 657
 658 int b53_configure_vlan(struct dsa_switch *ds)
 659 {
 660         struct b53_device *dev = ds->priv;
 661         struct b53_vlan vl = { 0 };
 662         int i, def_vid;
 663
 664         def_vid = b53_default_pvid(dev);
 665
 666         /* clear all vlan entries */
 667         if (is5325(dev) || is5365(dev)) {
 668                 for (i = def_vid; i < dev->num_vlans; i++)
 669                         b53_set_vlan_entry(dev, i, &vl);
 670         } else {
 671                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 672         }
 673
 674         b53_enable_vlan(dev, dev->vlan_enabled, dev->vlan_filtering_enabled);
 675
 676         b53_for_each_port(dev, i)
 677                 b53_write16(dev, B53_VLAN_PAGE,
 678                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 679
 680         if (!is5325(dev) && !is5365(dev))
 681                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 682
 683         return 0;
 684 }
 685 EXPORT_SYMBOL(b53_configure_vlan);
 686
 687 static void b53_switch_reset_gpio(struct b53_device *dev)
 688 {
 689         int gpio = dev->reset_gpio;
 690
 691         if (gpio < 0)
 692                 return;
 693
 694         /* Reset sequence: RESET low(50ms)->high(20ms)
 695          */
 696         gpio_set_value(gpio, 0);
 697         mdelay(50);
 698
 699         gpio_set_value(gpio, 1);
 700         mdelay(20);
 701
 702         dev->current_page = 0xff;
 703 }
 704
 705 static int b53_switch_reset(struct b53_device *dev)
 706 {
 707         unsigned int timeout = 1000;
 708         u8 mgmt, reg;
 709
 710         b53_switch_reset_gpio(dev);
 711
 712         if (is539x(dev)) {
 713                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 714                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 715         }
 716
 717         /* This is specific to 58xx devices here, do not use is58xx() which
 718          * covers the larger Starfigther 2 family, including 7445/7278 which
 719          * still use this driver as a library and need to perform the reset
 720          * earlier.
 721          */
 722         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 723             dev->chip_id == BCM583XX_DEVICE_ID) {
 724                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 725                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 726                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 727
 728                 do {
 729                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 730                         if (!(reg & SW_RST))
 731                                 break;
 732
 733                         usleep_range(1000, 2000);
 734                 } while (timeout-- > 0);
 735
 736                 if (timeout == 0)
 737                         return -ETIMEDOUT;
 738         }
 739
 740         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 741
 742         if (!(mgmt & SM_SW_FWD_EN)) {
 743                 mgmt &= ~SM_SW_FWD_MODE;
 744                 mgmt |= SM_SW_FWD_EN;
 745
 746                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 747                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 748
 749                 if (!(mgmt & SM_SW_FWD_EN)) {
 750                         dev_err(dev->dev, "Failed to enable switch!\n");
 751                         return -EINVAL;
 752                 }
 753         }
 754
 755         b53_enable_mib(dev);
 756
 757         return b53_flush_arl(dev, FAST_AGE_STATIC);
 758 }
 759
 760 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 761 {
 762         struct b53_device *priv = ds->priv;
 763         u16 value = 0;
 764         int ret;
 765
 766         if (priv->ops->phy_read16)
 767                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 768         else
 769                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 770                                  reg * 2, &value);
 771
 772         return ret ? ret : value;
 773 }
 774
 775 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 776 {
 777         struct b53_device *priv = ds->priv;
 778
 779         if (priv->ops->phy_write16)
 780                 return priv->ops->phy_write16(priv, addr, reg, val);
 781
 782         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 783 }
 784
 785 static int b53_reset_switch(struct b53_device *priv)
 786 {
 787         /* reset vlans */
 788         priv->enable_jumbo = false;
 789
 790         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 791         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 792
 793         return b53_switch_reset(priv);
 794 }
 795
 796 static int b53_apply_config(struct b53_device *priv)
 797 {
 798         /* disable switching */
 799         b53_set_forwarding(priv, 0);
 800
 801         b53_configure_vlan(priv->ds);
 802
 803         /* enable switching */
 804         b53_set_forwarding(priv, 1);
 805
 806         return 0;
 807 }
 808
 809 static void b53_reset_mib(struct b53_device *priv)
 810 {
 811         u8 gc;
 812
 813         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 814
 815         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 816         msleep(1);
 817         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 818         msleep(1);
 819 }
 820
 821 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 822 {
 823         if (is5365(dev))
 824                 return b53_mibs_65;
 825         else if (is63xx(dev))
 826                 return b53_mibs_63xx;
 827         else if (is58xx(dev))
 828                 return b53_mibs_58xx;
 829         else
 830                 return b53_mibs;
 831 }
 832
 833 static unsigned int b53_get_mib_size(struct b53_device *dev)
 834 {
 835         if (is5365(dev))
 836                 return B53_MIBS_65_SIZE;
 837         else if (is63xx(dev))
 838                 return B53_MIBS_63XX_SIZE;
 839         else if (is58xx(dev))
 840                 return B53_MIBS_58XX_SIZE;
 841         else
 842                 return B53_MIBS_SIZE;
 843 }
 844
 845 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 846 {
 847         /* These ports typically do not have built-in PHYs */
 848         switch (port) {
 849         case B53_CPU_PORT_25:
 850         case 7:
 851         case B53_CPU_PORT:
 852                 return NULL;
 853         }
 854
 855         return mdiobus_get_phy(ds->slave_mii_bus, port);
 856 }
 857
 858 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 859                      uint8_t *data)
 860 {
 861         struct b53_device *dev = ds->priv;
 862         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 863         unsigned int mib_size = b53_get_mib_size(dev);
 864         struct phy_device *phydev;
 865         unsigned int i;
 866
 867         if (stringset == ETH_SS_STATS) {
 868                 for (i = 0; i < mib_size; i++)
 869                         strlcpy(data + i * ETH_GSTRING_LEN,
 870                                 mibs[i].name, ETH_GSTRING_LEN);
 871         } else if (stringset == ETH_SS_PHY_STATS) {
 872                 phydev = b53_get_phy_device(ds, port);
 873                 if (!phydev)
 874                         return;
 875
 876                 phy_ethtool_get_strings(phydev, data);
 877         }
 878 }
 879 EXPORT_SYMBOL(b53_get_strings);
 880
 881 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 882 {
 883         struct b53_device *dev = ds->priv;
 884         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 885         unsigned int mib_size = b53_get_mib_size(dev);
 886         const struct b53_mib_desc *s;
 887         unsigned int i;
 888         u64 val = 0;
 889
 890         if (is5365(dev) && port == 5)
 891                 port = 8;
 892
 893         mutex_lock(&dev->stats_mutex);
 894
 895         for (i = 0; i < mib_size; i++) {
 896                 s = &mibs[i];
 897
 898                 if (s->size == 8) {
 899                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 900                 } else {
 901                         u32 val32;
 902
 903                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 904                                    &val32);
 905                         val = val32;
 906                 }
 907                 data[i] = (u64)val;
 908         }
 909
 910         mutex_unlock(&dev->stats_mutex);
 911 }
 912 EXPORT_SYMBOL(b53_get_ethtool_stats);
 913
 914 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 915 {
 916         struct phy_device *phydev;
 917
 918         phydev = b53_get_phy_device(ds, port);
 919         if (!phydev)
 920                 return;
 921
 922         phy_ethtool_get_stats(phydev, NULL, data);
 923 }
 924 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 925
 926 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 927 {
 928         struct b53_device *dev = ds->priv;
 929         struct phy_device *phydev;
 930
 931         if (sset == ETH_SS_STATS) {
 932                 return b53_get_mib_size(dev);
 933         } else if (sset == ETH_SS_PHY_STATS) {
 934                 phydev = b53_get_phy_device(ds, port);
 935                 if (!phydev)
 936                         return 0;
 937
 938                 return phy_ethtool_get_sset_count(phydev);
 939         }
 940
 941         return 0;
 942 }
 943 EXPORT_SYMBOL(b53_get_sset_count);
 944
 945 static int b53_setup(struct dsa_switch *ds)
 946 {
 947         struct b53_device *dev = ds->priv;
 948         unsigned int port;
 949         int ret;
 950
 951         ret = b53_reset_switch(dev);
 952         if (ret) {
 953                 dev_err(ds->dev, "failed to reset switch\n");
 954                 return ret;
 955         }
 956
 957         b53_reset_mib(dev);
 958
 959         ret = b53_apply_config(dev);
 960         if (ret)
 961                 dev_err(ds->dev, "failed to apply configuration\n");
 962
 963         /* Configure IMP/CPU port, disable unused ports. Enabled
 964          * ports will be configured with .port_enable
 965          */
 966         for (port = 0; port < dev->num_ports; port++) {
 967                 if (dsa_is_cpu_port(ds, port))
 968                         b53_enable_cpu_port(dev, port);
 969                 else if (dsa_is_unused_port(ds, port))
 970                         b53_disable_port(ds, port, NULL);
 971         }
 972
 973         return ret;
 974 }
 975
 976 static void b53_adjust_link(struct dsa_switch *ds, int port,
 977                             struct phy_device *phydev)
 978 {
 979         struct b53_device *dev = ds->priv;
 980         struct ethtool_eee *p = &dev->ports[port].eee;
 981         u8 rgmii_ctrl = 0, reg = 0, off;
 982
 983         if (!phy_is_pseudo_fixed_link(phydev))
 984                 return;
 985
 986         /* Override the port settings */
 987         if (port == dev->cpu_port) {
 988                 off = B53_PORT_OVERRIDE_CTRL;
 989                 reg = PORT_OVERRIDE_EN;
 990         } else {
 991                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 992                 reg = GMII_PO_EN;
 993         }
 994
 995         /* Set the link UP */
 996         if (phydev->link)
 997                 reg |= PORT_OVERRIDE_LINK;
 998
 999         if (phydev->duplex == DUPLEX_FULL)
1000                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1001
1002         switch (phydev->speed) {
1003         case 2000:
1004                 reg |= PORT_OVERRIDE_SPEED_2000M;
1005                 /* fallthrough */
1006         case SPEED_1000:
1007                 reg |= PORT_OVERRIDE_SPEED_1000M;
1008                 break;
1009         case SPEED_100:
1010                 reg |= PORT_OVERRIDE_SPEED_100M;
1011                 break;
1012         case SPEED_10:
1013                 reg |= PORT_OVERRIDE_SPEED_10M;
1014                 break;
1015         default:
1016                 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
1017                 return;
1018         }
1019
1020         /* Enable flow control on BCM5301x's CPU port */
1021         if (is5301x(dev) && port == dev->cpu_port)
1022                 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
1023
1024         if (phydev->pause) {
1025                 if (phydev->asym_pause)
1026                         reg |= PORT_OVERRIDE_TX_FLOW;
1027                 reg |= PORT_OVERRIDE_RX_FLOW;
1028         }
1029
1030         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1031
1032         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1033                 if (port == 8)
1034                         off = B53_RGMII_CTRL_IMP;
1035                 else
1036                         off = B53_RGMII_CTRL_P(port);
1037
1038                 /* Configure the port RGMII clock delay by DLL disabled and
1039                  * tx_clk aligned timing (restoring to reset defaults)
1040                  */
1041                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1042                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1043                                 RGMII_CTRL_TIMING_SEL);
1044
1045                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1046                  * sure that we enable the port TX clock internal delay to
1047                  * account for this internal delay that is inserted, otherwise
1048                  * the switch won't be able to receive correctly.
1049                  *
1050                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1051                  * any delay neither on transmission nor reception, so the
1052                  * BCM53125 must also be configured accordingly to account for
1053                  * the lack of delay and introduce
1054                  *
1055                  * The BCM53125 switch has its RX clock and TX clock control
1056                  * swapped, hence the reason why we modify the TX clock path in
1057                  * the "RGMII" case
1058                  */
1059                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1060                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1061                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1062                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1063                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1064                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1065
1066                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1067                          phy_modes(phydev->interface));
1068         }
1069
1070         /* configure MII port if necessary */
1071         if (is5325(dev)) {
1072                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1073                           &reg);
1074
1075                 /* reverse mii needs to be enabled */
1076                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1077                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1078                                    reg | PORT_OVERRIDE_RV_MII_25);
1079                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1080                                   &reg);
1081
1082                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1083                                 dev_err(ds->dev,
1084                                         "Failed to enable reverse MII mode\n");
1085                                 return;
1086                         }
1087                 }
1088         } else if (is5301x(dev)) {
1089                 if (port != dev->cpu_port) {
1090                         u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1091                         u8 gmii_po;
1092
1093                         b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1094                         gmii_po |= GMII_PO_LINK |
1095                                    GMII_PO_RX_FLOW |
1096                                    GMII_PO_TX_FLOW |
1097                                    GMII_PO_EN |
1098                                    GMII_PO_SPEED_2000M;
1099                         b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1100                 }
1101         }
1102
1103         /* Re-negotiate EEE if it was enabled already */
1104         p->eee_enabled = b53_eee_init(ds, port, phydev);
1105 }
1106
1107 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1108 {
1109         struct b53_device *dev = ds->priv;
1110         struct net_device *bridge_dev;
1111         unsigned int i;
1112         u16 pvid, new_pvid;
1113
1114         /* Handle the case were multiple bridges span the same switch device
1115          * and one of them has a different setting than what is being requested
1116          * which would be breaking filtering semantics for any of the other
1117          * bridge devices.
1118          */
1119         b53_for_each_port(dev, i) {
1120                 bridge_dev = dsa_to_port(ds, i)->bridge_dev;
1121                 if (bridge_dev &&
1122                     bridge_dev != dsa_to_port(ds, port)->bridge_dev &&
1123                     br_vlan_enabled(bridge_dev) != vlan_filtering) {
1124                         netdev_err(bridge_dev,
1125                                    "VLAN filtering is global to the switch!\n");
1126                         return -EINVAL;
1127                 }
1128         }
1129
1130         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1131         new_pvid = pvid;
1132         if (dev->vlan_filtering_enabled && !vlan_filtering) {
1133                 /* Filtering is currently enabled, use the default PVID since
1134                  * the bridge does not expect tagging anymore
1135                  */
1136                 dev->ports[port].pvid = pvid;
1137                 new_pvid = b53_default_pvid(dev);
1138         } else if (!dev->vlan_filtering_enabled && vlan_filtering) {
1139                 /* Filtering is currently disabled, restore the previous PVID */
1140                 new_pvid = dev->ports[port].pvid;
1141         }
1142
1143         if (pvid != new_pvid)
1144                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1145                             new_pvid);
1146
1147         b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1148
1149         return 0;
1150 }
1151 EXPORT_SYMBOL(b53_vlan_filtering);
1152
1153 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1154                      const struct switchdev_obj_port_vlan *vlan)
1155 {
1156         struct b53_device *dev = ds->priv;
1157
1158         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1159                 return -EOPNOTSUPP;
1160
1161         if (vlan->vid_end >= dev->num_vlans)
1162                 return -ERANGE;
1163
1164         b53_enable_vlan(dev, true, dev->vlan_filtering_enabled);
1165
1166         return 0;
1167 }
1168 EXPORT_SYMBOL(b53_vlan_prepare);
1169
1170 void b53_vlan_add(struct dsa_switch *ds, int port,
1171                   const struct switchdev_obj_port_vlan *vlan)
1172 {
1173         struct b53_device *dev = ds->priv;
1174         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1175         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1176         struct b53_vlan *vl;
1177         u16 vid;
1178
1179         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1180                 vl = &dev->vlans[vid];
1181
1182                 b53_get_vlan_entry(dev, vid, vl);
1183
1184                 if (vid == 0 && vid == b53_default_pvid(dev))
1185                         untagged = true;
1186
1187                 vl->members |= BIT(port);
1188                 if (untagged && !dsa_is_cpu_port(ds, port))
1189                         vl->untag |= BIT(port);
1190                 else
1191                         vl->untag &= ~BIT(port);
1192
1193                 b53_set_vlan_entry(dev, vid, vl);
1194                 b53_fast_age_vlan(dev, vid);
1195         }
1196
1197         if (pvid && !dsa_is_cpu_port(ds, port)) {
1198                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1199                             vlan->vid_end);
1200                 b53_fast_age_vlan(dev, vid);
1201         }
1202 }
1203 EXPORT_SYMBOL(b53_vlan_add);
1204
1205 int b53_vlan_del(struct dsa_switch *ds, int port,
1206                  const struct switchdev_obj_port_vlan *vlan)
1207 {
1208         struct b53_device *dev = ds->priv;
1209         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1210         struct b53_vlan *vl;
1211         u16 vid;
1212         u16 pvid;
1213
1214         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1215
1216         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1217                 vl = &dev->vlans[vid];
1218
1219                 b53_get_vlan_entry(dev, vid, vl);
1220
1221                 vl->members &= ~BIT(port);
1222
1223                 if (pvid == vid)
1224                         pvid = b53_default_pvid(dev);
1225
1226                 if (untagged && !dsa_is_cpu_port(ds, port))
1227                         vl->untag &= ~(BIT(port));
1228
1229                 b53_set_vlan_entry(dev, vid, vl);
1230                 b53_fast_age_vlan(dev, vid);
1231         }
1232
1233         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1234         b53_fast_age_vlan(dev, pvid);
1235
1236         return 0;
1237 }
1238 EXPORT_SYMBOL(b53_vlan_del);
1239
1240 /* Address Resolution Logic routines */
1241 static int b53_arl_op_wait(struct b53_device *dev)
1242 {
1243         unsigned int timeout = 10;
1244         u8 reg;
1245
1246         do {
1247                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1248                 if (!(reg & ARLTBL_START_DONE))
1249                         return 0;
1250
1251                 usleep_range(1000, 2000);
1252         } while (timeout--);
1253
1254         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1255
1256         return -ETIMEDOUT;
1257 }
1258
1259 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1260 {
1261         u8 reg;
1262
1263         if (op > ARLTBL_RW)
1264                 return -EINVAL;
1265
1266         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1267         reg |= ARLTBL_START_DONE;
1268         if (op)
1269                 reg |= ARLTBL_RW;
1270         else
1271                 reg &= ~ARLTBL_RW;
1272         if (dev->vlan_enabled)
1273                 reg &= ~ARLTBL_IVL_SVL_SELECT;
1274         else
1275                 reg |= ARLTBL_IVL_SVL_SELECT;
1276         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1277
1278         return b53_arl_op_wait(dev);
1279 }
1280
1281 static int b53_arl_read(struct b53_device *dev, u64 mac,
1282                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1283                         bool is_valid)
1284 {
1285         DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1286         unsigned int i;
1287         int ret;
1288
1289         ret = b53_arl_op_wait(dev);
1290         if (ret)
1291                 return ret;
1292
1293         bitmap_zero(free_bins, dev->num_arl_entries);
1294
1295         /* Read the bins */
1296         for (i = 0; i < dev->num_arl_entries; i++) {
1297                 u64 mac_vid;
1298                 u32 fwd_entry;
1299
1300                 b53_read64(dev, B53_ARLIO_PAGE,
1301                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1302                 b53_read32(dev, B53_ARLIO_PAGE,
1303                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1304                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1305
1306                 if (!(fwd_entry & ARLTBL_VALID)) {
1307                         set_bit(i, free_bins);
1308                         continue;
1309                 }
1310                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1311                         continue;
1312                 if (dev->vlan_enabled &&
1313                     ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1314                         continue;
1315                 *idx = i;
1316                 return 0;
1317         }
1318
1319         if (bitmap_weight(free_bins, dev->num_arl_entries) == 0)
1320                 return -ENOSPC;
1321
1322         *idx = find_first_bit(free_bins, dev->num_arl_entries);
1323
1324         return -ENOENT;
1325 }
1326
1327 static int b53_arl_op(struct b53_device *dev, int op, int port,
1328                       const unsigned char *addr, u16 vid, bool is_valid)
1329 {
1330         struct b53_arl_entry ent;
1331         u32 fwd_entry;
1332         u64 mac, mac_vid = 0;
1333         u8 idx = 0;
1334         int ret;
1335
1336         /* Convert the array into a 64-bit MAC */
1337         mac = ether_addr_to_u64(addr);
1338
1339         /* Perform a read for the given MAC and VID */
1340         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1341         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1342
1343         /* Issue a read operation for this MAC */
1344         ret = b53_arl_rw_op(dev, 1);
1345         if (ret)
1346                 return ret;
1347
1348         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1349         /* If this is a read, just finish now */
1350         if (op)
1351                 return ret;
1352
1353         switch (ret) {
1354         case -ETIMEDOUT:
1355                 return ret;
1356         case -ENOSPC:
1357                 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1358                         addr, vid);
1359                 return is_valid ? ret : 0;
1360         case -ENOENT:
1361                 /* We could not find a matching MAC, so reset to a new entry */
1362                 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1363                         addr, vid, idx);
1364                 fwd_entry = 0;
1365                 break;
1366         default:
1367                 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1368                         addr, vid, idx);
1369                 break;
1370         }
1371
1372         memset(&ent, 0, sizeof(ent));
1373         ent.port = port;
1374         ent.is_valid = is_valid;
1375         ent.vid = vid;
1376         ent.is_static = true;
1377         memcpy(ent.mac, addr, ETH_ALEN);
1378         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1379
1380         b53_write64(dev, B53_ARLIO_PAGE,
1381                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1382         b53_write32(dev, B53_ARLIO_PAGE,
1383                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1384
1385         return b53_arl_rw_op(dev, 0);
1386 }
1387
1388 int b53_fdb_add(struct dsa_switch *ds, int port,
1389                 const unsigned char *addr, u16 vid)
1390 {
1391         struct b53_device *priv = ds->priv;
1392
1393         /* 5325 and 5365 require some more massaging, but could
1394          * be supported eventually
1395          */
1396         if (is5325(priv) || is5365(priv))
1397                 return -EOPNOTSUPP;
1398
1399         return b53_arl_op(priv, 0, port, addr, vid, true);
1400 }
1401 EXPORT_SYMBOL(b53_fdb_add);
1402
1403 int b53_fdb_del(struct dsa_switch *ds, int port,
1404                 const unsigned char *addr, u16 vid)
1405 {
1406         struct b53_device *priv = ds->priv;
1407
1408         return b53_arl_op(priv, 0, port, addr, vid, false);
1409 }
1410 EXPORT_SYMBOL(b53_fdb_del);
1411
1412 static int b53_arl_search_wait(struct b53_device *dev)
1413 {
1414         unsigned int timeout = 1000;
1415         u8 reg;
1416
1417         do {
1418                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1419                 if (!(reg & ARL_SRCH_STDN))
1420                         return 0;
1421
1422                 if (reg & ARL_SRCH_VLID)
1423                         return 0;
1424
1425                 usleep_range(1000, 2000);
1426         } while (timeout--);
1427
1428         return -ETIMEDOUT;
1429 }
1430
1431 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1432                               struct b53_arl_entry *ent)
1433 {
1434         u64 mac_vid;
1435         u32 fwd_entry;
1436
1437         b53_read64(dev, B53_ARLIO_PAGE,
1438                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1439         b53_read32(dev, B53_ARLIO_PAGE,
1440                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1441         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1442 }
1443
1444 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1445                         dsa_fdb_dump_cb_t *cb, void *data)
1446 {
1447         if (!ent->is_valid)
1448                 return 0;
1449
1450         if (port != ent->port)
1451                 return 0;
1452
1453         return cb(ent->mac, ent->vid, ent->is_static, data);
1454 }
1455
1456 int b53_fdb_dump(struct dsa_switch *ds, int port,
1457                  dsa_fdb_dump_cb_t *cb, void *data)
1458 {
1459         struct b53_device *priv = ds->priv;
1460         struct b53_arl_entry results[2];
1461         unsigned int count = 0;
1462         int ret;
1463         u8 reg;
1464
1465         /* Start search operation */
1466         reg = ARL_SRCH_STDN;
1467         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1468
1469         do {
1470                 ret = b53_arl_search_wait(priv);
1471                 if (ret)
1472                         return ret;
1473
1474                 b53_arl_search_rd(priv, 0, &results[0]);
1475                 ret = b53_fdb_copy(port, &results[0], cb, data);
1476                 if (ret)
1477                         return ret;
1478
1479                 if (priv->num_arl_entries > 2) {
1480                         b53_arl_search_rd(priv, 1, &results[1]);
1481                         ret = b53_fdb_copy(port, &results[1], cb, data);
1482                         if (ret)
1483                                 return ret;
1484
1485                         if (!results[0].is_valid && !results[1].is_valid)
1486                                 break;
1487                 }
1488
1489         } while (count++ < 1024);
1490
1491         return 0;
1492 }
1493 EXPORT_SYMBOL(b53_fdb_dump);
1494
1495 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1496 {
1497         struct b53_device *dev = ds->priv;
1498         s8 cpu_port = ds->ports[port].cpu_dp->index;
1499         u16 pvlan, reg;
1500         unsigned int i;
1501
1502         /* Make this port leave the all VLANs join since we will have proper
1503          * VLAN entries from now on
1504          */
1505         if (is58xx(dev)) {
1506                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1507                 reg &= ~BIT(port);
1508                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1509                         reg &= ~BIT(cpu_port);
1510                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1511         }
1512
1513         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1514
1515         b53_for_each_port(dev, i) {
1516                 if (dsa_to_port(ds, i)->bridge_dev != br)
1517                         continue;
1518
1519                 /* Add this local port to the remote port VLAN control
1520                  * membership and update the remote port bitmask
1521                  */
1522                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1523                 reg |= BIT(port);
1524                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1525                 dev->ports[i].vlan_ctl_mask = reg;
1526
1527                 pvlan |= BIT(i);
1528         }
1529
1530         /* Configure the local port VLAN control membership to include
1531          * remote ports and update the local port bitmask
1532          */
1533         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1534         dev->ports[port].vlan_ctl_mask = pvlan;
1535
1536         b53_port_set_learning(dev, port, true);
1537
1538         return 0;
1539 }
1540 EXPORT_SYMBOL(b53_br_join);
1541
1542 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1543 {
1544         struct b53_device *dev = ds->priv;
1545         struct b53_vlan *vl = &dev->vlans[0];
1546         s8 cpu_port = ds->ports[port].cpu_dp->index;
1547         unsigned int i;
1548         u16 pvlan, reg, pvid;
1549
1550         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1551
1552         b53_for_each_port(dev, i) {
1553                 /* Don't touch the remaining ports */
1554                 if (dsa_to_port(ds, i)->bridge_dev != br)
1555                         continue;
1556
1557                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1558                 reg &= ~BIT(port);
1559                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1560                 dev->ports[port].vlan_ctl_mask = reg;
1561
1562                 /* Prevent self removal to preserve isolation */
1563                 if (port != i)
1564                         pvlan &= ~BIT(i);
1565         }
1566
1567         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1568         dev->ports[port].vlan_ctl_mask = pvlan;
1569
1570         pvid = b53_default_pvid(dev);
1571
1572         /* Make this port join all VLANs without VLAN entries */
1573         if (is58xx(dev)) {
1574                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1575                 reg |= BIT(port);
1576                 if (!(reg & BIT(cpu_port)))
1577                         reg |= BIT(cpu_port);
1578                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1579         } else {
1580                 b53_get_vlan_entry(dev, pvid, vl);
1581                 vl->members |= BIT(port) | BIT(cpu_port);
1582                 vl->untag |= BIT(port) | BIT(cpu_port);
1583                 b53_set_vlan_entry(dev, pvid, vl);
1584         }
1585         b53_port_set_learning(dev, port, false);
1586 }
1587 EXPORT_SYMBOL(b53_br_leave);
1588
1589 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1590 {
1591         struct b53_device *dev = ds->priv;
1592         u8 hw_state;
1593         u8 reg;
1594
1595         switch (state) {
1596         case BR_STATE_DISABLED:
1597                 hw_state = PORT_CTRL_DIS_STATE;
1598                 break;
1599         case BR_STATE_LISTENING:
1600                 hw_state = PORT_CTRL_LISTEN_STATE;
1601                 break;
1602         case BR_STATE_LEARNING:
1603                 hw_state = PORT_CTRL_LEARN_STATE;
1604                 break;
1605         case BR_STATE_FORWARDING:
1606                 hw_state = PORT_CTRL_FWD_STATE;
1607                 break;
1608         case BR_STATE_BLOCKING:
1609                 hw_state = PORT_CTRL_BLOCK_STATE;
1610                 break;
1611         default:
1612                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1613                 return;
1614         }
1615
1616         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1617         reg &= ~PORT_CTRL_STP_STATE_MASK;
1618         reg |= hw_state;
1619         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1620 }
1621 EXPORT_SYMBOL(b53_br_set_stp_state);
1622
1623 void b53_br_fast_age(struct dsa_switch *ds, int port)
1624 {
1625         struct b53_device *dev = ds->priv;
1626
1627         if (b53_fast_age_port(dev, port))
1628                 dev_err(ds->dev, "fast ageing failed\n");
1629 }
1630 EXPORT_SYMBOL(b53_br_fast_age);
1631
1632 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1633 {
1634         /* Broadcom switches will accept enabling Broadcom tags on the
1635          * following ports: 5, 7 and 8, any other port is not supported
1636          */
1637         switch (port) {
1638         case B53_CPU_PORT_25:
1639         case 7:
1640         case B53_CPU_PORT:
1641                 return true;
1642         }
1643
1644         return false;
1645 }
1646
1647 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1648 {
1649         bool ret = b53_possible_cpu_port(ds, port);
1650
1651         if (!ret)
1652                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1653                          port);
1654         return ret;
1655 }
1656
1657 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1658 {
1659         struct b53_device *dev = ds->priv;
1660
1661         /* Older models (5325, 5365) support a different tag format that we do
1662          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1663          * mode to be turned on which means we need to specifically manage ARL
1664          * misses on multicast addresses (TBD).
1665          */
1666         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1667             !b53_can_enable_brcm_tags(ds, port))
1668                 return DSA_TAG_PROTO_NONE;
1669
1670         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1671          * which requires us to use the prepended Broadcom tag type
1672          */
1673         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1674                 return DSA_TAG_PROTO_BRCM_PREPEND;
1675
1676         return DSA_TAG_PROTO_BRCM;
1677 }
1678 EXPORT_SYMBOL(b53_get_tag_protocol);
1679
1680 int b53_mirror_add(struct dsa_switch *ds, int port,
1681                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1682 {
1683         struct b53_device *dev = ds->priv;
1684         u16 reg, loc;
1685
1686         if (ingress)
1687                 loc = B53_IG_MIR_CTL;
1688         else
1689                 loc = B53_EG_MIR_CTL;
1690
1691         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1692         reg |= BIT(port);
1693         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1694
1695         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1696         reg &= ~CAP_PORT_MASK;
1697         reg |= mirror->to_local_port;
1698         reg |= MIRROR_EN;
1699         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1700
1701         return 0;
1702 }
1703 EXPORT_SYMBOL(b53_mirror_add);
1704
1705 void b53_mirror_del(struct dsa_switch *ds, int port,
1706                     struct dsa_mall_mirror_tc_entry *mirror)
1707 {
1708         struct b53_device *dev = ds->priv;
1709         bool loc_disable = false, other_loc_disable = false;
1710         u16 reg, loc;
1711
1712         if (mirror->ingress)
1713                 loc = B53_IG_MIR_CTL;
1714         else
1715                 loc = B53_EG_MIR_CTL;
1716
1717         /* Update the desired ingress/egress register */
1718         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1719         reg &= ~BIT(port);
1720         if (!(reg & MIRROR_MASK))
1721                 loc_disable = true;
1722         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1723
1724         /* Now look at the other one to know if we can disable mirroring
1725          * entirely
1726          */
1727         if (mirror->ingress)
1728                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1729         else
1730                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1731         if (!(reg & MIRROR_MASK))
1732                 other_loc_disable = true;
1733
1734         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1735         /* Both no longer have ports, let's disable mirroring */
1736         if (loc_disable && other_loc_disable) {
1737                 reg &= ~MIRROR_EN;
1738                 reg &= ~mirror->to_local_port;
1739         }
1740         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1741 }
1742 EXPORT_SYMBOL(b53_mirror_del);
1743
1744 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1745 {
1746         struct b53_device *dev = ds->priv;
1747         u16 reg;
1748
1749         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1750         if (enable)
1751                 reg |= BIT(port);
1752         else
1753                 reg &= ~BIT(port);
1754         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1755 }
1756 EXPORT_SYMBOL(b53_eee_enable_set);
1757
1758
1759 /* Returns 0 if EEE was not enabled, or 1 otherwise
1760  */
1761 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1762 {
1763         int ret;
1764
1765         ret = phy_init_eee(phy, 0);
1766         if (ret)
1767                 return 0;
1768
1769         b53_eee_enable_set(ds, port, true);
1770
1771         return 1;
1772 }
1773 EXPORT_SYMBOL(b53_eee_init);
1774
1775 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1776 {
1777         struct b53_device *dev = ds->priv;
1778         struct ethtool_eee *p = &dev->ports[port].eee;
1779         u16 reg;
1780
1781         if (is5325(dev) || is5365(dev))
1782                 return -EOPNOTSUPP;
1783
1784         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1785         e->eee_enabled = p->eee_enabled;
1786         e->eee_active = !!(reg & BIT(port));
1787
1788         return 0;
1789 }
1790 EXPORT_SYMBOL(b53_get_mac_eee);
1791
1792 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1793 {
1794         struct b53_device *dev = ds->priv;
1795         struct ethtool_eee *p = &dev->ports[port].eee;
1796
1797         if (is5325(dev) || is5365(dev))
1798                 return -EOPNOTSUPP;
1799
1800         p->eee_enabled = e->eee_enabled;
1801         b53_eee_enable_set(ds, port, e->eee_enabled);
1802
1803         return 0;
1804 }
1805 EXPORT_SYMBOL(b53_set_mac_eee);
1806
1807 static const struct dsa_switch_ops b53_switch_ops = {
1808         .get_tag_protocol       = b53_get_tag_protocol,
1809         .setup                  = b53_setup,
1810         .get_strings            = b53_get_strings,
1811         .get_ethtool_stats      = b53_get_ethtool_stats,
1812         .get_sset_count         = b53_get_sset_count,
1813         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1814         .phy_read               = b53_phy_read16,
1815         .phy_write              = b53_phy_write16,
1816         .adjust_link            = b53_adjust_link,
1817         .port_enable            = b53_enable_port,
1818         .port_disable           = b53_disable_port,
1819         .get_mac_eee            = b53_get_mac_eee,
1820         .set_mac_eee            = b53_set_mac_eee,
1821         .port_bridge_join       = b53_br_join,
1822         .port_bridge_leave      = b53_br_leave,
1823         .port_stp_state_set     = b53_br_set_stp_state,
1824         .port_fast_age          = b53_br_fast_age,
1825         .port_vlan_filtering    = b53_vlan_filtering,
1826         .port_vlan_prepare      = b53_vlan_prepare,
1827         .port_vlan_add          = b53_vlan_add,
1828         .port_vlan_del          = b53_vlan_del,
1829         .port_fdb_dump          = b53_fdb_dump,
1830         .port_fdb_add           = b53_fdb_add,
1831         .port_fdb_del           = b53_fdb_del,
1832         .port_mirror_add        = b53_mirror_add,
1833         .port_mirror_del        = b53_mirror_del,
1834 };
1835
1836 struct b53_chip_data {
1837         u32 chip_id;
1838         const char *dev_name;
1839         u16 vlans;
1840         u16 enabled_ports;
1841         u8 cpu_port;
1842         u8 vta_regs[3];
1843         u8 arl_entries;
1844         u8 duplex_reg;
1845         u8 jumbo_pm_reg;
1846         u8 jumbo_size_reg;
1847 };
1848
1849 #define B53_VTA_REGS    \
1850         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1851 #define B53_VTA_REGS_9798 \
1852         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1853 #define B53_VTA_REGS_63XX \
1854         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1855
1856 static const struct b53_chip_data b53_switch_chips[] = {
1857         {
1858                 .chip_id = BCM5325_DEVICE_ID,
1859                 .dev_name = "BCM5325",
1860                 .vlans = 16,
1861                 .enabled_ports = 0x1f,
1862                 .arl_entries = 2,
1863                 .cpu_port = B53_CPU_PORT_25,
1864                 .duplex_reg = B53_DUPLEX_STAT_FE,
1865         },
1866         {
1867                 .chip_id = BCM5365_DEVICE_ID,
1868                 .dev_name = "BCM5365",
1869                 .vlans = 256,
1870                 .enabled_ports = 0x1f,
1871                 .arl_entries = 2,
1872                 .cpu_port = B53_CPU_PORT_25,
1873                 .duplex_reg = B53_DUPLEX_STAT_FE,
1874         },
1875         {
1876                 .chip_id = BCM5389_DEVICE_ID,
1877                 .dev_name = "BCM5389",
1878                 .vlans = 4096,
1879                 .enabled_ports = 0x1f,
1880                 .arl_entries = 4,
1881                 .cpu_port = B53_CPU_PORT,
1882                 .vta_regs = B53_VTA_REGS,
1883                 .duplex_reg = B53_DUPLEX_STAT_GE,
1884                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1885                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1886         },
1887         {
1888                 .chip_id = BCM5395_DEVICE_ID,
1889                 .dev_name = "BCM5395",
1890                 .vlans = 4096,
1891                 .enabled_ports = 0x1f,
1892                 .arl_entries = 4,
1893                 .cpu_port = B53_CPU_PORT,
1894                 .vta_regs = B53_VTA_REGS,
1895                 .duplex_reg = B53_DUPLEX_STAT_GE,
1896                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1897                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1898         },
1899         {
1900                 .chip_id = BCM5397_DEVICE_ID,
1901                 .dev_name = "BCM5397",
1902                 .vlans = 4096,
1903                 .enabled_ports = 0x1f,
1904                 .arl_entries = 4,
1905                 .cpu_port = B53_CPU_PORT,
1906                 .vta_regs = B53_VTA_REGS_9798,
1907                 .duplex_reg = B53_DUPLEX_STAT_GE,
1908                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1909                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1910         },
1911         {
1912                 .chip_id = BCM5398_DEVICE_ID,
1913                 .dev_name = "BCM5398",
1914                 .vlans = 4096,
1915                 .enabled_ports = 0x7f,
1916                 .arl_entries = 4,
1917                 .cpu_port = B53_CPU_PORT,
1918                 .vta_regs = B53_VTA_REGS_9798,
1919                 .duplex_reg = B53_DUPLEX_STAT_GE,
1920                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1921                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1922         },
1923         {
1924                 .chip_id = BCM53115_DEVICE_ID,
1925                 .dev_name = "BCM53115",
1926                 .vlans = 4096,
1927                 .enabled_ports = 0x1f,
1928                 .arl_entries = 4,
1929                 .vta_regs = B53_VTA_REGS,
1930                 .cpu_port = B53_CPU_PORT,
1931                 .duplex_reg = B53_DUPLEX_STAT_GE,
1932                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1933                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1934         },
1935         {
1936                 .chip_id = BCM53125_DEVICE_ID,
1937                 .dev_name = "BCM53125",
1938                 .vlans = 4096,
1939                 .enabled_ports = 0xff,
1940                 .arl_entries = 4,
1941                 .cpu_port = B53_CPU_PORT,
1942                 .vta_regs = B53_VTA_REGS,
1943                 .duplex_reg = B53_DUPLEX_STAT_GE,
1944                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1945                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1946         },
1947         {
1948                 .chip_id = BCM53128_DEVICE_ID,
1949                 .dev_name = "BCM53128",
1950                 .vlans = 4096,
1951                 .enabled_ports = 0x1ff,
1952                 .arl_entries = 4,
1953                 .cpu_port = B53_CPU_PORT,
1954                 .vta_regs = B53_VTA_REGS,
1955                 .duplex_reg = B53_DUPLEX_STAT_GE,
1956                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1957                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1958         },
1959         {
1960                 .chip_id = BCM63XX_DEVICE_ID,
1961                 .dev_name = "BCM63xx",
1962                 .vlans = 4096,
1963                 .enabled_ports = 0, /* pdata must provide them */
1964                 .arl_entries = 4,
1965                 .cpu_port = B53_CPU_PORT,
1966                 .vta_regs = B53_VTA_REGS_63XX,
1967                 .duplex_reg = B53_DUPLEX_STAT_63XX,
1968                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1969                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1970         },
1971         {
1972                 .chip_id = BCM53010_DEVICE_ID,
1973                 .dev_name = "BCM53010",
1974                 .vlans = 4096,
1975                 .enabled_ports = 0x1f,
1976                 .arl_entries = 4,
1977                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1978                 .vta_regs = B53_VTA_REGS,
1979                 .duplex_reg = B53_DUPLEX_STAT_GE,
1980                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1981                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1982         },
1983         {
1984                 .chip_id = BCM53011_DEVICE_ID,
1985                 .dev_name = "BCM53011",
1986                 .vlans = 4096,
1987                 .enabled_ports = 0x1bf,
1988                 .arl_entries = 4,
1989                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1990                 .vta_regs = B53_VTA_REGS,
1991                 .duplex_reg = B53_DUPLEX_STAT_GE,
1992                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1993                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1994         },
1995         {
1996                 .chip_id = BCM53012_DEVICE_ID,
1997                 .dev_name = "BCM53012",
1998                 .vlans = 4096,
1999                 .enabled_ports = 0x1bf,
2000                 .arl_entries = 4,
2001                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2002                 .vta_regs = B53_VTA_REGS,
2003                 .duplex_reg = B53_DUPLEX_STAT_GE,
2004                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2005                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2006         },
2007         {
2008                 .chip_id = BCM53018_DEVICE_ID,
2009                 .dev_name = "BCM53018",
2010                 .vlans = 4096,
2011                 .enabled_ports = 0x1f,
2012                 .arl_entries = 4,
2013                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2014                 .vta_regs = B53_VTA_REGS,
2015                 .duplex_reg = B53_DUPLEX_STAT_GE,
2016                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2017                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2018         },
2019         {
2020                 .chip_id = BCM53019_DEVICE_ID,
2021                 .dev_name = "BCM53019",
2022                 .vlans = 4096,
2023                 .enabled_ports = 0x1f,
2024                 .arl_entries = 4,
2025                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2026                 .vta_regs = B53_VTA_REGS,
2027                 .duplex_reg = B53_DUPLEX_STAT_GE,
2028                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2029                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2030         },
2031         {
2032                 .chip_id = BCM58XX_DEVICE_ID,
2033                 .dev_name = "BCM585xx/586xx/88312",
2034                 .vlans  = 4096,
2035                 .enabled_ports = 0x1ff,
2036                 .arl_entries = 4,
2037                 .cpu_port = B53_CPU_PORT,
2038                 .vta_regs = B53_VTA_REGS,
2039                 .duplex_reg = B53_DUPLEX_STAT_GE,
2040                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2041                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2042         },
2043         {
2044                 .chip_id = BCM583XX_DEVICE_ID,
2045                 .dev_name = "BCM583xx/11360",
2046                 .vlans = 4096,
2047                 .enabled_ports = 0x103,
2048                 .arl_entries = 4,
2049                 .cpu_port = B53_CPU_PORT,
2050                 .vta_regs = B53_VTA_REGS,
2051                 .duplex_reg = B53_DUPLEX_STAT_GE,
2052                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2053                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2054         },
2055         {
2056                 .chip_id = BCM7445_DEVICE_ID,
2057                 .dev_name = "BCM7445",
2058                 .vlans  = 4096,
2059                 .enabled_ports = 0x1ff,
2060                 .arl_entries = 4,
2061                 .cpu_port = B53_CPU_PORT,
2062                 .vta_regs = B53_VTA_REGS,
2063                 .duplex_reg = B53_DUPLEX_STAT_GE,
2064                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2065                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2066         },
2067         {
2068                 .chip_id = BCM7278_DEVICE_ID,
2069                 .dev_name = "BCM7278",
2070                 .vlans = 4096,
2071                 .enabled_ports = 0x1ff,
2072                 .arl_entries= 4,
2073                 .cpu_port = B53_CPU_PORT,
2074                 .vta_regs = B53_VTA_REGS,
2075                 .duplex_reg = B53_DUPLEX_STAT_GE,
2076                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2077                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2078         },
2079 };
2080
2081 static int b53_switch_init(struct b53_device *dev)
2082 {
2083         unsigned int i;
2084         int ret;
2085
2086         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2087                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2088
2089                 if (chip->chip_id == dev->chip_id) {
2090                         if (!dev->enabled_ports)
2091                                 dev->enabled_ports = chip->enabled_ports;
2092                         dev->name = chip->dev_name;
2093                         dev->duplex_reg = chip->duplex_reg;
2094                         dev->vta_regs[0] = chip->vta_regs[0];
2095                         dev->vta_regs[1] = chip->vta_regs[1];
2096                         dev->vta_regs[2] = chip->vta_regs[2];
2097                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2098                         dev->cpu_port = chip->cpu_port;
2099                         dev->num_vlans = chip->vlans;
2100                         dev->num_arl_entries = chip->arl_entries;
2101                         break;
2102                 }
2103         }
2104
2105         /* check which BCM5325x version we have */
2106         if (is5325(dev)) {
2107                 u8 vc4;
2108
2109                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2110
2111                 /* check reserved bits */
2112                 switch (vc4 & 3) {
2113                 case 1:
2114                         /* BCM5325E */
2115                         break;
2116                 case 3:
2117                         /* BCM5325F - do not use port 4 */
2118                         dev->enabled_ports &= ~BIT(4);
2119                         break;
2120                 default:
2121 /* On the BCM47XX SoCs this is the supported internal switch.*/
2122 #ifndef CONFIG_BCM47XX
2123                         /* BCM5325M */
2124                         return -EINVAL;
2125 #else
2126                         break;
2127 #endif
2128                 }
2129         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2130                 u64 strap_value;
2131
2132                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2133                 /* use second IMP port if GMII is enabled */
2134                 if (strap_value & SV_GMII_CTRL_115)
2135                         dev->cpu_port = 5;
2136         }
2137
2138         dev->enabled_ports |= BIT(dev->cpu_port);
2139         dev->num_ports = fls(dev->enabled_ports);
2140
2141         /* Include non standard CPU port built-in PHYs to be probed */
2142         if (is539x(dev) || is531x5(dev)) {
2143                 for (i = 0; i < dev->num_ports; i++) {
2144                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2145                             !b53_possible_cpu_port(dev->ds, i))
2146                                 dev->ds->phys_mii_mask |= BIT(i);
2147                 }
2148         }
2149
2150         dev->ports = devm_kcalloc(dev->dev,
2151                                   dev->num_ports, sizeof(struct b53_port),
2152                                   GFP_KERNEL);
2153         if (!dev->ports)
2154                 return -ENOMEM;
2155
2156         dev->vlans = devm_kcalloc(dev->dev,
2157                                   dev->num_vlans, sizeof(struct b53_vlan),
2158                                   GFP_KERNEL);
2159         if (!dev->vlans)
2160                 return -ENOMEM;
2161
2162         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2163         if (dev->reset_gpio >= 0) {
2164                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2165                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2166                 if (ret)
2167                         return ret;
2168         }
2169
2170         return 0;
2171 }
2172
2173 struct b53_device *b53_switch_alloc(struct device *base,
2174                                     const struct b53_io_ops *ops,
2175                                     void *priv)
2176 {
2177         struct dsa_switch *ds;
2178         struct b53_device *dev;
2179
2180         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2181         if (!ds)
2182                 return NULL;
2183
2184         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2185         if (!dev)
2186                 return NULL;
2187
2188         ds->priv = dev;
2189         dev->dev = base;
2190
2191         dev->ds = ds;
2192         dev->priv = priv;
2193         dev->ops = ops;
2194         ds->ops = &b53_switch_ops;
2195         mutex_init(&dev->reg_mutex);
2196         mutex_init(&dev->stats_mutex);
2197
2198         return dev;
2199 }
2200 EXPORT_SYMBOL(b53_switch_alloc);
2201
2202 int b53_switch_detect(struct b53_device *dev)
2203 {
2204         u32 id32;
2205         u16 tmp;
2206         u8 id8;
2207         int ret;
2208
2209         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2210         if (ret)
2211                 return ret;
2212
2213         switch (id8) {
2214         case 0:
2215                 /* BCM5325 and BCM5365 do not have this register so reads
2216                  * return 0. But the read operation did succeed, so assume this
2217                  * is one of them.
2218                  *
2219                  * Next check if we can write to the 5325's VTA register; for
2220                  * 5365 it is read only.
2221                  */
2222                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2223                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2224
2225                 if (tmp == 0xf)
2226                         dev->chip_id = BCM5325_DEVICE_ID;
2227                 else
2228                         dev->chip_id = BCM5365_DEVICE_ID;
2229                 break;
2230         case BCM5389_DEVICE_ID:
2231         case BCM5395_DEVICE_ID:
2232         case BCM5397_DEVICE_ID:
2233         case BCM5398_DEVICE_ID:
2234                 dev->chip_id = id8;
2235                 break;
2236         default:
2237                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2238                 if (ret)
2239                         return ret;
2240
2241                 switch (id32) {
2242                 case BCM53115_DEVICE_ID:
2243                 case BCM53125_DEVICE_ID:
2244                 case BCM53128_DEVICE_ID:
2245                 case BCM53010_DEVICE_ID:
2246                 case BCM53011_DEVICE_ID:
2247                 case BCM53012_DEVICE_ID:
2248                 case BCM53018_DEVICE_ID:
2249                 case BCM53019_DEVICE_ID:
2250                         dev->chip_id = id32;
2251                         break;
2252                 default:
2253                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2254                                id8, id32);
2255                         return -ENODEV;
2256                 }
2257         }
2258
2259         if (dev->chip_id == BCM5325_DEVICE_ID)
2260                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2261                                  &dev->core_rev);
2262         else
2263                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2264                                  &dev->core_rev);
2265 }
2266 EXPORT_SYMBOL(b53_switch_detect);
2267
2268 int b53_switch_register(struct b53_device *dev)
2269 {
2270         int ret;
2271
2272         if (dev->pdata) {
2273                 dev->chip_id = dev->pdata->chip_id;
2274                 dev->enabled_ports = dev->pdata->enabled_ports;
2275         }
2276
2277         if (!dev->chip_id && b53_switch_detect(dev))
2278                 return -EINVAL;
2279
2280         ret = b53_switch_init(dev);
2281         if (ret)
2282                 return ret;
2283
2284         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2285
2286         return dsa_register_switch(dev->ds);
2287 }
2288 EXPORT_SYMBOL(b53_switch_register);
2289
2290 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2291 MODULE_DESCRIPTION("B53 switch library");
2292 MODULE_LICENSE("Dual BSD/GPL");