1 /* Xilinx CAN device driver
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
5 * Copyright (C) 2017 Sandvik Mining and Construction Oy
8 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/clk.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/netdevice.h>
29 #include <linux/of_device.h>
30 #include <linux/platform_device.h>
31 #include <linux/skbuff.h>
32 #include <linux/spinlock.h>
33 #include <linux/string.h>
34 #include <linux/types.h>
35 #include <linux/can/dev.h>
36 #include <linux/can/error.h>
37 #include <linux/can/led.h>
39 #define DRIVER_NAME "xilinx_can"
41 /* CAN registers set */
43 XCAN_SRR_OFFSET = 0x00, /* Software reset */
44 XCAN_MSR_OFFSET = 0x04, /* Mode select */
45 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
46 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
47 XCAN_ECR_OFFSET = 0x10, /* Error counter */
48 XCAN_ESR_OFFSET = 0x14, /* Error status */
49 XCAN_SR_OFFSET = 0x18, /* Status */
50 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
51 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
52 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
53 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
54 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
55 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
56 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
57 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
58 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
59 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
60 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
63 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
64 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
65 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
66 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
67 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
68 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
69 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
70 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
71 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
72 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
73 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
74 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
75 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
76 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
77 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
78 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
79 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
80 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
81 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
82 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
83 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
84 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
85 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
86 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
87 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
88 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
89 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
90 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
91 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
92 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
93 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
94 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
95 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
96 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
97 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
98 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
99 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
100 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
101 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
103 #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
104 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
105 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
106 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK)
108 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
109 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
110 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
111 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
112 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
113 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
114 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
116 /* CAN frame length constants */
117 #define XCAN_FRAME_MAX_DATA_LEN 8
118 #define XCAN_TIMEOUT (1 * HZ)
121 * struct xcan_priv - This definition define CAN driver instance
122 * @can: CAN private data structure.
123 * @tx_lock: Lock for synchronizing TX interrupt handling
124 * @tx_head: Tx CAN packets ready to send on the queue
125 * @tx_tail: Tx CAN packets successfully sended on the queue
126 * @tx_max: Maximum number packets the driver can send
127 * @napi: NAPI structure
128 * @read_reg: For reading data from CAN registers
129 * @write_reg: For writing data to CAN registers
130 * @dev: Network device data structure
131 * @reg_base: Ioremapped address to registers
132 * @irq_flags: For request_irq()
133 * @bus_clk: Pointer to struct clk
134 * @can_clk: Pointer to struct clk
139 unsigned int tx_head;
140 unsigned int tx_tail;
142 struct napi_struct napi;
143 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
144 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
146 struct net_device *dev;
147 void __iomem *reg_base;
148 unsigned long irq_flags;
153 /* CAN Bittiming constants as per Xilinx CAN specs */
154 static const struct can_bittiming_const xcan_bittiming_const = {
166 #define XCAN_CAP_WATERMARK 0x0001
167 struct xcan_devtype_data {
172 * xcan_write_reg_le - Write a value to the device register little endian
173 * @priv: Driver private data structure
174 * @reg: Register offset
175 * @val: Value to write at the Register offset
177 * Write data to the paricular CAN register
179 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
182 iowrite32(val, priv->reg_base + reg);
186 * xcan_read_reg_le - Read a value from the device register little endian
187 * @priv: Driver private data structure
188 * @reg: Register offset
190 * Read data from the particular CAN register
191 * Return: value read from the CAN register
193 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
195 return ioread32(priv->reg_base + reg);
199 * xcan_write_reg_be - Write a value to the device register big endian
200 * @priv: Driver private data structure
201 * @reg: Register offset
202 * @val: Value to write at the Register offset
204 * Write data to the paricular CAN register
206 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
209 iowrite32be(val, priv->reg_base + reg);
213 * xcan_read_reg_be - Read a value from the device register big endian
214 * @priv: Driver private data structure
215 * @reg: Register offset
217 * Read data from the particular CAN register
218 * Return: value read from the CAN register
220 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
222 return ioread32be(priv->reg_base + reg);
226 * set_reset_mode - Resets the CAN device mode
227 * @ndev: Pointer to net_device structure
229 * This is the driver reset mode routine.The driver
230 * enters into configuration mode.
232 * Return: 0 on success and failure value on error
234 static int set_reset_mode(struct net_device *ndev)
236 struct xcan_priv *priv = netdev_priv(ndev);
237 unsigned long timeout;
239 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
241 timeout = jiffies + XCAN_TIMEOUT;
242 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
243 if (time_after(jiffies, timeout)) {
244 netdev_warn(ndev, "timed out for config mode\n");
247 usleep_range(500, 10000);
250 /* reset clears FIFOs */
258 * xcan_set_bittiming - CAN set bit timing routine
259 * @ndev: Pointer to net_device structure
261 * This is the driver set bittiming routine.
262 * Return: 0 on success and failure value on error
264 static int xcan_set_bittiming(struct net_device *ndev)
266 struct xcan_priv *priv = netdev_priv(ndev);
267 struct can_bittiming *bt = &priv->can.bittiming;
271 /* Check whether Xilinx CAN is in configuration mode.
272 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
274 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
276 if (!is_config_mode) {
278 "BUG! Cannot set bittiming - CAN is not in config mode\n");
282 /* Setting Baud Rate prescalar value in BRPR Register */
283 btr0 = (bt->brp - 1);
285 /* Setting Time Segment 1 in BTR Register */
286 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
288 /* Setting Time Segment 2 in BTR Register */
289 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
291 /* Setting Synchronous jump width in BTR Register */
292 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
294 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
295 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
297 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
298 priv->read_reg(priv, XCAN_BRPR_OFFSET),
299 priv->read_reg(priv, XCAN_BTR_OFFSET));
305 * xcan_chip_start - This the drivers start routine
306 * @ndev: Pointer to net_device structure
308 * This is the drivers start routine.
309 * Based on the State of the CAN device it puts
310 * the CAN device into a proper mode.
312 * Return: 0 on success and failure value on error
314 static int xcan_chip_start(struct net_device *ndev)
316 struct xcan_priv *priv = netdev_priv(ndev);
317 u32 reg_msr, reg_sr_mask;
319 unsigned long timeout;
321 /* Check if it is in reset mode */
322 err = set_reset_mode(ndev);
326 err = xcan_set_bittiming(ndev);
330 /* Enable interrupts */
331 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
333 /* Check whether it is loopback mode or normal mode */
334 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
335 reg_msr = XCAN_MSR_LBACK_MASK;
336 reg_sr_mask = XCAN_SR_LBACK_MASK;
339 reg_sr_mask = XCAN_SR_NORMAL_MASK;
342 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
343 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
345 timeout = jiffies + XCAN_TIMEOUT;
346 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
347 if (time_after(jiffies, timeout)) {
349 "timed out for correct mode\n");
353 netdev_dbg(ndev, "status:#x%08x\n",
354 priv->read_reg(priv, XCAN_SR_OFFSET));
356 priv->can.state = CAN_STATE_ERROR_ACTIVE;
361 * xcan_do_set_mode - This sets the mode of the driver
362 * @ndev: Pointer to net_device structure
363 * @mode: Tells the mode of the driver
365 * This check the drivers state and calls the
366 * the corresponding modes to set.
368 * Return: 0 on success and failure value on error
370 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
376 ret = xcan_chip_start(ndev);
378 netdev_err(ndev, "xcan_chip_start failed!\n");
381 netif_wake_queue(ndev);
392 * xcan_start_xmit - Starts the transmission
393 * @skb: sk_buff pointer that contains data to be Txed
394 * @ndev: Pointer to net_device structure
396 * This function is invoked from upper layers to initiate transmission. This
397 * function uses the next available free txbuff and populates their fields to
398 * start the transmission.
400 * Return: 0 on success and failure value on error
402 static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
404 struct xcan_priv *priv = netdev_priv(ndev);
405 struct net_device_stats *stats = &ndev->stats;
406 struct can_frame *cf = (struct can_frame *)skb->data;
407 u32 id, dlc, data[2] = {0, 0};
410 if (can_dropped_invalid_skb(ndev, skb))
413 /* Check if the TX buffer is full */
414 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
415 XCAN_SR_TXFLL_MASK)) {
416 netif_stop_queue(ndev);
417 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
418 return NETDEV_TX_BUSY;
421 /* Watch carefully on the bit sequence */
422 if (cf->can_id & CAN_EFF_FLAG) {
423 /* Extended CAN ID format */
424 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
426 id |= (((cf->can_id & CAN_EFF_MASK) >>
427 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
428 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
430 /* The substibute remote TX request bit should be "1"
431 * for extended frames as in the Xilinx CAN datasheet
433 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
435 if (cf->can_id & CAN_RTR_FLAG)
436 /* Extended frames remote TX request */
437 id |= XCAN_IDR_RTR_MASK;
439 /* Standard CAN ID format */
440 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
443 if (cf->can_id & CAN_RTR_FLAG)
444 /* Standard frames remote TX request */
445 id |= XCAN_IDR_SRR_MASK;
448 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
451 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
453 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
455 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
457 spin_lock_irqsave(&priv->tx_lock, flags);
461 /* Write the Frame to Xilinx CAN TX FIFO */
462 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
463 /* If the CAN frame is RTR frame this write triggers tranmission */
464 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
465 if (!(cf->can_id & CAN_RTR_FLAG)) {
466 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
467 /* If the CAN frame is Standard/Extended frame this
468 * write triggers tranmission
470 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
471 stats->tx_bytes += cf->can_dlc;
474 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */
475 if (priv->tx_max > 1)
476 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK);
478 /* Check if the TX buffer is full */
479 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
480 netif_stop_queue(ndev);
482 spin_unlock_irqrestore(&priv->tx_lock, flags);
488 * xcan_rx - Is called from CAN isr to complete the received
490 * @ndev: Pointer to net_device structure
492 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
493 * does minimal processing and invokes "netif_receive_skb" to complete further
495 * Return: 1 on success and 0 on failure.
497 static int xcan_rx(struct net_device *ndev)
499 struct xcan_priv *priv = netdev_priv(ndev);
500 struct net_device_stats *stats = &ndev->stats;
501 struct can_frame *cf;
503 u32 id_xcan, dlc, data[2] = {0, 0};
505 skb = alloc_can_skb(ndev, &cf);
506 if (unlikely(!skb)) {
511 /* Read a frame from Xilinx zynq CANPS */
512 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
513 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
516 /* Change Xilinx CAN data length format to socketCAN data format */
517 cf->can_dlc = get_can_dlc(dlc);
519 /* Change Xilinx CAN ID format to socketCAN ID format */
520 if (id_xcan & XCAN_IDR_IDE_MASK) {
521 /* The received frame is an Extended format frame */
522 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
523 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
525 cf->can_id |= CAN_EFF_FLAG;
526 if (id_xcan & XCAN_IDR_RTR_MASK)
527 cf->can_id |= CAN_RTR_FLAG;
529 /* The received frame is a standard format frame */
530 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
532 if (id_xcan & XCAN_IDR_SRR_MASK)
533 cf->can_id |= CAN_RTR_FLAG;
536 /* DW1/DW2 must always be read to remove message from RXFIFO */
537 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
538 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
540 if (!(cf->can_id & CAN_RTR_FLAG)) {
541 /* Change Xilinx CAN data format to socketCAN data format */
543 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
545 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
548 stats->rx_bytes += cf->can_dlc;
550 netif_receive_skb(skb);
556 * xcan_current_error_state - Get current error state from HW
557 * @ndev: Pointer to net_device structure
559 * Checks the current CAN error state from the HW. Note that this
560 * only checks for ERROR_PASSIVE and ERROR_WARNING.
563 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE
566 static enum can_state xcan_current_error_state(struct net_device *ndev)
568 struct xcan_priv *priv = netdev_priv(ndev);
569 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET);
571 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK)
572 return CAN_STATE_ERROR_PASSIVE;
573 else if (status & XCAN_SR_ERRWRN_MASK)
574 return CAN_STATE_ERROR_WARNING;
576 return CAN_STATE_ERROR_ACTIVE;
580 * xcan_set_error_state - Set new CAN error state
581 * @ndev: Pointer to net_device structure
582 * @new_state: The new CAN state to be set
583 * @cf: Error frame to be populated or NULL
585 * Set new CAN error state for the device, updating statistics and
586 * populating the error frame if given.
588 static void xcan_set_error_state(struct net_device *ndev,
589 enum can_state new_state,
590 struct can_frame *cf)
592 struct xcan_priv *priv = netdev_priv(ndev);
593 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET);
594 u32 txerr = ecr & XCAN_ECR_TEC_MASK;
595 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT;
597 priv->can.state = new_state;
600 cf->can_id |= CAN_ERR_CRTL;
606 case CAN_STATE_ERROR_PASSIVE:
607 priv->can.can_stats.error_passive++;
609 cf->data[1] = (rxerr > 127) ?
610 CAN_ERR_CRTL_RX_PASSIVE :
611 CAN_ERR_CRTL_TX_PASSIVE;
613 case CAN_STATE_ERROR_WARNING:
614 priv->can.can_stats.error_warning++;
616 cf->data[1] |= (txerr > rxerr) ?
617 CAN_ERR_CRTL_TX_WARNING :
618 CAN_ERR_CRTL_RX_WARNING;
620 case CAN_STATE_ERROR_ACTIVE:
622 cf->data[1] |= CAN_ERR_CRTL_ACTIVE;
625 /* non-ERROR states are handled elsewhere */
632 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
633 * @ndev: Pointer to net_device structure
635 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
636 * the performed RX/TX has caused it to drop to a lesser state and set
637 * the interface state accordingly.
639 static void xcan_update_error_state_after_rxtx(struct net_device *ndev)
641 struct xcan_priv *priv = netdev_priv(ndev);
642 enum can_state old_state = priv->can.state;
643 enum can_state new_state;
645 /* changing error state due to successful frame RX/TX can only
646 * occur from these states
648 if (old_state != CAN_STATE_ERROR_WARNING &&
649 old_state != CAN_STATE_ERROR_PASSIVE)
652 new_state = xcan_current_error_state(ndev);
654 if (new_state != old_state) {
656 struct can_frame *cf;
658 skb = alloc_can_err_skb(ndev, &cf);
660 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
663 struct net_device_stats *stats = &ndev->stats;
666 stats->rx_bytes += cf->can_dlc;
673 * xcan_err_interrupt - error frame Isr
674 * @ndev: net_device pointer
675 * @isr: interrupt status register value
677 * This is the CAN error interrupt and it will
678 * check the the type of error and forward the error
679 * frame to upper layers.
681 static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
683 struct xcan_priv *priv = netdev_priv(ndev);
684 struct net_device_stats *stats = &ndev->stats;
685 struct can_frame *cf;
689 skb = alloc_can_err_skb(ndev, &cf);
691 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
692 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
694 if (isr & XCAN_IXR_BSOFF_MASK) {
695 priv->can.state = CAN_STATE_BUS_OFF;
696 priv->can.can_stats.bus_off++;
697 /* Leave device in Config Mode in bus-off state */
698 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
701 cf->can_id |= CAN_ERR_BUSOFF;
703 enum can_state new_state = xcan_current_error_state(ndev);
705 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
708 /* Check for Arbitration lost interrupt */
709 if (isr & XCAN_IXR_ARBLST_MASK) {
710 priv->can.can_stats.arbitration_lost++;
712 cf->can_id |= CAN_ERR_LOSTARB;
713 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
717 /* Check for RX FIFO Overflow interrupt */
718 if (isr & XCAN_IXR_RXOFLW_MASK) {
719 stats->rx_over_errors++;
722 cf->can_id |= CAN_ERR_CRTL;
723 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
727 /* Check for error interrupt */
728 if (isr & XCAN_IXR_ERROR_MASK) {
730 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
732 /* Check for Ack error interrupt */
733 if (err_status & XCAN_ESR_ACKER_MASK) {
736 cf->can_id |= CAN_ERR_ACK;
737 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
741 /* Check for Bit error interrupt */
742 if (err_status & XCAN_ESR_BERR_MASK) {
745 cf->can_id |= CAN_ERR_PROT;
746 cf->data[2] = CAN_ERR_PROT_BIT;
750 /* Check for Stuff error interrupt */
751 if (err_status & XCAN_ESR_STER_MASK) {
754 cf->can_id |= CAN_ERR_PROT;
755 cf->data[2] = CAN_ERR_PROT_STUFF;
759 /* Check for Form error interrupt */
760 if (err_status & XCAN_ESR_FMER_MASK) {
763 cf->can_id |= CAN_ERR_PROT;
764 cf->data[2] = CAN_ERR_PROT_FORM;
768 /* Check for CRC error interrupt */
769 if (err_status & XCAN_ESR_CRCER_MASK) {
772 cf->can_id |= CAN_ERR_PROT;
773 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
776 priv->can.can_stats.bus_error++;
781 stats->rx_bytes += cf->can_dlc;
785 netdev_dbg(ndev, "%s: error status register:0x%x\n",
786 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
790 * xcan_state_interrupt - It will check the state of the CAN device
791 * @ndev: net_device pointer
792 * @isr: interrupt status register value
794 * This will checks the state of the CAN device
795 * and puts the device into appropriate state.
797 static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
799 struct xcan_priv *priv = netdev_priv(ndev);
801 /* Check for Sleep interrupt if set put CAN device in sleep state */
802 if (isr & XCAN_IXR_SLP_MASK)
803 priv->can.state = CAN_STATE_SLEEPING;
805 /* Check for Wake up interrupt if set put CAN device in Active state */
806 if (isr & XCAN_IXR_WKUP_MASK)
807 priv->can.state = CAN_STATE_ERROR_ACTIVE;
811 * xcan_rx_poll - Poll routine for rx packets (NAPI)
812 * @napi: napi structure pointer
813 * @quota: Max number of rx packets to be processed.
815 * This is the poll routine for rx part.
816 * It will process the packets maximux quota value.
818 * Return: number of packets received
820 static int xcan_rx_poll(struct napi_struct *napi, int quota)
822 struct net_device *ndev = napi->dev;
823 struct xcan_priv *priv = netdev_priv(ndev);
827 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
828 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
829 work_done += xcan_rx(ndev);
830 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
831 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
835 can_led_event(ndev, CAN_LED_EVENT_RX);
836 xcan_update_error_state_after_rxtx(ndev);
839 if (work_done < quota) {
841 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
842 ier |= XCAN_IXR_RXNEMP_MASK;
843 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
849 * xcan_tx_interrupt - Tx Done Isr
850 * @ndev: net_device pointer
851 * @isr: Interrupt status register value
853 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
855 struct xcan_priv *priv = netdev_priv(ndev);
856 struct net_device_stats *stats = &ndev->stats;
857 unsigned int frames_in_fifo;
858 int frames_sent = 1; /* TXOK => at least 1 frame was sent */
862 /* Synchronize with xmit as we need to know the exact number
863 * of frames in the FIFO to stay in sync due to the TXFEMP
865 * This also prevents a race between netif_wake_queue() and
866 * netif_stop_queue().
868 spin_lock_irqsave(&priv->tx_lock, flags);
870 frames_in_fifo = priv->tx_head - priv->tx_tail;
872 if (WARN_ON_ONCE(frames_in_fifo == 0)) {
873 /* clear TXOK anyway to avoid getting back here */
874 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
875 spin_unlock_irqrestore(&priv->tx_lock, flags);
879 /* Check if 2 frames were sent (TXOK only means that at least 1
882 if (frames_in_fifo > 1) {
883 WARN_ON(frames_in_fifo > priv->tx_max);
885 /* Synchronize TXOK and isr so that after the loop:
886 * (1) isr variable is up-to-date at least up to TXOK clear
887 * time. This avoids us clearing a TXOK of a second frame
888 * but not noticing that the FIFO is now empty and thus
889 * marking only a single frame as sent.
890 * (2) No TXOK is left. Having one could mean leaving a
891 * stray TXOK as we might process the associated frame
892 * via TXFEMP handling as we read TXFEMP *after* TXOK
893 * clear to satisfy (1).
895 while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) {
896 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
897 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
900 if (isr & XCAN_IXR_TXFEMP_MASK) {
901 /* nothing in FIFO anymore */
902 frames_sent = frames_in_fifo;
905 /* single frame in fifo, just clear TXOK */
906 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
909 while (frames_sent--) {
910 can_get_echo_skb(ndev, priv->tx_tail %
916 netif_wake_queue(ndev);
918 spin_unlock_irqrestore(&priv->tx_lock, flags);
920 can_led_event(ndev, CAN_LED_EVENT_TX);
921 xcan_update_error_state_after_rxtx(ndev);
925 * xcan_interrupt - CAN Isr
927 * @dev_id: device id poniter
929 * This is the xilinx CAN Isr. It checks for the type of interrupt
930 * and invokes the corresponding ISR.
933 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
935 static irqreturn_t xcan_interrupt(int irq, void *dev_id)
937 struct net_device *ndev = (struct net_device *)dev_id;
938 struct xcan_priv *priv = netdev_priv(ndev);
942 /* Get the interrupt status from Xilinx CAN */
943 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
947 /* Check for the type of interrupt and Processing it */
948 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
949 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
950 XCAN_IXR_WKUP_MASK));
951 xcan_state_interrupt(ndev, isr);
954 /* Check for Tx interrupt and Processing it */
955 if (isr & XCAN_IXR_TXOK_MASK)
956 xcan_tx_interrupt(ndev, isr);
958 /* Check for the type of error interrupt and Processing it */
959 isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
960 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK);
962 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors);
963 xcan_err_interrupt(ndev, isr);
966 /* Check for the type of receive interrupt and Processing it */
967 if (isr & XCAN_IXR_RXNEMP_MASK) {
968 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
969 ier &= ~XCAN_IXR_RXNEMP_MASK;
970 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
971 napi_schedule(&priv->napi);
977 * xcan_chip_stop - Driver stop routine
978 * @ndev: Pointer to net_device structure
980 * This is the drivers stop routine. It will disable the
981 * interrupts and put the device into configuration mode.
983 static void xcan_chip_stop(struct net_device *ndev)
985 struct xcan_priv *priv = netdev_priv(ndev);
988 /* Disable interrupts and leave the can in configuration mode */
989 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
990 ier &= ~XCAN_INTR_ALL;
991 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
992 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
993 priv->can.state = CAN_STATE_STOPPED;
997 * xcan_open - Driver open routine
998 * @ndev: Pointer to net_device structure
1000 * This is the driver open routine.
1001 * Return: 0 on success and failure value on error
1003 static int xcan_open(struct net_device *ndev)
1005 struct xcan_priv *priv = netdev_priv(ndev);
1008 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
1011 netdev_err(ndev, "irq allocation for CAN failed\n");
1015 ret = clk_prepare_enable(priv->can_clk);
1017 netdev_err(ndev, "unable to enable device clock\n");
1021 ret = clk_prepare_enable(priv->bus_clk);
1023 netdev_err(ndev, "unable to enable bus clock\n");
1027 /* Set chip into reset mode */
1028 ret = set_reset_mode(ndev);
1030 netdev_err(ndev, "mode resetting failed!\n");
1035 ret = open_candev(ndev);
1039 ret = xcan_chip_start(ndev);
1041 netdev_err(ndev, "xcan_chip_start failed!\n");
1045 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1046 napi_enable(&priv->napi);
1047 netif_start_queue(ndev);
1054 clk_disable_unprepare(priv->bus_clk);
1056 clk_disable_unprepare(priv->can_clk);
1058 free_irq(ndev->irq, ndev);
1064 * xcan_close - Driver close routine
1065 * @ndev: Pointer to net_device structure
1069 static int xcan_close(struct net_device *ndev)
1071 struct xcan_priv *priv = netdev_priv(ndev);
1073 netif_stop_queue(ndev);
1074 napi_disable(&priv->napi);
1075 xcan_chip_stop(ndev);
1076 clk_disable_unprepare(priv->bus_clk);
1077 clk_disable_unprepare(priv->can_clk);
1078 free_irq(ndev->irq, ndev);
1081 can_led_event(ndev, CAN_LED_EVENT_STOP);
1087 * xcan_get_berr_counter - error counter routine
1088 * @ndev: Pointer to net_device structure
1089 * @bec: Pointer to can_berr_counter structure
1091 * This is the driver error counter routine.
1092 * Return: 0 on success and failure value on error
1094 static int xcan_get_berr_counter(const struct net_device *ndev,
1095 struct can_berr_counter *bec)
1097 struct xcan_priv *priv = netdev_priv(ndev);
1100 ret = clk_prepare_enable(priv->can_clk);
1104 ret = clk_prepare_enable(priv->bus_clk);
1108 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1109 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1110 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1112 clk_disable_unprepare(priv->bus_clk);
1113 clk_disable_unprepare(priv->can_clk);
1118 clk_disable_unprepare(priv->can_clk);
1124 static const struct net_device_ops xcan_netdev_ops = {
1125 .ndo_open = xcan_open,
1126 .ndo_stop = xcan_close,
1127 .ndo_start_xmit = xcan_start_xmit,
1128 .ndo_change_mtu = can_change_mtu,
1132 * xcan_suspend - Suspend method for the driver
1133 * @dev: Address of the platform_device structure
1135 * Put the driver into low power mode.
1138 static int __maybe_unused xcan_suspend(struct device *dev)
1140 struct platform_device *pdev = dev_get_drvdata(dev);
1141 struct net_device *ndev = platform_get_drvdata(pdev);
1142 struct xcan_priv *priv = netdev_priv(ndev);
1144 if (netif_running(ndev)) {
1145 netif_stop_queue(ndev);
1146 netif_device_detach(ndev);
1149 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
1150 priv->can.state = CAN_STATE_SLEEPING;
1152 clk_disable(priv->bus_clk);
1153 clk_disable(priv->can_clk);
1159 * xcan_resume - Resume from suspend
1160 * @dev: Address of the platformdevice structure
1162 * Resume operation after suspend.
1163 * Return: 0 on success and failure value on error
1165 static int __maybe_unused xcan_resume(struct device *dev)
1167 struct platform_device *pdev = dev_get_drvdata(dev);
1168 struct net_device *ndev = platform_get_drvdata(pdev);
1169 struct xcan_priv *priv = netdev_priv(ndev);
1172 ret = clk_enable(priv->bus_clk);
1174 dev_err(dev, "Cannot enable clock.\n");
1177 ret = clk_enable(priv->can_clk);
1179 dev_err(dev, "Cannot enable clock.\n");
1180 clk_disable_unprepare(priv->bus_clk);
1184 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1185 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1186 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1188 if (netif_running(ndev)) {
1189 netif_device_attach(ndev);
1190 netif_start_queue(ndev);
1196 static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1198 static const struct xcan_devtype_data xcan_zynq_data = {
1199 .caps = XCAN_CAP_WATERMARK,
1202 /* Match table for OF platform binding */
1203 static const struct of_device_id xcan_of_match[] = {
1204 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1205 { .compatible = "xlnx,axi-can-1.00.a", },
1206 { /* end of list */ },
1208 MODULE_DEVICE_TABLE(of, xcan_of_match);
1211 * xcan_probe - Platform registration call
1212 * @pdev: Handle to the platform device structure
1214 * This function does all the memory allocation and registration for the CAN
1217 * Return: 0 on success and failure value on error
1219 static int xcan_probe(struct platform_device *pdev)
1221 struct resource *res; /* IO mem resources */
1222 struct net_device *ndev;
1223 struct xcan_priv *priv;
1224 const struct of_device_id *of_id;
1227 int ret, rx_max, tx_max, tx_fifo_depth;
1229 /* Get the virtual base address for the device */
1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1231 addr = devm_ioremap_resource(&pdev->dev, res);
1233 ret = PTR_ERR(addr);
1237 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1242 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1246 of_id = of_match_device(xcan_of_match, &pdev->dev);
1248 const struct xcan_devtype_data *devtype_data = of_id->data;
1251 caps = devtype_data->caps;
1254 /* There is no way to directly figure out how many frames have been
1255 * sent when the TXOK interrupt is processed. If watermark programming
1256 * is supported, we can have 2 frames in the FIFO and use TXFEMP
1257 * to determine if 1 or 2 frames have been sent.
1258 * Theoretically we should be able to use TXFWMEMP to determine up
1259 * to 3 frames, but it seems that after putting a second frame in the
1260 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less
1261 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was
1262 * sent), which is not a sensible state - possibly TXFWMEMP is not
1263 * completely synchronized with the rest of the bits?
1265 if (caps & XCAN_CAP_WATERMARK)
1266 tx_max = min(tx_fifo_depth, 2);
1270 /* Create a CAN device instance */
1271 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1275 priv = netdev_priv(ndev);
1277 priv->can.bittiming_const = &xcan_bittiming_const;
1278 priv->can.do_set_mode = xcan_do_set_mode;
1279 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1280 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1281 CAN_CTRLMODE_BERR_REPORTING;
1282 priv->reg_base = addr;
1283 priv->tx_max = tx_max;
1284 spin_lock_init(&priv->tx_lock);
1286 /* Get IRQ for the device */
1287 ndev->irq = platform_get_irq(pdev, 0);
1288 ndev->flags |= IFF_ECHO; /* We support local echo */
1290 platform_set_drvdata(pdev, ndev);
1291 SET_NETDEV_DEV(ndev, &pdev->dev);
1292 ndev->netdev_ops = &xcan_netdev_ops;
1294 /* Getting the CAN can_clk info */
1295 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1296 if (IS_ERR(priv->can_clk)) {
1297 dev_err(&pdev->dev, "Device clock not found.\n");
1298 ret = PTR_ERR(priv->can_clk);
1301 /* Check for type of CAN device */
1302 if (of_device_is_compatible(pdev->dev.of_node,
1303 "xlnx,zynq-can-1.0")) {
1304 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1305 if (IS_ERR(priv->bus_clk)) {
1306 dev_err(&pdev->dev, "bus clock not found\n");
1307 ret = PTR_ERR(priv->bus_clk);
1311 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1312 if (IS_ERR(priv->bus_clk)) {
1313 dev_err(&pdev->dev, "bus clock not found\n");
1314 ret = PTR_ERR(priv->bus_clk);
1319 ret = clk_prepare_enable(priv->can_clk);
1321 dev_err(&pdev->dev, "unable to enable device clock\n");
1325 ret = clk_prepare_enable(priv->bus_clk);
1327 dev_err(&pdev->dev, "unable to enable bus clock\n");
1328 goto err_unprepare_disable_dev;
1331 priv->write_reg = xcan_write_reg_le;
1332 priv->read_reg = xcan_read_reg_le;
1334 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1335 priv->write_reg = xcan_write_reg_be;
1336 priv->read_reg = xcan_read_reg_be;
1339 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1341 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1343 ret = register_candev(ndev);
1345 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1346 goto err_unprepare_disable_busclk;
1349 devm_can_led_init(ndev);
1350 clk_disable_unprepare(priv->bus_clk);
1351 clk_disable_unprepare(priv->can_clk);
1352 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth: actual %d, using %d\n",
1353 priv->reg_base, ndev->irq, priv->can.clock.freq,
1354 tx_fifo_depth, priv->tx_max);
1358 err_unprepare_disable_busclk:
1359 clk_disable_unprepare(priv->bus_clk);
1360 err_unprepare_disable_dev:
1361 clk_disable_unprepare(priv->can_clk);
1369 * xcan_remove - Unregister the device after releasing the resources
1370 * @pdev: Handle to the platform device structure
1372 * This function frees all the resources allocated to the device.
1375 static int xcan_remove(struct platform_device *pdev)
1377 struct net_device *ndev = platform_get_drvdata(pdev);
1378 struct xcan_priv *priv = netdev_priv(ndev);
1380 if (set_reset_mode(ndev) < 0)
1381 netdev_err(ndev, "mode resetting failed!\n");
1383 unregister_candev(ndev);
1384 netif_napi_del(&priv->napi);
1390 static struct platform_driver xcan_driver = {
1391 .probe = xcan_probe,
1392 .remove = xcan_remove,
1394 .name = DRIVER_NAME,
1395 .pm = &xcan_dev_pm_ops,
1396 .of_match_table = xcan_of_match,
1400 module_platform_driver(xcan_driver);
1402 MODULE_LICENSE("GPL");
1403 MODULE_AUTHOR("Xilinx Inc");
1404 MODULE_DESCRIPTION("Xilinx CAN interface");