1 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
3 * Copyright(C) Timesys Corporation 2016
5 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
6 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
7 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
8 * Copyright 2006 Arcom Control Systems Ltd.
10 * Based on CAN bus driver for the CCAN controller written by
11 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
12 * - Simon Kallweit, intefo AG
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/can/core.h>
21 #include <linux/can/dev.h>
22 #include <linux/can/led.h>
23 #include <linux/clk.h>
24 #include <linux/completion.h>
25 #include <linux/delay.h>
26 #include <linux/device.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/freezer.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/netdevice.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/slab.h>
39 #include <linux/spi/spi.h>
40 #include <linux/uaccess.h>
42 #define HI3110_MASTER_RESET 0x56
43 #define HI3110_READ_CTRL0 0xD2
44 #define HI3110_READ_CTRL1 0xD4
45 #define HI3110_READ_STATF 0xE2
46 #define HI3110_WRITE_CTRL0 0x14
47 #define HI3110_WRITE_CTRL1 0x16
48 #define HI3110_WRITE_INTE 0x1C
49 #define HI3110_WRITE_BTR0 0x18
50 #define HI3110_WRITE_BTR1 0x1A
51 #define HI3110_READ_BTR0 0xD6
52 #define HI3110_READ_BTR1 0xD8
53 #define HI3110_READ_INTF 0xDE
54 #define HI3110_READ_ERR 0xDC
55 #define HI3110_READ_FIFO_WOTIME 0x48
56 #define HI3110_WRITE_FIFO 0x12
57 #define HI3110_READ_MESSTAT 0xDA
58 #define HI3110_READ_REC 0xEA
59 #define HI3110_READ_TEC 0xEC
61 #define HI3110_CTRL0_MODE_MASK (7 << 5)
62 #define HI3110_CTRL0_NORMAL_MODE (0 << 5)
63 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
64 #define HI3110_CTRL0_MONITOR_MODE (2 << 5)
65 #define HI3110_CTRL0_SLEEP_MODE (3 << 5)
66 #define HI3110_CTRL0_INIT_MODE (4 << 5)
68 #define HI3110_CTRL1_TXEN BIT(7)
70 #define HI3110_INT_RXTMP BIT(7)
71 #define HI3110_INT_RXFIFO BIT(6)
72 #define HI3110_INT_TXCPLT BIT(5)
73 #define HI3110_INT_BUSERR BIT(4)
74 #define HI3110_INT_MCHG BIT(3)
75 #define HI3110_INT_WAKEUP BIT(2)
76 #define HI3110_INT_F1MESS BIT(1)
77 #define HI3110_INT_F0MESS BIT(0)
79 #define HI3110_ERR_BUSOFF BIT(7)
80 #define HI3110_ERR_TXERRP BIT(6)
81 #define HI3110_ERR_RXERRP BIT(5)
82 #define HI3110_ERR_BITERR BIT(4)
83 #define HI3110_ERR_FRMERR BIT(3)
84 #define HI3110_ERR_CRCERR BIT(2)
85 #define HI3110_ERR_ACKERR BIT(1)
86 #define HI3110_ERR_STUFERR BIT(0)
87 #define HI3110_ERR_PROTOCOL_MASK (0x1F)
88 #define HI3110_ERR_PASSIVE_MASK (0x60)
90 #define HI3110_STAT_RXFMTY BIT(1)
91 #define HI3110_STAT_BUSOFF BIT(2)
92 #define HI3110_STAT_ERRP BIT(3)
93 #define HI3110_STAT_ERRW BIT(4)
94 #define HI3110_STAT_TXMTY BIT(7)
96 #define HI3110_BTR0_SJW_SHIFT 6
97 #define HI3110_BTR0_BRP_SHIFT 0
99 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
100 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
101 #define HI3110_BTR1_TSEG2_SHIFT 4
102 #define HI3110_BTR1_TSEG1_SHIFT 0
104 #define HI3110_FIFO_WOTIME_TAG_OFF 0
105 #define HI3110_FIFO_WOTIME_ID_OFF 1
106 #define HI3110_FIFO_WOTIME_DLC_OFF 5
107 #define HI3110_FIFO_WOTIME_DAT_OFF 6
109 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
110 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
112 #define HI3110_FIFO_TAG_OFF 0
113 #define HI3110_FIFO_ID_OFF 1
114 #define HI3110_FIFO_STD_DLC_OFF 3
115 #define HI3110_FIFO_STD_DATA_OFF 4
116 #define HI3110_FIFO_EXT_DLC_OFF 5
117 #define HI3110_FIFO_EXT_DATA_OFF 6
119 #define HI3110_CAN_MAX_DATA_LEN 8
120 #define HI3110_RX_BUF_LEN 15
121 #define HI3110_TX_STD_BUF_LEN 12
122 #define HI3110_TX_EXT_BUF_LEN 14
123 #define HI3110_CAN_FRAME_MAX_BITS 128
124 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */
126 #define HI3110_TX_ECHO_SKB_MAX 1
128 #define HI3110_OST_DELAY_MS (10)
130 #define DEVICE_NAME "hi3110"
132 static int hi3110_enable_dma = 1; /* Enable SPI DMA. Default: 1 (On) */
133 module_param(hi3110_enable_dma, int, 0444);
134 MODULE_PARM_DESC(hi3110_enable_dma, "Enable SPI DMA. Default: 1 (On)");
136 static const struct can_bittiming_const hi3110_bittiming_const = {
149 CAN_HI3110_HI3110 = 0x3110,
154 struct net_device *net;
155 struct spi_device *spi;
156 enum hi3110_model model;
158 struct mutex hi3110_lock; /* SPI device lock */
162 dma_addr_t spi_tx_dma;
163 dma_addr_t spi_rx_dma;
165 struct sk_buff *tx_skb;
168 struct workqueue_struct *wq;
169 struct work_struct tx_work;
170 struct work_struct restart_work;
174 #define HI3110_AFTER_SUSPEND_UP 1
175 #define HI3110_AFTER_SUSPEND_DOWN 2
176 #define HI3110_AFTER_SUSPEND_POWER 4
177 #define HI3110_AFTER_SUSPEND_RESTART 8
179 struct regulator *power;
180 struct regulator *transceiver;
184 static void hi3110_clean(struct net_device *net)
186 struct hi3110_priv *priv = netdev_priv(net);
188 if (priv->tx_skb || priv->tx_len)
189 net->stats.tx_errors++;
191 dev_kfree_skb(priv->tx_skb);
193 can_free_echo_skb(priv->net, 0);
198 /* Note about handling of error return of hi3110_spi_trans: accessing
199 * registers via SPI is not really different conceptually than using
200 * normal I/O assembler instructions, although it's much more
201 * complicated from a practical POV. So it's not advisable to always
202 * check the return value of this function. Imagine that every
203 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
204 * error();", it would be a great mess (well there are some situation
205 * when exception handling C++ like could be useful after all). So we
206 * just check that transfers are OK at the beginning of our
207 * conversation with the chip and to avoid doing really nasty things
208 * (like injecting bogus packets in the network stack).
210 static int hi3110_spi_trans(struct spi_device *spi, int len)
212 struct hi3110_priv *priv = spi_get_drvdata(spi);
213 struct spi_transfer t = {
214 .tx_buf = priv->spi_tx_buf,
215 .rx_buf = priv->spi_rx_buf,
219 struct spi_message m;
222 spi_message_init(&m);
224 if (hi3110_enable_dma) {
225 t.tx_dma = priv->spi_tx_dma;
226 t.rx_dma = priv->spi_rx_dma;
230 spi_message_add_tail(&t, &m);
232 ret = spi_sync(spi, &m);
235 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
239 static int hi3110_cmd(struct spi_device *spi, u8 command)
241 struct hi3110_priv *priv = spi_get_drvdata(spi);
243 priv->spi_tx_buf[0] = command;
244 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
246 return hi3110_spi_trans(spi, 1);
249 static u8 hi3110_read(struct spi_device *spi, u8 command)
251 struct hi3110_priv *priv = spi_get_drvdata(spi);
254 priv->spi_tx_buf[0] = command;
255 hi3110_spi_trans(spi, 2);
256 val = priv->spi_rx_buf[1];
261 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
263 struct hi3110_priv *priv = spi_get_drvdata(spi);
265 priv->spi_tx_buf[0] = reg;
266 priv->spi_tx_buf[1] = val;
267 hi3110_spi_trans(spi, 2);
270 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
272 struct hi3110_priv *priv = spi_get_drvdata(spi);
274 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
275 memcpy(priv->spi_tx_buf + 1, buf, len);
276 hi3110_spi_trans(spi, len + 1);
279 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
281 u8 buf[HI3110_TX_EXT_BUF_LEN];
283 buf[HI3110_FIFO_TAG_OFF] = 0;
285 if (frame->can_id & CAN_EFF_FLAG) {
287 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
288 buf[HI3110_FIFO_ID_OFF + 1] =
289 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
291 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
292 buf[HI3110_FIFO_ID_OFF + 2] =
293 (frame->can_id & CAN_EFF_MASK) >> 7;
294 buf[HI3110_FIFO_ID_OFF + 3] =
295 ((frame->can_id & CAN_EFF_MASK) << 1) |
296 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
298 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc;
300 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
301 frame->data, frame->can_dlc);
303 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
304 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
307 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3;
308 buf[HI3110_FIFO_ID_OFF + 1] =
309 ((frame->can_id & CAN_SFF_MASK) << 5) |
310 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
312 buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc;
314 memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
315 frame->data, frame->can_dlc);
317 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
318 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
322 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
324 struct hi3110_priv *priv = spi_get_drvdata(spi);
326 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
327 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
328 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
331 static void hi3110_hw_rx(struct spi_device *spi)
333 struct hi3110_priv *priv = spi_get_drvdata(spi);
335 struct can_frame *frame;
336 u8 buf[HI3110_RX_BUF_LEN - 1];
338 skb = alloc_can_skb(priv->net, &frame);
340 priv->net->stats.rx_dropped++;
344 hi3110_hw_rx_frame(spi, buf);
345 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
346 /* IDE is recessive (1), indicating extended 29-bit frame */
347 frame->can_id = CAN_EFF_FLAG;
349 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
350 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
351 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
352 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
353 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
355 /* IDE is dominant (0), frame indicating standard 11-bit */
357 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
358 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
362 frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
364 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
365 frame->can_id |= CAN_RTR_FLAG;
367 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
370 priv->net->stats.rx_packets++;
371 priv->net->stats.rx_bytes += frame->can_dlc;
373 can_led_event(priv->net, CAN_LED_EVENT_RX);
378 static void hi3110_hw_sleep(struct spi_device *spi)
380 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
383 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
384 struct net_device *net)
386 struct hi3110_priv *priv = netdev_priv(net);
387 struct spi_device *spi = priv->spi;
389 if (priv->tx_skb || priv->tx_len) {
390 dev_err(&spi->dev, "hard_xmit called while tx busy\n");
391 return NETDEV_TX_BUSY;
394 if (can_dropped_invalid_skb(net, skb))
397 netif_stop_queue(net);
399 queue_work(priv->wq, &priv->tx_work);
404 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
406 struct hi3110_priv *priv = netdev_priv(net);
411 /* We have to delay work since SPI I/O may sleep */
412 priv->can.state = CAN_STATE_ERROR_ACTIVE;
413 priv->restart_tx = 1;
414 if (priv->can.restart_ms == 0)
415 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
416 queue_work(priv->wq, &priv->restart_work);
425 static int hi3110_get_berr_counter(const struct net_device *net,
426 struct can_berr_counter *bec)
428 struct hi3110_priv *priv = netdev_priv(net);
429 struct spi_device *spi = priv->spi;
431 mutex_lock(&priv->hi3110_lock);
432 bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
433 bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
434 mutex_unlock(&priv->hi3110_lock);
439 static int hi3110_set_normal_mode(struct spi_device *spi)
441 struct hi3110_priv *priv = spi_get_drvdata(spi);
444 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
445 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
448 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
450 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
451 reg = HI3110_CTRL0_LOOPBACK_MODE;
452 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
453 reg = HI3110_CTRL0_MONITOR_MODE;
455 reg = HI3110_CTRL0_NORMAL_MODE;
457 hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
459 /* Wait for the device to enter the mode */
460 mdelay(HI3110_OST_DELAY_MS);
461 reg = hi3110_read(spi, HI3110_READ_CTRL0);
462 if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
465 priv->can.state = CAN_STATE_ERROR_ACTIVE;
469 static int hi3110_do_set_bittiming(struct net_device *net)
471 struct hi3110_priv *priv = netdev_priv(net);
472 struct can_bittiming *bt = &priv->can.bittiming;
473 struct spi_device *spi = priv->spi;
475 hi3110_write(spi, HI3110_WRITE_BTR0,
476 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
477 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
479 hi3110_write(spi, HI3110_WRITE_BTR1,
480 (priv->can.ctrlmode &
481 CAN_CTRLMODE_3_SAMPLES ?
482 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
483 ((bt->phase_seg1 + bt->prop_seg - 1)
484 << HI3110_BTR1_TSEG1_SHIFT) |
485 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
487 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
488 hi3110_read(spi, HI3110_READ_BTR0),
489 hi3110_read(spi, HI3110_READ_BTR1));
494 static int hi3110_setup(struct net_device *net)
496 hi3110_do_set_bittiming(net);
500 static int hi3110_hw_reset(struct spi_device *spi)
505 /* Wait for oscillator startup timer after power up */
506 mdelay(HI3110_OST_DELAY_MS);
508 ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
512 /* Wait for oscillator startup timer after reset */
513 mdelay(HI3110_OST_DELAY_MS);
515 reg = hi3110_read(spi, HI3110_READ_CTRL0);
516 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
519 /* As per the datasheet it appears the error flags are
520 * not cleared on reset. Explicitly clear them by performing a read
522 hi3110_read(spi, HI3110_READ_ERR);
527 static int hi3110_hw_probe(struct spi_device *spi)
531 hi3110_hw_reset(spi);
533 /* Confirm correct operation by checking against reset values
536 statf = hi3110_read(spi, HI3110_READ_STATF);
538 dev_dbg(&spi->dev, "statf: %02X\n", statf);
546 static int hi3110_power_enable(struct regulator *reg, int enable)
548 if (IS_ERR_OR_NULL(reg))
552 return regulator_enable(reg);
554 return regulator_disable(reg);
557 static int hi3110_stop(struct net_device *net)
559 struct hi3110_priv *priv = netdev_priv(net);
560 struct spi_device *spi = priv->spi;
564 priv->force_quit = 1;
565 free_irq(spi->irq, priv);
566 destroy_workqueue(priv->wq);
569 mutex_lock(&priv->hi3110_lock);
571 /* Disable transmit, interrupts and clear flags */
572 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
573 hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
574 hi3110_read(spi, HI3110_READ_INTF);
578 hi3110_hw_sleep(spi);
580 hi3110_power_enable(priv->transceiver, 0);
582 priv->can.state = CAN_STATE_STOPPED;
584 mutex_unlock(&priv->hi3110_lock);
586 can_led_event(net, CAN_LED_EVENT_STOP);
591 static void hi3110_tx_work_handler(struct work_struct *ws)
593 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
595 struct spi_device *spi = priv->spi;
596 struct net_device *net = priv->net;
597 struct can_frame *frame;
599 mutex_lock(&priv->hi3110_lock);
601 if (priv->can.state == CAN_STATE_BUS_OFF) {
604 frame = (struct can_frame *)priv->tx_skb->data;
605 hi3110_hw_tx(spi, frame);
606 priv->tx_len = 1 + frame->can_dlc;
607 can_put_echo_skb(priv->tx_skb, net, 0);
611 mutex_unlock(&priv->hi3110_lock);
614 static void hi3110_restart_work_handler(struct work_struct *ws)
616 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
618 struct spi_device *spi = priv->spi;
619 struct net_device *net = priv->net;
621 mutex_lock(&priv->hi3110_lock);
622 if (priv->after_suspend) {
623 hi3110_hw_reset(spi);
625 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
626 hi3110_set_normal_mode(spi);
627 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
628 netif_device_attach(net);
630 hi3110_set_normal_mode(spi);
631 netif_wake_queue(net);
633 hi3110_hw_sleep(spi);
635 priv->after_suspend = 0;
636 priv->force_quit = 0;
639 if (priv->restart_tx) {
640 priv->restart_tx = 0;
641 hi3110_hw_reset(spi);
644 hi3110_set_normal_mode(spi);
645 netif_wake_queue(net);
647 mutex_unlock(&priv->hi3110_lock);
650 static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
652 struct hi3110_priv *priv = dev_id;
653 struct spi_device *spi = priv->spi;
654 struct net_device *net = priv->net;
656 mutex_lock(&priv->hi3110_lock);
658 while (!priv->force_quit) {
659 enum can_state new_state;
660 u8 intf, eflag, statf;
662 while (!(HI3110_STAT_RXFMTY &
663 (statf = hi3110_read(spi, HI3110_READ_STATF)))) {
667 intf = hi3110_read(spi, HI3110_READ_INTF);
668 eflag = hi3110_read(spi, HI3110_READ_ERR);
669 /* Update can state */
670 if (eflag & HI3110_ERR_BUSOFF)
671 new_state = CAN_STATE_BUS_OFF;
672 else if (eflag & HI3110_ERR_PASSIVE_MASK)
673 new_state = CAN_STATE_ERROR_PASSIVE;
674 else if (statf & HI3110_STAT_ERRW)
675 new_state = CAN_STATE_ERROR_WARNING;
677 new_state = CAN_STATE_ERROR_ACTIVE;
679 if (new_state != priv->can.state) {
680 struct can_frame *cf;
682 enum can_state rx_state, tx_state;
685 skb = alloc_can_err_skb(net, &cf);
689 txerr = hi3110_read(spi, HI3110_READ_TEC);
690 rxerr = hi3110_read(spi, HI3110_READ_REC);
691 tx_state = txerr >= rxerr ? new_state : 0;
692 rx_state = txerr <= rxerr ? new_state : 0;
693 can_change_state(net, cf, tx_state, rx_state);
696 if (new_state == CAN_STATE_BUS_OFF) {
698 if (priv->can.restart_ms == 0) {
699 priv->force_quit = 1;
700 hi3110_hw_sleep(spi);
709 /* Update bus errors */
710 if ((intf & HI3110_INT_BUSERR) &&
711 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
712 struct can_frame *cf;
715 /* Check for protocol errors */
716 if (eflag & HI3110_ERR_PROTOCOL_MASK) {
717 skb = alloc_can_err_skb(net, &cf);
721 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
722 priv->can.can_stats.bus_error++;
723 priv->net->stats.rx_errors++;
724 if (eflag & HI3110_ERR_BITERR)
725 cf->data[2] |= CAN_ERR_PROT_BIT;
726 else if (eflag & HI3110_ERR_FRMERR)
727 cf->data[2] |= CAN_ERR_PROT_FORM;
728 else if (eflag & HI3110_ERR_STUFERR)
729 cf->data[2] |= CAN_ERR_PROT_STUFF;
730 else if (eflag & HI3110_ERR_CRCERR)
731 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
732 else if (eflag & HI3110_ERR_ACKERR)
733 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
735 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
736 cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
737 netdev_dbg(priv->net, "Bus Error\n");
742 if (priv->tx_len && statf & HI3110_STAT_TXMTY) {
743 net->stats.tx_packets++;
744 net->stats.tx_bytes += priv->tx_len - 1;
745 can_led_event(net, CAN_LED_EVENT_TX);
747 can_get_echo_skb(net, 0);
750 netif_wake_queue(net);
756 mutex_unlock(&priv->hi3110_lock);
760 static int hi3110_open(struct net_device *net)
762 struct hi3110_priv *priv = netdev_priv(net);
763 struct spi_device *spi = priv->spi;
764 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH;
767 ret = open_candev(net);
771 mutex_lock(&priv->hi3110_lock);
772 hi3110_power_enable(priv->transceiver, 1);
774 priv->force_quit = 0;
778 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
779 flags, DEVICE_NAME, priv);
781 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
785 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
791 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
792 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
794 ret = hi3110_hw_reset(spi);
798 ret = hi3110_setup(net);
802 ret = hi3110_set_normal_mode(spi);
806 can_led_event(net, CAN_LED_EVENT_OPEN);
807 netif_wake_queue(net);
808 mutex_unlock(&priv->hi3110_lock);
813 destroy_workqueue(priv->wq);
815 free_irq(spi->irq, priv);
816 hi3110_hw_sleep(spi);
818 hi3110_power_enable(priv->transceiver, 0);
820 mutex_unlock(&priv->hi3110_lock);
824 static const struct net_device_ops hi3110_netdev_ops = {
825 .ndo_open = hi3110_open,
826 .ndo_stop = hi3110_stop,
827 .ndo_start_xmit = hi3110_hard_start_xmit,
830 static const struct of_device_id hi3110_of_match[] = {
832 .compatible = "holt,hi3110",
833 .data = (void *)CAN_HI3110_HI3110,
837 MODULE_DEVICE_TABLE(of, hi3110_of_match);
839 static const struct spi_device_id hi3110_id_table[] = {
842 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110,
846 MODULE_DEVICE_TABLE(spi, hi3110_id_table);
848 static int hi3110_can_probe(struct spi_device *spi)
850 const struct of_device_id *of_id = of_match_device(hi3110_of_match,
852 struct net_device *net;
853 struct hi3110_priv *priv;
857 clk = devm_clk_get(&spi->dev, NULL);
859 dev_err(&spi->dev, "no CAN clock source defined\n");
862 freq = clk_get_rate(clk);
868 /* Allocate can/net device */
869 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
874 ret = clk_prepare_enable(clk);
879 net->netdev_ops = &hi3110_netdev_ops;
880 net->flags |= IFF_ECHO;
882 priv = netdev_priv(net);
883 priv->can.bittiming_const = &hi3110_bittiming_const;
884 priv->can.do_set_mode = hi3110_do_set_mode;
885 priv->can.do_get_berr_counter = hi3110_get_berr_counter;
886 priv->can.clock.freq = freq / 2;
887 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
888 CAN_CTRLMODE_LOOPBACK |
889 CAN_CTRLMODE_LISTENONLY |
890 CAN_CTRLMODE_BERR_REPORTING;
893 priv->model = (enum hi3110_model)of_id->data;
895 priv->model = spi_get_device_id(spi)->driver_data;
899 spi_set_drvdata(spi, priv);
901 /* Configure the SPI bus */
902 spi->bits_per_word = 8;
903 ret = spi_setup(spi);
907 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
908 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
909 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
910 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
915 ret = hi3110_power_enable(priv->power, 1);
920 mutex_init(&priv->hi3110_lock);
922 /* If requested, allocate DMA buffers */
923 if (hi3110_enable_dma) {
924 spi->dev.coherent_dma_mask = ~0;
926 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate
927 * that much and share it between Tx and Rx DMA buffers.
929 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
934 if (priv->spi_tx_buf) {
935 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
936 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
939 /* Fall back to non-DMA */
940 hi3110_enable_dma = 0;
944 /* Allocate non-DMA buffers */
945 if (!hi3110_enable_dma) {
946 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
948 if (!priv->spi_tx_buf) {
952 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
955 if (!priv->spi_rx_buf) {
961 SET_NETDEV_DEV(net, &spi->dev);
963 ret = hi3110_hw_probe(spi);
966 dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
970 hi3110_hw_sleep(spi);
972 ret = register_candev(net);
976 devm_can_led_init(net);
977 netdev_info(net, "%x successfully initialized.\n", priv->model);
982 hi3110_power_enable(priv->power, 0);
986 clk_disable_unprepare(clk);
991 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
995 static int hi3110_can_remove(struct spi_device *spi)
997 struct hi3110_priv *priv = spi_get_drvdata(spi);
998 struct net_device *net = priv->net;
1000 unregister_candev(net);
1002 hi3110_power_enable(priv->power, 0);
1004 if (!IS_ERR(priv->clk))
1005 clk_disable_unprepare(priv->clk);
1012 static int __maybe_unused hi3110_can_suspend(struct device *dev)
1014 struct spi_device *spi = to_spi_device(dev);
1015 struct hi3110_priv *priv = spi_get_drvdata(spi);
1016 struct net_device *net = priv->net;
1018 priv->force_quit = 1;
1019 disable_irq(spi->irq);
1021 /* Note: at this point neither IST nor workqueues are running.
1022 * open/stop cannot be called anyway so locking is not needed
1024 if (netif_running(net)) {
1025 netif_device_detach(net);
1027 hi3110_hw_sleep(spi);
1028 hi3110_power_enable(priv->transceiver, 0);
1029 priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
1031 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
1034 if (!IS_ERR_OR_NULL(priv->power)) {
1035 regulator_disable(priv->power);
1036 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
1042 static int __maybe_unused hi3110_can_resume(struct device *dev)
1044 struct spi_device *spi = to_spi_device(dev);
1045 struct hi3110_priv *priv = spi_get_drvdata(spi);
1047 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
1048 hi3110_power_enable(priv->power, 1);
1050 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
1051 hi3110_power_enable(priv->transceiver, 1);
1052 queue_work(priv->wq, &priv->restart_work);
1054 priv->after_suspend = 0;
1057 priv->force_quit = 0;
1058 enable_irq(spi->irq);
1062 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume);
1064 static struct spi_driver hi3110_can_driver = {
1066 .name = DEVICE_NAME,
1067 .of_match_table = hi3110_of_match,
1068 .pm = &hi3110_can_pm_ops,
1070 .id_table = hi3110_id_table,
1071 .probe = hi3110_can_probe,
1072 .remove = hi3110_can_remove,
1075 module_spi_driver(hi3110_can_driver);
1077 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
1078 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
1079 MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
1080 MODULE_LICENSE("GPL v2");