drivers/net/can/rcar/rcar_canfd.c

   1 /* Renesas R-Car CAN FD device driver
   2  *
   3  * Copyright (C) 2015 Renesas Electronics Corp.
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 /* The R-Car CAN FD controller can operate in either one of the below two modes
  12  *  - CAN FD only mode
  13  *  - Classical CAN (CAN 2.0) only mode
  14  *
  15  * This driver puts the controller in CAN FD only mode by default. In this
  16  * mode, the controller acts as a CAN FD node that can also interoperate with
  17  * CAN 2.0 nodes.
  18  *
  19  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  20  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  21  * also required to switch modes.
  22  *
  23  * Note: The h/w manual register naming convention is clumsy and not acceptable
  24  * to use as it is in the driver. However, those names are added as comments
  25  * wherever it is modified to a readable name.
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/errno.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/can/led.h>
  37 #include <linux/can/dev.h>
  38 #include <linux/clk.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/bitmap.h>
  42 #include <linux/bitops.h>
  43 #include <linux/iopoll.h>
  44
  45 #define RCANFD_DRV_NAME                 "rcar_canfd"
  46
  47 /* Global register bits */
  48
  49 /* RSCFDnCFDGRMCFG */
  50 #define RCANFD_GRMCFG_RCMC              BIT(0)
  51
  52 /* RSCFDnCFDGCFG / RSCFDnGCFG */
  53 #define RCANFD_GCFG_EEFE                BIT(6)
  54 #define RCANFD_GCFG_CMPOC               BIT(5)  /* CAN FD only */
  55 #define RCANFD_GCFG_DCS                 BIT(4)
  56 #define RCANFD_GCFG_DCE                 BIT(1)
  57 #define RCANFD_GCFG_TPRI                BIT(0)
  58
  59 /* RSCFDnCFDGCTR / RSCFDnGCTR */
  60 #define RCANFD_GCTR_TSRST               BIT(16)
  61 #define RCANFD_GCTR_CFMPOFIE            BIT(11) /* CAN FD only */
  62 #define RCANFD_GCTR_THLEIE              BIT(10)
  63 #define RCANFD_GCTR_MEIE                BIT(9)
  64 #define RCANFD_GCTR_DEIE                BIT(8)
  65 #define RCANFD_GCTR_GSLPR               BIT(2)
  66 #define RCANFD_GCTR_GMDC_MASK           (0x3)
  67 #define RCANFD_GCTR_GMDC_GOPM           (0x0)
  68 #define RCANFD_GCTR_GMDC_GRESET         (0x1)
  69 #define RCANFD_GCTR_GMDC_GTEST          (0x2)
  70
  71 /* RSCFDnCFDGSTS / RSCFDnGSTS */
  72 #define RCANFD_GSTS_GRAMINIT            BIT(3)
  73 #define RCANFD_GSTS_GSLPSTS             BIT(2)
  74 #define RCANFD_GSTS_GHLTSTS             BIT(1)
  75 #define RCANFD_GSTS_GRSTSTS             BIT(0)
  76 /* Non-operational status */
  77 #define RCANFD_GSTS_GNOPM               (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  78
  79 /* RSCFDnCFDGERFL / RSCFDnGERFL */
  80 #define RCANFD_GERFL_EEF1               BIT(17)
  81 #define RCANFD_GERFL_EEF0               BIT(16)
  82 #define RCANFD_GERFL_CMPOF              BIT(3)  /* CAN FD only */
  83 #define RCANFD_GERFL_THLES              BIT(2)
  84 #define RCANFD_GERFL_MES                BIT(1)
  85 #define RCANFD_GERFL_DEF                BIT(0)
  86
  87 #define RCANFD_GERFL_ERR(gpriv, x)      ((x) & (RCANFD_GERFL_EEF1 |\
  88                                         RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
  89                                         (gpriv->fdmode ?\
  90                                          RCANFD_GERFL_CMPOF : 0)))
  91
  92 /* AFL Rx rules registers */
  93
  94 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  95 #define RCANFD_GAFLCFG_SETRNC(n, x)     (((x) & 0xff) << (24 - n * 8))
  96 #define RCANFD_GAFLCFG_GETRNC(n, x)     (((x) >> (24 - n * 8)) & 0xff)
  97
  98 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
  99 #define RCANFD_GAFLECTR_AFLDAE          BIT(8)
 100 #define RCANFD_GAFLECTR_AFLPN(x)        ((x) & 0x1f)
 101
 102 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 103 #define RCANFD_GAFLID_GAFLLB            BIT(29)
 104
 105 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 106 #define RCANFD_GAFLP1_GAFLFDP(x)        (1 << (x))
 107
 108 /* Channel register bits */
 109
 110 /* RSCFDnCmCFG - Classical CAN only */
 111 #define RCANFD_CFG_SJW(x)               (((x) & 0x3) << 24)
 112 #define RCANFD_CFG_TSEG2(x)             (((x) & 0x7) << 20)
 113 #define RCANFD_CFG_TSEG1(x)             (((x) & 0xf) << 16)
 114 #define RCANFD_CFG_BRP(x)               (((x) & 0x3ff) << 0)
 115
 116 /* RSCFDnCFDCmNCFG - CAN FD only */
 117 #define RCANFD_NCFG_NTSEG2(x)           (((x) & 0x1f) << 24)
 118 #define RCANFD_NCFG_NTSEG1(x)           (((x) & 0x7f) << 16)
 119 #define RCANFD_NCFG_NSJW(x)             (((x) & 0x1f) << 11)
 120 #define RCANFD_NCFG_NBRP(x)             (((x) & 0x3ff) << 0)
 121
 122 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 123 #define RCANFD_CCTR_CTME                BIT(24)
 124 #define RCANFD_CCTR_ERRD                BIT(23)
 125 #define RCANFD_CCTR_BOM_MASK            (0x3 << 21)
 126 #define RCANFD_CCTR_BOM_ISO             (0x0 << 21)
 127 #define RCANFD_CCTR_BOM_BENTRY          (0x1 << 21)
 128 #define RCANFD_CCTR_BOM_BEND            (0x2 << 21)
 129 #define RCANFD_CCTR_TDCVFIE             BIT(19)
 130 #define RCANFD_CCTR_SOCOIE              BIT(18)
 131 #define RCANFD_CCTR_EOCOIE              BIT(17)
 132 #define RCANFD_CCTR_TAIE                BIT(16)
 133 #define RCANFD_CCTR_ALIE                BIT(15)
 134 #define RCANFD_CCTR_BLIE                BIT(14)
 135 #define RCANFD_CCTR_OLIE                BIT(13)
 136 #define RCANFD_CCTR_BORIE               BIT(12)
 137 #define RCANFD_CCTR_BOEIE               BIT(11)
 138 #define RCANFD_CCTR_EPIE                BIT(10)
 139 #define RCANFD_CCTR_EWIE                BIT(9)
 140 #define RCANFD_CCTR_BEIE                BIT(8)
 141 #define RCANFD_CCTR_CSLPR               BIT(2)
 142 #define RCANFD_CCTR_CHMDC_MASK          (0x3)
 143 #define RCANFD_CCTR_CHDMC_COPM          (0x0)
 144 #define RCANFD_CCTR_CHDMC_CRESET        (0x1)
 145 #define RCANFD_CCTR_CHDMC_CHLT          (0x2)
 146
 147 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 148 #define RCANFD_CSTS_COMSTS              BIT(7)
 149 #define RCANFD_CSTS_RECSTS              BIT(6)
 150 #define RCANFD_CSTS_TRMSTS              BIT(5)
 151 #define RCANFD_CSTS_BOSTS               BIT(4)
 152 #define RCANFD_CSTS_EPSTS               BIT(3)
 153 #define RCANFD_CSTS_SLPSTS              BIT(2)
 154 #define RCANFD_CSTS_HLTSTS              BIT(1)
 155 #define RCANFD_CSTS_CRSTSTS             BIT(0)
 156
 157 #define RCANFD_CSTS_TECCNT(x)           (((x) >> 24) & 0xff)
 158 #define RCANFD_CSTS_RECCNT(x)           (((x) >> 16) & 0xff)
 159
 160 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 161 #define RCANFD_CERFL_ADERR              BIT(14)
 162 #define RCANFD_CERFL_B0ERR              BIT(13)
 163 #define RCANFD_CERFL_B1ERR              BIT(12)
 164 #define RCANFD_CERFL_CERR               BIT(11)
 165 #define RCANFD_CERFL_AERR               BIT(10)
 166 #define RCANFD_CERFL_FERR               BIT(9)
 167 #define RCANFD_CERFL_SERR               BIT(8)
 168 #define RCANFD_CERFL_ALF                BIT(7)
 169 #define RCANFD_CERFL_BLF                BIT(6)
 170 #define RCANFD_CERFL_OVLF               BIT(5)
 171 #define RCANFD_CERFL_BORF               BIT(4)
 172 #define RCANFD_CERFL_BOEF               BIT(3)
 173 #define RCANFD_CERFL_EPF                BIT(2)
 174 #define RCANFD_CERFL_EWF                BIT(1)
 175 #define RCANFD_CERFL_BEF                BIT(0)
 176
 177 #define RCANFD_CERFL_ERR(x)             ((x) & (0x7fff)) /* above bits 14:0 */
 178
 179 /* RSCFDnCFDCmDCFG */
 180 #define RCANFD_DCFG_DSJW(x)             (((x) & 0x7) << 24)
 181 #define RCANFD_DCFG_DTSEG2(x)           (((x) & 0x7) << 20)
 182 #define RCANFD_DCFG_DTSEG1(x)           (((x) & 0xf) << 16)
 183 #define RCANFD_DCFG_DBRP(x)             (((x) & 0xff) << 0)
 184
 185 /* RSCFDnCFDCmFDCFG */
 186 #define RCANFD_FDCFG_TDCE               BIT(9)
 187 #define RCANFD_FDCFG_TDCOC              BIT(8)
 188 #define RCANFD_FDCFG_TDCO(x)            (((x) & 0x7f) >> 16)
 189
 190 /* RSCFDnCFDRFCCx */
 191 #define RCANFD_RFCC_RFIM                BIT(12)
 192 #define RCANFD_RFCC_RFDC(x)             (((x) & 0x7) << 8)
 193 #define RCANFD_RFCC_RFPLS(x)            (((x) & 0x7) << 4)
 194 #define RCANFD_RFCC_RFIE                BIT(1)
 195 #define RCANFD_RFCC_RFE                 BIT(0)
 196
 197 /* RSCFDnCFDRFSTSx */
 198 #define RCANFD_RFSTS_RFIF               BIT(3)
 199 #define RCANFD_RFSTS_RFMLT              BIT(2)
 200 #define RCANFD_RFSTS_RFFLL              BIT(1)
 201 #define RCANFD_RFSTS_RFEMP              BIT(0)
 202
 203 /* RSCFDnCFDRFIDx */
 204 #define RCANFD_RFID_RFIDE               BIT(31)
 205 #define RCANFD_RFID_RFRTR               BIT(30)
 206
 207 /* RSCFDnCFDRFPTRx */
 208 #define RCANFD_RFPTR_RFDLC(x)           (((x) >> 28) & 0xf)
 209 #define RCANFD_RFPTR_RFPTR(x)           (((x) >> 16) & 0xfff)
 210 #define RCANFD_RFPTR_RFTS(x)            (((x) >> 0) & 0xffff)
 211
 212 /* RSCFDnCFDRFFDSTSx */
 213 #define RCANFD_RFFDSTS_RFFDF            BIT(2)
 214 #define RCANFD_RFFDSTS_RFBRS            BIT(1)
 215 #define RCANFD_RFFDSTS_RFESI            BIT(0)
 216
 217 /* Common FIFO bits */
 218
 219 /* RSCFDnCFDCFCCk */
 220 #define RCANFD_CFCC_CFTML(x)            (((x) & 0xf) << 20)
 221 #define RCANFD_CFCC_CFM(x)              (((x) & 0x3) << 16)
 222 #define RCANFD_CFCC_CFIM                BIT(12)
 223 #define RCANFD_CFCC_CFDC(x)             (((x) & 0x7) << 8)
 224 #define RCANFD_CFCC_CFPLS(x)            (((x) & 0x7) << 4)
 225 #define RCANFD_CFCC_CFTXIE              BIT(2)
 226 #define RCANFD_CFCC_CFE                 BIT(0)
 227
 228 /* RSCFDnCFDCFSTSk */
 229 #define RCANFD_CFSTS_CFMC(x)            (((x) >> 8) & 0xff)
 230 #define RCANFD_CFSTS_CFTXIF             BIT(4)
 231 #define RCANFD_CFSTS_CFMLT              BIT(2)
 232 #define RCANFD_CFSTS_CFFLL              BIT(1)
 233 #define RCANFD_CFSTS_CFEMP              BIT(0)
 234
 235 /* RSCFDnCFDCFIDk */
 236 #define RCANFD_CFID_CFIDE               BIT(31)
 237 #define RCANFD_CFID_CFRTR               BIT(30)
 238 #define RCANFD_CFID_CFID_MASK(x)        ((x) & 0x1fffffff)
 239
 240 /* RSCFDnCFDCFPTRk */
 241 #define RCANFD_CFPTR_CFDLC(x)           (((x) & 0xf) << 28)
 242 #define RCANFD_CFPTR_CFPTR(x)           (((x) & 0xfff) << 16)
 243 #define RCANFD_CFPTR_CFTS(x)            (((x) & 0xff) << 0)
 244
 245 /* RSCFDnCFDCFFDCSTSk */
 246 #define RCANFD_CFFDCSTS_CFFDF           BIT(2)
 247 #define RCANFD_CFFDCSTS_CFBRS           BIT(1)
 248 #define RCANFD_CFFDCSTS_CFESI           BIT(0)
 249
 250 /* This controller supports either Classical CAN only mode or CAN FD only mode.
 251  * These modes are supported in two separate set of register maps & names.
 252  * However, some of the register offsets are common for both modes. Those
 253  * offsets are listed below as Common registers.
 254  *
 255  * The CAN FD only mode specific registers & Classical CAN only mode specific
 256  * registers are listed separately. Their register names starts with
 257  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 258  */
 259
 260 /* Common registers */
 261
 262 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 263 #define RCANFD_CCFG(m)                  (0x0000 + (0x10 * (m)))
 264 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 265 #define RCANFD_CCTR(m)                  (0x0004 + (0x10 * (m)))
 266 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 267 #define RCANFD_CSTS(m)                  (0x0008 + (0x10 * (m)))
 268 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 269 #define RCANFD_CERFL(m)                 (0x000C + (0x10 * (m)))
 270
 271 /* RSCFDnCFDGCFG / RSCFDnGCFG */
 272 #define RCANFD_GCFG                     (0x0084)
 273 /* RSCFDnCFDGCTR / RSCFDnGCTR */
 274 #define RCANFD_GCTR                     (0x0088)
 275 /* RSCFDnCFDGCTS / RSCFDnGCTS */
 276 #define RCANFD_GSTS                     (0x008c)
 277 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 278 #define RCANFD_GERFL                    (0x0090)
 279 /* RSCFDnCFDGTSC / RSCFDnGTSC */
 280 #define RCANFD_GTSC                     (0x0094)
 281 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 282 #define RCANFD_GAFLECTR                 (0x0098)
 283 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
 284 #define RCANFD_GAFLCFG0                 (0x009c)
 285 /* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
 286 #define RCANFD_GAFLCFG1                 (0x00a0)
 287 /* RSCFDnCFDRMNB / RSCFDnRMNB */
 288 #define RCANFD_RMNB                     (0x00a4)
 289 /* RSCFDnCFDRMND / RSCFDnRMND */
 290 #define RCANFD_RMND(y)                  (0x00a8 + (0x04 * (y)))
 291
 292 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 293 #define RCANFD_RFCC(x)                  (0x00b8 + (0x04 * (x)))
 294 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 295 #define RCANFD_RFSTS(x)                 (0x00d8 + (0x04 * (x)))
 296 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 297 #define RCANFD_RFPCTR(x)                (0x00f8 + (0x04 * (x)))
 298
 299 /* Common FIFO Control registers */
 300
 301 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 302 #define RCANFD_CFCC(ch, idx)            (0x0118 + (0x0c * (ch)) + \
 303                                          (0x04 * (idx)))
 304 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 305 #define RCANFD_CFSTS(ch, idx)           (0x0178 + (0x0c * (ch)) + \
 306                                          (0x04 * (idx)))
 307 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 308 #define RCANFD_CFPCTR(ch, idx)          (0x01d8 + (0x0c * (ch)) + \
 309                                          (0x04 * (idx)))
 310
 311 /* RSCFDnCFDFESTS / RSCFDnFESTS */
 312 #define RCANFD_FESTS                    (0x0238)
 313 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 314 #define RCANFD_FFSTS                    (0x023c)
 315 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 316 #define RCANFD_FMSTS                    (0x0240)
 317 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 318 #define RCANFD_RFISTS                   (0x0244)
 319 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 320 #define RCANFD_CFRISTS                  (0x0248)
 321 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 322 #define RCANFD_CFTISTS                  (0x024c)
 323
 324 /* RSCFDnCFDTMCp / RSCFDnTMCp */
 325 #define RCANFD_TMC(p)                   (0x0250 + (0x01 * (p)))
 326 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 327 #define RCANFD_TMSTS(p)                 (0x02d0 + (0x01 * (p)))
 328
 329 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 330 #define RCANFD_TMTRSTS(y)               (0x0350 + (0x04 * (y)))
 331 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 332 #define RCANFD_TMTARSTS(y)              (0x0360 + (0x04 * (y)))
 333 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 334 #define RCANFD_TMTCSTS(y)               (0x0370 + (0x04 * (y)))
 335 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 336 #define RCANFD_TMTASTS(y)               (0x0380 + (0x04 * (y)))
 337 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 338 #define RCANFD_TMIEC(y)                 (0x0390 + (0x04 * (y)))
 339
 340 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 341 #define RCANFD_TXQCC(m)                 (0x03a0 + (0x04 * (m)))
 342 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 343 #define RCANFD_TXQSTS(m)                (0x03c0 + (0x04 * (m)))
 344 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 345 #define RCANFD_TXQPCTR(m)               (0x03e0 + (0x04 * (m)))
 346
 347 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 348 #define RCANFD_THLCC(m)                 (0x0400 + (0x04 * (m)))
 349 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 350 #define RCANFD_THLSTS(m)                (0x0420 + (0x04 * (m)))
 351 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 352 #define RCANFD_THLPCTR(m)               (0x0440 + (0x04 * (m)))
 353
 354 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 355 #define RCANFD_GTINTSTS0                (0x0460)
 356 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 357 #define RCANFD_GTINTSTS1                (0x0464)
 358 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 359 #define RCANFD_GTSTCFG                  (0x0468)
 360 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 361 #define RCANFD_GTSTCTR                  (0x046c)
 362 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 363 #define RCANFD_GLOCKK                   (0x047c)
 364 /* RSCFDnCFDGRMCFG */
 365 #define RCANFD_GRMCFG                   (0x04fc)
 366
 367 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 368 #define RCANFD_GAFLID(offset, j)        ((offset) + (0x10 * (j)))
 369 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 370 #define RCANFD_GAFLM(offset, j)         ((offset) + 0x04 + (0x10 * (j)))
 371 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 372 #define RCANFD_GAFLP0(offset, j)        ((offset) + 0x08 + (0x10 * (j)))
 373 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 374 #define RCANFD_GAFLP1(offset, j)        ((offset) + 0x0c + (0x10 * (j)))
 375
 376 /* Classical CAN only mode register map */
 377
 378 /* RSCFDnGAFLXXXj offset */
 379 #define RCANFD_C_GAFL_OFFSET            (0x0500)
 380
 381 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 382 #define RCANFD_C_RMID(q)                (0x0600 + (0x10 * (q)))
 383 #define RCANFD_C_RMPTR(q)               (0x0604 + (0x10 * (q)))
 384 #define RCANFD_C_RMDF0(q)               (0x0608 + (0x10 * (q)))
 385 #define RCANFD_C_RMDF1(q)               (0x060c + (0x10 * (q)))
 386
 387 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 388 #define RCANFD_C_RFOFFSET               (0x0e00)
 389 #define RCANFD_C_RFID(x)                (RCANFD_C_RFOFFSET + (0x10 * (x)))
 390 #define RCANFD_C_RFPTR(x)               (RCANFD_C_RFOFFSET + 0x04 + \
 391                                          (0x10 * (x)))
 392 #define RCANFD_C_RFDF(x, df)            (RCANFD_C_RFOFFSET + 0x08 + \
 393                                          (0x10 * (x)) + (0x04 * (df)))
 394
 395 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 396 #define RCANFD_C_CFOFFSET               (0x0e80)
 397 #define RCANFD_C_CFID(ch, idx)          (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
 398                                          (0x10 * (idx)))
 399 #define RCANFD_C_CFPTR(ch, idx)         (RCANFD_C_CFOFFSET + 0x04 + \
 400                                          (0x30 * (ch)) + (0x10 * (idx)))
 401 #define RCANFD_C_CFDF(ch, idx, df)      (RCANFD_C_CFOFFSET + 0x08 + \
 402                                          (0x30 * (ch)) + (0x10 * (idx)) + \
 403                                          (0x04 * (df)))
 404
 405 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 406 #define RCANFD_C_TMID(p)                (0x1000 + (0x10 * (p)))
 407 #define RCANFD_C_TMPTR(p)               (0x1004 + (0x10 * (p)))
 408 #define RCANFD_C_TMDF0(p)               (0x1008 + (0x10 * (p)))
 409 #define RCANFD_C_TMDF1(p)               (0x100c + (0x10 * (p)))
 410
 411 /* RSCFDnTHLACCm */
 412 #define RCANFD_C_THLACC(m)              (0x1800 + (0x04 * (m)))
 413 /* RSCFDnRPGACCr */
 414 #define RCANFD_C_RPGACC(r)              (0x1900 + (0x04 * (r)))
 415
 416 /* CAN FD mode specific regsiter map */
 417
 418 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 419 #define RCANFD_F_DCFG(m)                (0x0500 + (0x20 * (m)))
 420 #define RCANFD_F_CFDCFG(m)              (0x0504 + (0x20 * (m)))
 421 #define RCANFD_F_CFDCTR(m)              (0x0508 + (0x20 * (m)))
 422 #define RCANFD_F_CFDSTS(m)              (0x050c + (0x20 * (m)))
 423 #define RCANFD_F_CFDCRC(m)              (0x0510 + (0x20 * (m)))
 424
 425 /* RSCFDnCFDGAFLXXXj offset */
 426 #define RCANFD_F_GAFL_OFFSET            (0x1000)
 427
 428 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 429 #define RCANFD_F_RMID(q)                (0x2000 + (0x20 * (q)))
 430 #define RCANFD_F_RMPTR(q)               (0x2004 + (0x20 * (q)))
 431 #define RCANFD_F_RMFDSTS(q)             (0x2008 + (0x20 * (q)))
 432 #define RCANFD_F_RMDF(q, b)             (0x200c + (0x04 * (b)) + (0x20 * (q)))
 433
 434 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 435 #define RCANFD_F_RFOFFSET               (0x3000)
 436 #define RCANFD_F_RFID(x)                (RCANFD_F_RFOFFSET + (0x80 * (x)))
 437 #define RCANFD_F_RFPTR(x)               (RCANFD_F_RFOFFSET + 0x04 + \
 438                                          (0x80 * (x)))
 439 #define RCANFD_F_RFFDSTS(x)             (RCANFD_F_RFOFFSET + 0x08 + \
 440                                          (0x80 * (x)))
 441 #define RCANFD_F_RFDF(x, df)            (RCANFD_F_RFOFFSET + 0x0c + \
 442                                          (0x80 * (x)) + (0x04 * (df)))
 443
 444 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 445 #define RCANFD_F_CFOFFSET               (0x3400)
 446 #define RCANFD_F_CFID(ch, idx)          (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
 447                                          (0x80 * (idx)))
 448 #define RCANFD_F_CFPTR(ch, idx)         (RCANFD_F_CFOFFSET + 0x04 + \
 449                                          (0x180 * (ch)) + (0x80 * (idx)))
 450 #define RCANFD_F_CFFDCSTS(ch, idx)      (RCANFD_F_CFOFFSET + 0x08 + \
 451                                          (0x180 * (ch)) + (0x80 * (idx)))
 452 #define RCANFD_F_CFDF(ch, idx, df)      (RCANFD_F_CFOFFSET + 0x0c + \
 453                                          (0x180 * (ch)) + (0x80 * (idx)) + \
 454                                          (0x04 * (df)))
 455
 456 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 457 #define RCANFD_F_TMID(p)                (0x4000 + (0x20 * (p)))
 458 #define RCANFD_F_TMPTR(p)               (0x4004 + (0x20 * (p)))
 459 #define RCANFD_F_TMFDCTR(p)             (0x4008 + (0x20 * (p)))
 460 #define RCANFD_F_TMDF(p, b)             (0x400c + (0x20 * (p)) + (0x04 * (b)))
 461
 462 /* RSCFDnCFDTHLACCm */
 463 #define RCANFD_F_THLACC(m)              (0x6000 + (0x04 * (m)))
 464 /* RSCFDnCFDRPGACCr */
 465 #define RCANFD_F_RPGACC(r)              (0x6400 + (0x04 * (r)))
 466
 467 /* Constants */
 468 #define RCANFD_FIFO_DEPTH               8       /* Tx FIFO depth */
 469 #define RCANFD_NAPI_WEIGHT              8       /* Rx poll quota */
 470
 471 #define RCANFD_NUM_CHANNELS             2       /* Two channels max */
 472 #define RCANFD_CHANNELS_MASK            BIT((RCANFD_NUM_CHANNELS) - 1)
 473
 474 #define RCANFD_GAFL_PAGENUM(entry)      ((entry) / 16)
 475 #define RCANFD_CHANNEL_NUMRULES         1       /* only one rule per channel */
 476
 477 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 478  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 479  * number is added to RFFIFO index.
 480  */
 481 #define RCANFD_RFFIFO_IDX               0
 482
 483 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 484  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 485  */
 486 #define RCANFD_CFFIFO_IDX               0
 487
 488 /* fCAN clock select register settings */
 489 enum rcar_canfd_fcanclk {
 490         RCANFD_CANFDCLK = 0,            /* CANFD clock */
 491         RCANFD_EXTCLK,                  /* Externally input clock */
 492 };
 493
 494 struct rcar_canfd_global;
 495
 496 /* Channel priv data */
 497 struct rcar_canfd_channel {
 498         struct can_priv can;                    /* Must be the first member */
 499         struct net_device *ndev;
 500         struct rcar_canfd_global *gpriv;        /* Controller reference */
 501         void __iomem *base;                     /* Register base address */
 502         struct napi_struct napi;
 503         u8  tx_len[RCANFD_FIFO_DEPTH];          /* For net stats */
 504         u32 tx_head;                            /* Incremented on xmit */
 505         u32 tx_tail;                            /* Incremented on xmit done */
 506         u32 channel;                            /* Channel number */
 507         spinlock_t tx_lock;                     /* To protect tx path */
 508 };
 509
 510 /* Global priv data */
 511 struct rcar_canfd_global {
 512         struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 513         void __iomem *base;             /* Register base address */
 514         struct platform_device *pdev;   /* Respective platform device */
 515         struct clk *clkp;               /* Peripheral clock */
 516         struct clk *can_clk;            /* fCAN clock */
 517         enum rcar_canfd_fcanclk fcan;   /* CANFD or Ext clock */
 518         unsigned long channels_mask;    /* Enabled channels mask */
 519         bool fdmode;                    /* CAN FD or Classical CAN only mode */
 520 };
 521
 522 /* CAN FD mode nominal rate constants */
 523 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 524         .name = RCANFD_DRV_NAME,
 525         .tseg1_min = 2,
 526         .tseg1_max = 128,
 527         .tseg2_min = 2,
 528         .tseg2_max = 32,
 529         .sjw_max = 32,
 530         .brp_min = 1,
 531         .brp_max = 1024,
 532         .brp_inc = 1,
 533 };
 534
 535 /* CAN FD mode data rate constants */
 536 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 537         .name = RCANFD_DRV_NAME,
 538         .tseg1_min = 2,
 539         .tseg1_max = 16,
 540         .tseg2_min = 2,
 541         .tseg2_max = 8,
 542         .sjw_max = 8,
 543         .brp_min = 1,
 544         .brp_max = 256,
 545         .brp_inc = 1,
 546 };
 547
 548 /* Classical CAN mode bitrate constants */
 549 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 550         .name = RCANFD_DRV_NAME,
 551         .tseg1_min = 4,
 552         .tseg1_max = 16,
 553         .tseg2_min = 2,
 554         .tseg2_max = 8,
 555         .sjw_max = 4,
 556         .brp_min = 1,
 557         .brp_max = 1024,
 558         .brp_inc = 1,
 559 };
 560
 561 /* Helper functions */
 562 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 563 {
 564         u32 data = readl(reg);
 565
 566         data &= ~mask;
 567         data |= (val & mask);
 568         writel(data, reg);
 569 }
 570
 571 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 572 {
 573         return readl(base + (offset));
 574 }
 575
 576 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 577 {
 578         writel(val, base + (offset));
 579 }
 580
 581 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 582 {
 583         rcar_canfd_update(val, val, base + (reg));
 584 }
 585
 586 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 587 {
 588         rcar_canfd_update(val, 0, base + (reg));
 589 }
 590
 591 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 592                                   u32 mask, u32 val)
 593 {
 594         rcar_canfd_update(mask, val, base + (reg));
 595 }
 596
 597 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 598                                 struct canfd_frame *cf, u32 off)
 599 {
 600         u32 i, lwords;
 601
 602         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 603         for (i = 0; i < lwords; i++)
 604                 *((u32 *)cf->data + i) =
 605                         rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 606 }
 607
 608 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 609                                 struct canfd_frame *cf, u32 off)
 610 {
 611         u32 i, lwords;
 612
 613         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 614         for (i = 0; i < lwords; i++)
 615                 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 616                                  *((u32 *)cf->data + i));
 617 }
 618
 619 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 620 {
 621         u32 i;
 622
 623         for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 624                 can_free_echo_skb(ndev, i);
 625 }
 626
 627 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 628 {
 629         u32 sts, ch;
 630         int err;
 631
 632         /* Check RAMINIT flag as CAN RAM initialization takes place
 633          * after the MCU reset
 634          */
 635         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 636                                  !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 637         if (err) {
 638                 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 639                 return err;
 640         }
 641
 642         /* Transition to Global Reset mode */
 643         rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 644         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 645                               RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 646
 647         /* Ensure Global reset mode */
 648         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 649                                  (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 650         if (err) {
 651                 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 652                 return err;
 653         }
 654
 655         /* Reset Global error flags */
 656         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 657
 658         /* Set the controller into appropriate mode */
 659         if (gpriv->fdmode)
 660                 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 661                                    RCANFD_GRMCFG_RCMC);
 662         else
 663                 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 664                                      RCANFD_GRMCFG_RCMC);
 665
 666         /* Transition all Channels to reset mode */
 667         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 668                 rcar_canfd_clear_bit(gpriv->base,
 669                                      RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 670
 671                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 672                                       RCANFD_CCTR_CHMDC_MASK,
 673                                       RCANFD_CCTR_CHDMC_CRESET);
 674
 675                 /* Ensure Channel reset mode */
 676                 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 677                                          (sts & RCANFD_CSTS_CRSTSTS),
 678                                          2, 500000);
 679                 if (err) {
 680                         dev_dbg(&gpriv->pdev->dev,
 681                                 "channel %u reset failed\n", ch);
 682                         return err;
 683                 }
 684         }
 685         return 0;
 686 }
 687
 688 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 689 {
 690         u32 cfg, ch;
 691
 692         /* Global configuration settings */
 693
 694         /* ECC Error flag Enable */
 695         cfg = RCANFD_GCFG_EEFE;
 696
 697         if (gpriv->fdmode)
 698                 /* Truncate payload to configured message size RFPLS */
 699                 cfg |= RCANFD_GCFG_CMPOC;
 700
 701         /* Set External Clock if selected */
 702         if (gpriv->fcan != RCANFD_CANFDCLK)
 703                 cfg |= RCANFD_GCFG_DCS;
 704
 705         rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 706
 707         /* Channel configuration settings */
 708         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 709                 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 710                                    RCANFD_CCTR_ERRD);
 711                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 712                                       RCANFD_CCTR_BOM_MASK,
 713                                       RCANFD_CCTR_BOM_BENTRY);
 714         }
 715 }
 716
 717 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 718                                            u32 ch)
 719 {
 720         u32 cfg;
 721         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 722         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 723
 724         if (ch == 0) {
 725                 start = 0; /* Channel 0 always starts from 0th rule */
 726         } else {
 727                 /* Get number of Channel 0 rules and adjust */
 728                 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
 729                 start = RCANFD_GAFLCFG_GETRNC(0, cfg);
 730         }
 731
 732         /* Enable write access to entry */
 733         page = RCANFD_GAFL_PAGENUM(start);
 734         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 735                            (RCANFD_GAFLECTR_AFLPN(page) |
 736                             RCANFD_GAFLECTR_AFLDAE));
 737
 738         /* Write number of rules for channel */
 739         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
 740                            RCANFD_GAFLCFG_SETRNC(ch, num_rules));
 741         if (gpriv->fdmode)
 742                 offset = RCANFD_F_GAFL_OFFSET;
 743         else
 744                 offset = RCANFD_C_GAFL_OFFSET;
 745
 746         /* Accept all IDs */
 747         rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 748         /* IDE or RTR is not considered for matching */
 749         rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 750         /* Any data length accepted */
 751         rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 752         /* Place the msg in corresponding Rx FIFO entry */
 753         rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
 754                          RCANFD_GAFLP1_GAFLFDP(ridx));
 755
 756         /* Disable write access to page */
 757         rcar_canfd_clear_bit(gpriv->base,
 758                              RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 759 }
 760
 761 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 762 {
 763         /* Rx FIFO is used for reception */
 764         u32 cfg;
 765         u16 rfdc, rfpls;
 766
 767         /* Select Rx FIFO based on channel */
 768         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 769
 770         rfdc = 2;               /* b010 - 8 messages Rx FIFO depth */
 771         if (gpriv->fdmode)
 772                 rfpls = 7;      /* b111 - Max 64 bytes payload */
 773         else
 774                 rfpls = 0;      /* b000 - Max 8 bytes payload */
 775
 776         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 777                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 778         rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
 779 }
 780
 781 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 782 {
 783         /* Tx/Rx(Common) FIFO configured in Tx mode is
 784          * used for transmission
 785          *
 786          * Each channel has 3 Common FIFO dedicated to them.
 787          * Use the 1st (index 0) out of 3
 788          */
 789         u32 cfg;
 790         u16 cftml, cfm, cfdc, cfpls;
 791
 792         cftml = 0;              /* 0th buffer */
 793         cfm = 1;                /* b01 - Transmit mode */
 794         cfdc = 2;               /* b010 - 8 messages Tx FIFO depth */
 795         if (gpriv->fdmode)
 796                 cfpls = 7;      /* b111 - Max 64 bytes payload */
 797         else
 798                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 799
 800         cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
 801                 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
 802                 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 803         rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
 804
 805         if (gpriv->fdmode)
 806                 /* Clear FD mode specific control/status register */
 807                 rcar_canfd_write(gpriv->base,
 808                                  RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
 809 }
 810
 811 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 812 {
 813         u32 ctr;
 814
 815         /* Clear any stray error interrupt flags */
 816         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 817
 818         /* Global interrupts setup */
 819         ctr = RCANFD_GCTR_MEIE;
 820         if (gpriv->fdmode)
 821                 ctr |= RCANFD_GCTR_CFMPOFIE;
 822
 823         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 824 }
 825
 826 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 827                                                  *gpriv)
 828 {
 829         /* Disable all interrupts */
 830         rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 831
 832         /* Clear any stray error interrupt flags */
 833         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 834 }
 835
 836 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 837                                                  *priv)
 838 {
 839         u32 ctr, ch = priv->channel;
 840
 841         /* Clear any stray error flags */
 842         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 843
 844         /* Channel interrupts setup */
 845         ctr = (RCANFD_CCTR_TAIE |
 846                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 847                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 848                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 849                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 850         rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 851 }
 852
 853 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 854                                                   *priv)
 855 {
 856         u32 ctr, ch = priv->channel;
 857
 858         ctr = (RCANFD_CCTR_TAIE |
 859                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 860                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 861                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 862                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 863         rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 864
 865         /* Clear any stray error flags */
 866         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 867 }
 868
 869 static void rcar_canfd_global_error(struct net_device *ndev)
 870 {
 871         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 872         struct rcar_canfd_global *gpriv = priv->gpriv;
 873         struct net_device_stats *stats = &ndev->stats;
 874         u32 ch = priv->channel;
 875         u32 gerfl, sts;
 876         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 877
 878         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 879         if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
 880                 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
 881                 stats->tx_dropped++;
 882         }
 883         if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
 884                 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
 885                 stats->tx_dropped++;
 886         }
 887         if (gerfl & RCANFD_GERFL_MES) {
 888                 sts = rcar_canfd_read(priv->base,
 889                                       RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
 890                 if (sts & RCANFD_CFSTS_CFMLT) {
 891                         netdev_dbg(ndev, "Tx Message Lost flag\n");
 892                         stats->tx_dropped++;
 893                         rcar_canfd_write(priv->base,
 894                                          RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
 895                                          sts & ~RCANFD_CFSTS_CFMLT);
 896                 }
 897
 898                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
 899                 if (sts & RCANFD_RFSTS_RFMLT) {
 900                         netdev_dbg(ndev, "Rx Message Lost flag\n");
 901                         stats->rx_dropped++;
 902                         rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
 903                                          sts & ~RCANFD_RFSTS_RFMLT);
 904                 }
 905         }
 906         if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 907                 /* Message Lost flag will be set for respective channel
 908                  * when this condition happens with counters and flags
 909                  * already updated.
 910                  */
 911                 netdev_dbg(ndev, "global payload overflow interrupt\n");
 912         }
 913
 914         /* Clear all global error interrupts. Only affected channels bits
 915          * get cleared
 916          */
 917         rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 918 }
 919
 920 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 921                              u16 txerr, u16 rxerr)
 922 {
 923         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 924         struct net_device_stats *stats = &ndev->stats;
 925         struct can_frame *cf;
 926         struct sk_buff *skb;
 927         u32 ch = priv->channel;
 928
 929         netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
 930
 931         /* Propagate the error condition to the CAN stack */
 932         skb = alloc_can_err_skb(ndev, &cf);
 933         if (!skb) {
 934                 stats->rx_dropped++;
 935                 return;
 936         }
 937
 938         /* Channel error interrupts */
 939         if (cerfl & RCANFD_CERFL_BEF) {
 940                 netdev_dbg(ndev, "Bus error\n");
 941                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 942                 cf->data[2] = CAN_ERR_PROT_UNSPEC;
 943                 priv->can.can_stats.bus_error++;
 944         }
 945         if (cerfl & RCANFD_CERFL_ADERR) {
 946                 netdev_dbg(ndev, "ACK Delimiter Error\n");
 947                 stats->tx_errors++;
 948                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
 949         }
 950         if (cerfl & RCANFD_CERFL_B0ERR) {
 951                 netdev_dbg(ndev, "Bit Error (dominant)\n");
 952                 stats->tx_errors++;
 953                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 954         }
 955         if (cerfl & RCANFD_CERFL_B1ERR) {
 956                 netdev_dbg(ndev, "Bit Error (recessive)\n");
 957                 stats->tx_errors++;
 958                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 959         }
 960         if (cerfl & RCANFD_CERFL_CERR) {
 961                 netdev_dbg(ndev, "CRC Error\n");
 962                 stats->rx_errors++;
 963                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 964         }
 965         if (cerfl & RCANFD_CERFL_AERR) {
 966                 netdev_dbg(ndev, "ACK Error\n");
 967                 stats->tx_errors++;
 968                 cf->can_id |= CAN_ERR_ACK;
 969                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 970         }
 971         if (cerfl & RCANFD_CERFL_FERR) {
 972                 netdev_dbg(ndev, "Form Error\n");
 973                 stats->rx_errors++;
 974                 cf->data[2] |= CAN_ERR_PROT_FORM;
 975         }
 976         if (cerfl & RCANFD_CERFL_SERR) {
 977                 netdev_dbg(ndev, "Stuff Error\n");
 978                 stats->rx_errors++;
 979                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 980         }
 981         if (cerfl & RCANFD_CERFL_ALF) {
 982                 netdev_dbg(ndev, "Arbitration lost Error\n");
 983                 priv->can.can_stats.arbitration_lost++;
 984                 cf->can_id |= CAN_ERR_LOSTARB;
 985                 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
 986         }
 987         if (cerfl & RCANFD_CERFL_BLF) {
 988                 netdev_dbg(ndev, "Bus Lock Error\n");
 989                 stats->rx_errors++;
 990                 cf->can_id |= CAN_ERR_BUSERROR;
 991         }
 992         if (cerfl & RCANFD_CERFL_EWF) {
 993                 netdev_dbg(ndev, "Error warning interrupt\n");
 994                 priv->can.state = CAN_STATE_ERROR_WARNING;
 995                 priv->can.can_stats.error_warning++;
 996                 cf->can_id |= CAN_ERR_CRTL;
 997                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
 998                         CAN_ERR_CRTL_RX_WARNING;
 999                 cf->data[6] = txerr;
1000                 cf->data[7] = rxerr;
1001         }
1002         if (cerfl & RCANFD_CERFL_EPF) {
1003                 netdev_dbg(ndev, "Error passive interrupt\n");
1004                 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1005                 priv->can.can_stats.error_passive++;
1006                 cf->can_id |= CAN_ERR_CRTL;
1007                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1008                         CAN_ERR_CRTL_RX_PASSIVE;
1009                 cf->data[6] = txerr;
1010                 cf->data[7] = rxerr;
1011         }
1012         if (cerfl & RCANFD_CERFL_BOEF) {
1013                 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1014                 rcar_canfd_tx_failure_cleanup(ndev);
1015                 priv->can.state = CAN_STATE_BUS_OFF;
1016                 priv->can.can_stats.bus_off++;
1017                 can_bus_off(ndev);
1018                 cf->can_id |= CAN_ERR_BUSOFF;
1019         }
1020         if (cerfl & RCANFD_CERFL_OVLF) {
1021                 netdev_dbg(ndev,
1022                            "Overload Frame Transmission error interrupt\n");
1023                 stats->tx_errors++;
1024                 cf->can_id |= CAN_ERR_PROT;
1025                 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1026         }
1027
1028         /* Clear channel error interrupts that are handled */
1029         rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1030                          RCANFD_CERFL_ERR(~cerfl));
1031         stats->rx_packets++;
1032         stats->rx_bytes += cf->can_dlc;
1033         netif_rx(skb);
1034 }
1035
1036 static void rcar_canfd_tx_done(struct net_device *ndev)
1037 {
1038         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1039         struct net_device_stats *stats = &ndev->stats;
1040         u32 sts;
1041         unsigned long flags;
1042         u32 ch = priv->channel;
1043
1044         do {
1045                 u8 unsent, sent;
1046
1047                 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1048                 stats->tx_packets++;
1049                 stats->tx_bytes += priv->tx_len[sent];
1050                 priv->tx_len[sent] = 0;
1051                 can_get_echo_skb(ndev, sent);
1052
1053                 spin_lock_irqsave(&priv->tx_lock, flags);
1054                 priv->tx_tail++;
1055                 sts = rcar_canfd_read(priv->base,
1056                                       RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1057                 unsent = RCANFD_CFSTS_CFMC(sts);
1058
1059                 /* Wake producer only when there is room */
1060                 if (unsent != RCANFD_FIFO_DEPTH)
1061                         netif_wake_queue(ndev);
1062
1063                 if (priv->tx_head - priv->tx_tail <= unsent) {
1064                         spin_unlock_irqrestore(&priv->tx_lock, flags);
1065                         break;
1066                 }
1067                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1068
1069         } while (1);
1070
1071         /* Clear interrupt */
1072         rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1073                          sts & ~RCANFD_CFSTS_CFTXIF);
1074         can_led_event(ndev, CAN_LED_EVENT_TX);
1075 }
1076
1077 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1078 {
1079         struct rcar_canfd_global *gpriv = dev_id;
1080         struct net_device *ndev;
1081         struct rcar_canfd_channel *priv;
1082         u32 sts, cc, gerfl;
1083         u32 ch, ridx;
1084
1085         /* Global error interrupts still indicate a condition specific
1086          * to a channel. RxFIFO interrupt is a global interrupt.
1087          */
1088         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1089                 priv = gpriv->ch[ch];
1090                 ndev = priv->ndev;
1091                 ridx = ch + RCANFD_RFFIFO_IDX;
1092
1093                 /* Global error interrupts */
1094                 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1095                 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1096                         rcar_canfd_global_error(ndev);
1097
1098                 /* Handle Rx interrupts */
1099                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1100                 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(ridx));
1101                 if (likely(sts & RCANFD_RFSTS_RFIF &&
1102                            cc & RCANFD_RFCC_RFIE)) {
1103                         if (napi_schedule_prep(&priv->napi)) {
1104                                 /* Disable Rx FIFO interrupts */
1105                                 rcar_canfd_clear_bit(priv->base,
1106                                                      RCANFD_RFCC(ridx),
1107                                                      RCANFD_RFCC_RFIE);
1108                                 __napi_schedule(&priv->napi);
1109                         }
1110                 }
1111         }
1112         return IRQ_HANDLED;
1113 }
1114
1115 static void rcar_canfd_state_change(struct net_device *ndev,
1116                                     u16 txerr, u16 rxerr)
1117 {
1118         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1119         struct net_device_stats *stats = &ndev->stats;
1120         enum can_state rx_state, tx_state, state = priv->can.state;
1121         struct can_frame *cf;
1122         struct sk_buff *skb;
1123
1124         /* Handle transition from error to normal states */
1125         if (txerr < 96 && rxerr < 96)
1126                 state = CAN_STATE_ERROR_ACTIVE;
1127         else if (txerr < 128 && rxerr < 128)
1128                 state = CAN_STATE_ERROR_WARNING;
1129
1130         if (state != priv->can.state) {
1131                 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1132                            state, priv->can.state, txerr, rxerr);
1133                 skb = alloc_can_err_skb(ndev, &cf);
1134                 if (!skb) {
1135                         stats->rx_dropped++;
1136                         return;
1137                 }
1138                 tx_state = txerr >= rxerr ? state : 0;
1139                 rx_state = txerr <= rxerr ? state : 0;
1140
1141                 can_change_state(ndev, cf, tx_state, rx_state);
1142                 stats->rx_packets++;
1143                 stats->rx_bytes += cf->can_dlc;
1144                 netif_rx(skb);
1145         }
1146 }
1147
1148 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1149 {
1150         struct rcar_canfd_global *gpriv = dev_id;
1151         struct net_device *ndev;
1152         struct rcar_canfd_channel *priv;
1153         u32 sts, ch, cerfl;
1154         u16 txerr, rxerr;
1155
1156         /* Common FIFO is a per channel resource */
1157         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1158                 priv = gpriv->ch[ch];
1159                 ndev = priv->ndev;
1160
1161                 /* Channel error interrupts */
1162                 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1163                 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1164                 txerr = RCANFD_CSTS_TECCNT(sts);
1165                 rxerr = RCANFD_CSTS_RECCNT(sts);
1166                 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1167                         rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1168
1169                 /* Handle state change to lower states */
1170                 if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
1171                              (priv->can.state != CAN_STATE_BUS_OFF)))
1172                         rcar_canfd_state_change(ndev, txerr, rxerr);
1173
1174                 /* Handle Tx interrupts */
1175                 sts = rcar_canfd_read(priv->base,
1176                                       RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1177                 if (likely(sts & RCANFD_CFSTS_CFTXIF))
1178                         rcar_canfd_tx_done(ndev);
1179         }
1180         return IRQ_HANDLED;
1181 }
1182
1183 static void rcar_canfd_set_bittiming(struct net_device *dev)
1184 {
1185         struct rcar_canfd_channel *priv = netdev_priv(dev);
1186         const struct can_bittiming *bt = &priv->can.bittiming;
1187         const struct can_bittiming *dbt = &priv->can.data_bittiming;
1188         u16 brp, sjw, tseg1, tseg2;
1189         u32 cfg;
1190         u32 ch = priv->channel;
1191
1192         /* Nominal bit timing settings */
1193         brp = bt->brp - 1;
1194         sjw = bt->sjw - 1;
1195         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1196         tseg2 = bt->phase_seg2 - 1;
1197
1198         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1199                 /* CAN FD only mode */
1200                 cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1201                        RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1202
1203                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1204                 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1205                            brp, sjw, tseg1, tseg2);
1206
1207                 /* Data bit timing settings */
1208                 brp = dbt->brp - 1;
1209                 sjw = dbt->sjw - 1;
1210                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1211                 tseg2 = dbt->phase_seg2 - 1;
1212
1213                 cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1214                        RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1215
1216                 rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1217                 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1218                            brp, sjw, tseg1, tseg2);
1219         } else {
1220                 /* Classical CAN only mode */
1221                 cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1222                         RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
1223
1224                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1225                 netdev_dbg(priv->ndev,
1226                            "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1227                            brp, sjw, tseg1, tseg2);
1228         }
1229 }
1230
1231 static int rcar_canfd_start(struct net_device *ndev)
1232 {
1233         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1234         int err = -EOPNOTSUPP;
1235         u32 sts, ch = priv->channel;
1236         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1237
1238         rcar_canfd_set_bittiming(ndev);
1239
1240         rcar_canfd_enable_channel_interrupts(priv);
1241
1242         /* Set channel to Operational mode */
1243         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1244                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1245
1246         /* Verify channel mode change */
1247         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1248                                  (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1249         if (err) {
1250                 netdev_err(ndev, "channel %u communication state failed\n", ch);
1251                 goto fail_mode_change;
1252         }
1253
1254         /* Enable Common & Rx FIFO */
1255         rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1256                            RCANFD_CFCC_CFE);
1257         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1258
1259         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1260         return 0;
1261
1262 fail_mode_change:
1263         rcar_canfd_disable_channel_interrupts(priv);
1264         return err;
1265 }
1266
1267 static int rcar_canfd_open(struct net_device *ndev)
1268 {
1269         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1270         struct rcar_canfd_global *gpriv = priv->gpriv;
1271         int err;
1272
1273         /* Peripheral clock is already enabled in probe */
1274         err = clk_prepare_enable(gpriv->can_clk);
1275         if (err) {
1276                 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1277                 goto out_clock;
1278         }
1279
1280         err = open_candev(ndev);
1281         if (err) {
1282                 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1283                 goto out_can_clock;
1284         }
1285
1286         napi_enable(&priv->napi);
1287         err = rcar_canfd_start(ndev);
1288         if (err)
1289                 goto out_close;
1290         netif_start_queue(ndev);
1291         can_led_event(ndev, CAN_LED_EVENT_OPEN);
1292         return 0;
1293 out_close:
1294         napi_disable(&priv->napi);
1295         close_candev(ndev);
1296 out_can_clock:
1297         clk_disable_unprepare(gpriv->can_clk);
1298 out_clock:
1299         return err;
1300 }
1301
1302 static void rcar_canfd_stop(struct net_device *ndev)
1303 {
1304         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1305         int err;
1306         u32 sts, ch = priv->channel;
1307         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1308
1309         /* Transition to channel reset mode  */
1310         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1311                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1312
1313         /* Check Channel reset mode */
1314         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1315                                  (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1316         if (err)
1317                 netdev_err(ndev, "channel %u reset failed\n", ch);
1318
1319         rcar_canfd_disable_channel_interrupts(priv);
1320
1321         /* Disable Common & Rx FIFO */
1322         rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1323                              RCANFD_CFCC_CFE);
1324         rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1325
1326         /* Set the state as STOPPED */
1327         priv->can.state = CAN_STATE_STOPPED;
1328 }
1329
1330 static int rcar_canfd_close(struct net_device *ndev)
1331 {
1332         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1333         struct rcar_canfd_global *gpriv = priv->gpriv;
1334
1335         netif_stop_queue(ndev);
1336         rcar_canfd_stop(ndev);
1337         napi_disable(&priv->napi);
1338         clk_disable_unprepare(gpriv->can_clk);
1339         close_candev(ndev);
1340         can_led_event(ndev, CAN_LED_EVENT_STOP);
1341         return 0;
1342 }
1343
1344 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1345                                          struct net_device *ndev)
1346 {
1347         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1348         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1349         u32 sts = 0, id, dlc;
1350         unsigned long flags;
1351         u32 ch = priv->channel;
1352
1353         if (can_dropped_invalid_skb(ndev, skb))
1354                 return NETDEV_TX_OK;
1355
1356         if (cf->can_id & CAN_EFF_FLAG) {
1357                 id = cf->can_id & CAN_EFF_MASK;
1358                 id |= RCANFD_CFID_CFIDE;
1359         } else {
1360                 id = cf->can_id & CAN_SFF_MASK;
1361         }
1362
1363         if (cf->can_id & CAN_RTR_FLAG)
1364                 id |= RCANFD_CFID_CFRTR;
1365
1366         dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
1367
1368         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1369                 rcar_canfd_write(priv->base,
1370                                  RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1371                 rcar_canfd_write(priv->base,
1372                                  RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1373
1374                 if (can_is_canfd_skb(skb)) {
1375                         /* CAN FD frame format */
1376                         sts |= RCANFD_CFFDCSTS_CFFDF;
1377                         if (cf->flags & CANFD_BRS)
1378                                 sts |= RCANFD_CFFDCSTS_CFBRS;
1379
1380                         if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1381                                 sts |= RCANFD_CFFDCSTS_CFESI;
1382                 }
1383
1384                 rcar_canfd_write(priv->base,
1385                                  RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1386
1387                 rcar_canfd_put_data(priv, cf,
1388                                     RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1389         } else {
1390                 rcar_canfd_write(priv->base,
1391                                  RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1392                 rcar_canfd_write(priv->base,
1393                                  RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1394                 rcar_canfd_put_data(priv, cf,
1395                                     RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1396         }
1397
1398         priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1399         can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
1400
1401         spin_lock_irqsave(&priv->tx_lock, flags);
1402         priv->tx_head++;
1403
1404         /* Stop the queue if we've filled all FIFO entries */
1405         if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1406                 netif_stop_queue(ndev);
1407
1408         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1409          * pointer for the Common FIFO
1410          */
1411         rcar_canfd_write(priv->base,
1412                          RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1413
1414         spin_unlock_irqrestore(&priv->tx_lock, flags);
1415         return NETDEV_TX_OK;
1416 }
1417
1418 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1419 {
1420         struct net_device_stats *stats = &priv->ndev->stats;
1421         struct canfd_frame *cf;
1422         struct sk_buff *skb;
1423         u32 sts = 0, id, dlc;
1424         u32 ch = priv->channel;
1425         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1426
1427         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1428                 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1429                 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1430
1431                 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1432                 if (sts & RCANFD_RFFDSTS_RFFDF)
1433                         skb = alloc_canfd_skb(priv->ndev, &cf);
1434                 else
1435                         skb = alloc_can_skb(priv->ndev,
1436                                             (struct can_frame **)&cf);
1437         } else {
1438                 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1439                 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1440                 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1441         }
1442
1443         if (!skb) {
1444                 stats->rx_dropped++;
1445                 return;
1446         }
1447
1448         if (id & RCANFD_RFID_RFIDE)
1449                 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1450         else
1451                 cf->can_id = id & CAN_SFF_MASK;
1452
1453         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1454                 if (sts & RCANFD_RFFDSTS_RFFDF)
1455                         cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1456                 else
1457                         cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1458
1459                 if (sts & RCANFD_RFFDSTS_RFESI) {
1460                         cf->flags |= CANFD_ESI;
1461                         netdev_dbg(priv->ndev, "ESI Error\n");
1462                 }
1463
1464                 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1465                         cf->can_id |= CAN_RTR_FLAG;
1466                 } else {
1467                         if (sts & RCANFD_RFFDSTS_RFBRS)
1468                                 cf->flags |= CANFD_BRS;
1469
1470                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1471                 }
1472         } else {
1473                 cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1474                 if (id & RCANFD_RFID_RFRTR)
1475                         cf->can_id |= CAN_RTR_FLAG;
1476                 else
1477                         rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1478         }
1479
1480         /* Write 0xff to RFPC to increment the CPU-side
1481          * pointer of the Rx FIFO
1482          */
1483         rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1484
1485         can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1486
1487         stats->rx_bytes += cf->len;
1488         stats->rx_packets++;
1489         netif_receive_skb(skb);
1490 }
1491
1492 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1493 {
1494         struct rcar_canfd_channel *priv =
1495                 container_of(napi, struct rcar_canfd_channel, napi);
1496         int num_pkts;
1497         u32 sts;
1498         u32 ch = priv->channel;
1499         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1500
1501         for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1502                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1503                 /* Check FIFO empty condition */
1504                 if (sts & RCANFD_RFSTS_RFEMP)
1505                         break;
1506
1507                 rcar_canfd_rx_pkt(priv);
1508
1509                 /* Clear interrupt bit */
1510                 if (sts & RCANFD_RFSTS_RFIF)
1511                         rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1512                                          sts & ~RCANFD_RFSTS_RFIF);
1513         }
1514
1515         /* All packets processed */
1516         if (num_pkts < quota) {
1517                 napi_complete(napi);
1518                 /* Enable Rx FIFO interrupts */
1519                 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1520                                    RCANFD_RFCC_RFIE);
1521         }
1522         return num_pkts;
1523 }
1524
1525 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1526 {
1527         int err;
1528
1529         switch (mode) {
1530         case CAN_MODE_START:
1531                 err = rcar_canfd_start(ndev);
1532                 if (err)
1533                         return err;
1534                 netif_wake_queue(ndev);
1535                 return 0;
1536         default:
1537                 return -EOPNOTSUPP;
1538         }
1539 }
1540
1541 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1542                                        struct can_berr_counter *bec)
1543 {
1544         struct rcar_canfd_channel *priv = netdev_priv(dev);
1545         u32 val, ch = priv->channel;
1546
1547         /* Peripheral clock is already enabled in probe */
1548         val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1549         bec->txerr = RCANFD_CSTS_TECCNT(val);
1550         bec->rxerr = RCANFD_CSTS_RECCNT(val);
1551         return 0;
1552 }
1553
1554 static const struct net_device_ops rcar_canfd_netdev_ops = {
1555         .ndo_open = rcar_canfd_open,
1556         .ndo_stop = rcar_canfd_close,
1557         .ndo_start_xmit = rcar_canfd_start_xmit,
1558         .ndo_change_mtu = can_change_mtu,
1559 };
1560
1561 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1562                                     u32 fcan_freq)
1563 {
1564         struct platform_device *pdev = gpriv->pdev;
1565         struct rcar_canfd_channel *priv;
1566         struct net_device *ndev;
1567         int err = -ENODEV;
1568
1569         ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1570         if (!ndev) {
1571                 dev_err(&pdev->dev, "alloc_candev() failed\n");
1572                 err = -ENOMEM;
1573                 goto fail;
1574         }
1575         priv = netdev_priv(ndev);
1576
1577         ndev->netdev_ops = &rcar_canfd_netdev_ops;
1578         ndev->flags |= IFF_ECHO;
1579         priv->ndev = ndev;
1580         priv->base = gpriv->base;
1581         priv->channel = ch;
1582         priv->can.clock.freq = fcan_freq;
1583         dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1584
1585         if (gpriv->fdmode) {
1586                 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1587                 priv->can.data_bittiming_const =
1588                         &rcar_canfd_data_bittiming_const;
1589
1590                 /* Controller starts in CAN FD only mode */
1591                 can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1592                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1593         } else {
1594                 /* Controller starts in Classical CAN only mode */
1595                 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1596                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1597         }
1598
1599         priv->can.do_set_mode = rcar_canfd_do_set_mode;
1600         priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1601         priv->gpriv = gpriv;
1602         SET_NETDEV_DEV(ndev, &pdev->dev);
1603
1604         netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1605                        RCANFD_NAPI_WEIGHT);
1606         spin_lock_init(&priv->tx_lock);
1607         devm_can_led_init(ndev);
1608         gpriv->ch[priv->channel] = priv;
1609         err = register_candev(ndev);
1610         if (err) {
1611                 dev_err(&pdev->dev,
1612                         "register_candev() failed, error %d\n", err);
1613                 goto fail_candev;
1614         }
1615         dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1616         return 0;
1617
1618 fail_candev:
1619         netif_napi_del(&priv->napi);
1620         free_candev(ndev);
1621 fail:
1622         return err;
1623 }
1624
1625 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1626 {
1627         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1628
1629         if (priv) {
1630                 unregister_candev(priv->ndev);
1631                 netif_napi_del(&priv->napi);
1632                 free_candev(priv->ndev);
1633         }
1634 }
1635
1636 static int rcar_canfd_probe(struct platform_device *pdev)
1637 {
1638         struct resource *mem;
1639         void __iomem *addr;
1640         u32 sts, ch, fcan_freq;
1641         struct rcar_canfd_global *gpriv;
1642         struct device_node *of_child;
1643         unsigned long channels_mask = 0;
1644         int err, ch_irq, g_irq;
1645         bool fdmode = true;                     /* CAN FD only mode - default */
1646
1647         if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1648                 fdmode = false;                 /* Classical CAN only mode */
1649
1650         of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1651         if (of_child && of_device_is_available(of_child))
1652                 channels_mask |= BIT(0);        /* Channel 0 */
1653
1654         of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1655         if (of_child && of_device_is_available(of_child))
1656                 channels_mask |= BIT(1);        /* Channel 1 */
1657
1658         ch_irq = platform_get_irq(pdev, 0);
1659         if (ch_irq < 0) {
1660                 dev_err(&pdev->dev, "no Channel IRQ resource\n");
1661                 err = ch_irq;
1662                 goto fail_dev;
1663         }
1664
1665         g_irq = platform_get_irq(pdev, 1);
1666         if (g_irq < 0) {
1667                 dev_err(&pdev->dev, "no Global IRQ resource\n");
1668                 err = g_irq;
1669                 goto fail_dev;
1670         }
1671
1672         /* Global controller context */
1673         gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1674         if (!gpriv) {
1675                 err = -ENOMEM;
1676                 goto fail_dev;
1677         }
1678         gpriv->pdev = pdev;
1679         gpriv->channels_mask = channels_mask;
1680         gpriv->fdmode = fdmode;
1681
1682         /* Peripheral clock */
1683         gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1684         if (IS_ERR(gpriv->clkp)) {
1685                 err = PTR_ERR(gpriv->clkp);
1686                 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1687                         err);
1688                 goto fail_dev;
1689         }
1690
1691         /* fCAN clock: Pick External clock. If not available fallback to
1692          * CANFD clock
1693          */
1694         gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1695         if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1696                 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1697                 if (IS_ERR(gpriv->can_clk)) {
1698                         err = PTR_ERR(gpriv->can_clk);
1699                         dev_err(&pdev->dev,
1700                                 "cannot get canfd clock, error %d\n", err);
1701                         goto fail_dev;
1702                 }
1703                 gpriv->fcan = RCANFD_CANFDCLK;
1704
1705         } else {
1706                 gpriv->fcan = RCANFD_EXTCLK;
1707         }
1708         fcan_freq = clk_get_rate(gpriv->can_clk);
1709
1710         if (gpriv->fcan == RCANFD_CANFDCLK)
1711                 /* CANFD clock is further divided by (1/2) within the IP */
1712                 fcan_freq /= 2;
1713
1714         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1715         addr = devm_ioremap_resource(&pdev->dev, mem);
1716         if (IS_ERR(addr)) {
1717                 err = PTR_ERR(addr);
1718                 goto fail_dev;
1719         }
1720         gpriv->base = addr;
1721
1722         /* Request IRQ that's common for both channels */
1723         err = devm_request_irq(&pdev->dev, ch_irq,
1724                                rcar_canfd_channel_interrupt, 0,
1725                                "canfd.chn", gpriv);
1726         if (err) {
1727                 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1728                         ch_irq, err);
1729                 goto fail_dev;
1730         }
1731         err = devm_request_irq(&pdev->dev, g_irq,
1732                                rcar_canfd_global_interrupt, 0,
1733                                "canfd.gbl", gpriv);
1734         if (err) {
1735                 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1736                         g_irq, err);
1737                 goto fail_dev;
1738         }
1739
1740         /* Enable peripheral clock for register access */
1741         err = clk_prepare_enable(gpriv->clkp);
1742         if (err) {
1743                 dev_err(&pdev->dev,
1744                         "failed to enable peripheral clock, error %d\n", err);
1745                 goto fail_dev;
1746         }
1747
1748         err = rcar_canfd_reset_controller(gpriv);
1749         if (err) {
1750                 dev_err(&pdev->dev, "reset controller failed\n");
1751                 goto fail_clk;
1752         }
1753
1754         /* Controller in Global reset & Channel reset mode */
1755         rcar_canfd_configure_controller(gpriv);
1756
1757         /* Configure per channel attributes */
1758         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1759                 /* Configure Channel's Rx fifo */
1760                 rcar_canfd_configure_rx(gpriv, ch);
1761
1762                 /* Configure Channel's Tx (Common) fifo */
1763                 rcar_canfd_configure_tx(gpriv, ch);
1764
1765                 /* Configure receive rules */
1766                 rcar_canfd_configure_afl_rules(gpriv, ch);
1767         }
1768
1769         /* Configure common interrupts */
1770         rcar_canfd_enable_global_interrupts(gpriv);
1771
1772         /* Start Global operation mode */
1773         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1774                               RCANFD_GCTR_GMDC_GOPM);
1775
1776         /* Verify mode change */
1777         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1778                                  !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1779         if (err) {
1780                 dev_err(&pdev->dev, "global operational mode failed\n");
1781                 goto fail_mode;
1782         }
1783
1784         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1785                 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1786                 if (err)
1787                         goto fail_channel;
1788         }
1789
1790         platform_set_drvdata(pdev, gpriv);
1791         dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1792                  gpriv->fcan, gpriv->fdmode);
1793         return 0;
1794
1795 fail_channel:
1796         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1797                 rcar_canfd_channel_remove(gpriv, ch);
1798 fail_mode:
1799         rcar_canfd_disable_global_interrupts(gpriv);
1800 fail_clk:
1801         clk_disable_unprepare(gpriv->clkp);
1802 fail_dev:
1803         return err;
1804 }
1805
1806 static int rcar_canfd_remove(struct platform_device *pdev)
1807 {
1808         struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1809         u32 ch;
1810
1811         rcar_canfd_reset_controller(gpriv);
1812         rcar_canfd_disable_global_interrupts(gpriv);
1813
1814         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1815                 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1816                 rcar_canfd_channel_remove(gpriv, ch);
1817         }
1818
1819         /* Enter global sleep mode */
1820         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
1821         clk_disable_unprepare(gpriv->clkp);
1822         return 0;
1823 }
1824
1825 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
1826 {
1827         return 0;
1828 }
1829
1830 static int __maybe_unused rcar_canfd_resume(struct device *dev)
1831 {
1832         return 0;
1833 }
1834
1835 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
1836                          rcar_canfd_resume);
1837
1838 static const struct of_device_id rcar_canfd_of_table[] = {
1839         { .compatible = "renesas,rcar-gen3-canfd" },
1840         { }
1841 };
1842
1843 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
1844
1845 static struct platform_driver rcar_canfd_driver = {
1846         .driver = {
1847                 .name = RCANFD_DRV_NAME,
1848                 .of_match_table = of_match_ptr(rcar_canfd_of_table),
1849                 .pm = &rcar_canfd_pm_ops,
1850         },
1851         .probe = rcar_canfd_probe,
1852         .remove = rcar_canfd_remove,
1853 };
1854
1855 module_platform_driver(rcar_canfd_driver);
1856
1857 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1858 MODULE_LICENSE("GPL");
1859 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
1860 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);