1 // SPDX-License-Identifier: GPL-2.0-only
3 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8 * Copyright (C) 2009 Wolfram Sang, Pengutronix <kernel@pengutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/netdevice.h>
16 #include <linux/can/dev.h>
17 #include <linux/of_platform.h>
18 #include <sysdev/fsl_soc.h>
19 #include <linux/clk.h>
21 #include <asm/mpc52xx.h>
25 #define DRV_NAME "mpc5xxx_can"
27 struct mpc5xxx_can_data {
29 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
31 void (*put_clock)(struct platform_device *ofdev);
34 #ifdef CONFIG_PPC_MPC52xx
35 static const struct of_device_id mpc52xx_cdm_ids[] = {
36 { .compatible = "fsl,mpc5200-cdm", },
40 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
41 const char *clock_name, int *mscan_clksrc)
44 struct mpc52xx_cdm __iomem *cdm;
45 struct device_node *np_cdm;
49 pvr = mfspr(SPRN_PVR);
52 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
53 * (IP_CLK) can be selected as MSCAN clock source. According to
54 * the MPC5200 user's manual, the oscillator clock is the better
55 * choice as it has less jitter. For this reason, it is selected
56 * by default. Unfortunately, it can not be selected for the old
57 * MPC5200 Rev. A chips due to a hardware bug (check errata).
59 if (clock_name && strcmp(clock_name, "ip") == 0)
60 *mscan_clksrc = MSCAN_CLKSRC_BUS;
62 *mscan_clksrc = MSCAN_CLKSRC_XTAL;
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
68 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
71 /* Determine SYS_XTAL_IN frequency from the clock domain settings */
72 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
74 dev_err(&ofdev->dev, "can't get clock node!\n");
77 cdm = of_iomap(np_cdm, 0);
80 dev_err(&ofdev->dev, "can't map clock node!\n");
84 if (in_8(&cdm->ipb_clk_sel) & 0x1)
86 val = in_be32(&cdm->rstcfg);
88 freq *= (val & (1 << 5)) ? 8 : 4;
89 freq /= (val & (1 << 6)) ? 12 : 16;
96 #else /* !CONFIG_PPC_MPC52xx */
97 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
98 const char *clock_name, int *mscan_clksrc)
102 #endif /* CONFIG_PPC_MPC52xx */
104 #ifdef CONFIG_PPC_MPC512x
105 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
106 const char *clock_source, int *mscan_clksrc)
108 struct device_node *np;
116 struct clk *clk_in, *clk_can;
117 unsigned long freq_calc;
118 struct mscan_priv *priv;
121 /* the caller passed in the clock source spec that was read from
122 * the device tree, get the optional clock divider as well
124 np = ofdev->dev.of_node;
126 of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
127 dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
128 clock_source ? clock_source : "<NULL>", clockdiv);
130 /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
131 * get set, and the 'ips' clock is the input to the MSCAN
134 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
135 * bit needs to get cleared, an optional clock-divider may have
136 * been specified (the default value is 1), the appropriate
137 * MSCAN related MCLK is the input to the MSCAN component
139 * in the absence of a clock-source spec, first an optimal clock
140 * gets determined based on the 'sys' clock, if that fails the
141 * 'ref' clock is used
143 clk_from = CLK_FROM_AUTO;
145 /* interpret the device tree's spec for the clock source */
146 if (!strcmp(clock_source, "ip"))
147 clk_from = CLK_FROM_IPS;
148 else if (!strcmp(clock_source, "sys"))
149 clk_from = CLK_FROM_SYS;
150 else if (!strcmp(clock_source, "ref"))
151 clk_from = CLK_FROM_REF;
154 dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
156 if (clk_from == CLK_FROM_AUTO) {
157 /* no spec so far, try the 'sys' clock; round to the
158 * next MHz and see if we can get a multiple of 16MHz
160 dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
161 clk_in = devm_clk_get(&ofdev->dev, "sys");
164 freq_calc = clk_get_rate(clk_in);
166 freq_calc /= 1000000;
167 freq_calc *= 1000000;
168 if ((freq_calc % 16000000) == 0) {
169 clk_from = CLK_FROM_SYS;
170 clockdiv = freq_calc / 16000000;
172 "clk fit, sys[%lu] div[%d] freq[%lu]\n",
173 freq_calc, clockdiv, freq_calc / clockdiv);
176 if (clk_from == CLK_FROM_AUTO) {
177 /* no spec so far, use the 'ref' clock */
178 dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
179 clk_in = devm_clk_get(&ofdev->dev, "ref");
182 clk_from = CLK_FROM_REF;
183 freq_calc = clk_get_rate(clk_in);
185 "clk fit, ref[%lu] (no div) freq[%lu]\n",
186 freq_calc, freq_calc);
189 /* select IPS or MCLK as the MSCAN input (returned to the caller),
190 * setup the MCLK mux source and rate if applicable, apply the
191 * optionally specified or derived above divider, and determine
192 * the actual resulting clock rate to return to the caller
196 clk_can = devm_clk_get(&ofdev->dev, "ips");
199 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
200 priv->clk_can = clk_can;
201 freq_calc = clk_get_rate(clk_can);
202 *mscan_clksrc = MSCAN_CLKSRC_IPS;
203 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
204 *mscan_clksrc, freq_calc);
208 clk_can = devm_clk_get(&ofdev->dev, "mclk");
211 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
212 priv->clk_can = clk_can;
213 if (clk_from == CLK_FROM_SYS)
214 clk_in = devm_clk_get(&ofdev->dev, "sys");
215 if (clk_from == CLK_FROM_REF)
216 clk_in = devm_clk_get(&ofdev->dev, "ref");
219 clk_set_parent(clk_can, clk_in);
220 freq_calc = clk_get_rate(clk_in);
221 freq_calc /= clockdiv;
222 clk_set_rate(clk_can, freq_calc);
223 freq_calc = clk_get_rate(clk_can);
224 *mscan_clksrc = MSCAN_CLKSRC_BUS;
225 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
226 *mscan_clksrc, freq_calc);
232 /* the above clk_can item is used for the bitrate, access to
233 * the peripheral's register set needs the clk_ipg item
235 clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
237 goto err_notavail_ipg;
238 if (clk_prepare_enable(clk_ipg))
239 goto err_notavail_ipg;
240 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
241 priv->clk_ipg = clk_ipg;
243 /* return the determined clock source rate */
247 dev_err(&ofdev->dev, "invalid clock source specification\n");
248 /* clock source rate could not get determined */
252 dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
253 /* clock source rate could not get determined */
257 dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
258 /* clock source rate could not get determined */
262 static void mpc512x_can_put_clock(struct platform_device *ofdev)
264 struct mscan_priv *priv;
266 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
268 clk_disable_unprepare(priv->clk_ipg);
270 #else /* !CONFIG_PPC_MPC512x */
271 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
272 const char *clock_name, int *mscan_clksrc)
276 #define mpc512x_can_put_clock NULL
277 #endif /* CONFIG_PPC_MPC512x */
279 static const struct of_device_id mpc5xxx_can_table[];
280 static int mpc5xxx_can_probe(struct platform_device *ofdev)
282 const struct of_device_id *match;
283 const struct mpc5xxx_can_data *data;
284 struct device_node *np = ofdev->dev.of_node;
285 struct net_device *dev;
286 struct mscan_priv *priv;
288 const char *clock_name = NULL;
289 int irq, mscan_clksrc = 0;
292 match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
297 base = of_iomap(np, 0);
299 dev_err(&ofdev->dev, "couldn't ioremap\n");
303 irq = irq_of_parse_and_map(np, 0);
305 dev_err(&ofdev->dev, "no irq found\n");
310 dev = alloc_mscandev();
312 goto exit_dispose_irq;
313 platform_set_drvdata(ofdev, dev);
314 SET_NETDEV_DEV(dev, &ofdev->dev);
316 priv = netdev_priv(dev);
317 priv->reg_base = base;
320 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
323 priv->type = data->type;
324 priv->can.clock.freq = data->get_clock(ofdev, clock_name,
326 if (!priv->can.clock.freq) {
327 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
331 err = register_mscandev(dev, mscan_clksrc);
333 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
338 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
339 priv->reg_base, dev->irq, priv->can.clock.freq);
345 data->put_clock(ofdev);
348 irq_dispose_mapping(irq);
355 static int mpc5xxx_can_remove(struct platform_device *ofdev)
357 const struct of_device_id *match;
358 const struct mpc5xxx_can_data *data;
359 struct net_device *dev = platform_get_drvdata(ofdev);
360 struct mscan_priv *priv = netdev_priv(dev);
362 match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
363 data = match ? match->data : NULL;
365 unregister_mscandev(dev);
366 if (data && data->put_clock)
367 data->put_clock(ofdev);
368 iounmap(priv->reg_base);
369 irq_dispose_mapping(dev->irq);
376 static struct mscan_regs saved_regs;
377 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
379 struct net_device *dev = platform_get_drvdata(ofdev);
380 struct mscan_priv *priv = netdev_priv(dev);
381 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
383 _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
388 static int mpc5xxx_can_resume(struct platform_device *ofdev)
390 struct net_device *dev = platform_get_drvdata(ofdev);
391 struct mscan_priv *priv = netdev_priv(dev);
392 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
394 regs->canctl0 |= MSCAN_INITRQ;
395 while (!(regs->canctl1 & MSCAN_INITAK))
398 regs->canctl1 = saved_regs.canctl1;
399 regs->canbtr0 = saved_regs.canbtr0;
400 regs->canbtr1 = saved_regs.canbtr1;
401 regs->canidac = saved_regs.canidac;
403 /* restore masks, buffers etc. */
404 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0,
405 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
407 regs->canctl0 &= ~MSCAN_INITRQ;
408 regs->cantbsel = saved_regs.cantbsel;
409 regs->canrier = saved_regs.canrier;
410 regs->cantier = saved_regs.cantier;
411 regs->canctl0 = saved_regs.canctl0;
417 static const struct mpc5xxx_can_data mpc5200_can_data = {
418 .type = MSCAN_TYPE_MPC5200,
419 .get_clock = mpc52xx_can_get_clock,
420 /* .put_clock not applicable */
423 static const struct mpc5xxx_can_data mpc5121_can_data = {
424 .type = MSCAN_TYPE_MPC5121,
425 .get_clock = mpc512x_can_get_clock,
426 .put_clock = mpc512x_can_put_clock,
429 static const struct of_device_id mpc5xxx_can_table[] = {
430 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
431 /* Note that only MPC5121 Rev. 2 (and later) is supported */
432 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
435 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
437 static struct platform_driver mpc5xxx_can_driver = {
439 .name = "mpc5xxx_can",
440 .of_match_table = mpc5xxx_can_table,
442 .probe = mpc5xxx_can_probe,
443 .remove = mpc5xxx_can_remove,
445 .suspend = mpc5xxx_can_suspend,
446 .resume = mpc5xxx_can_resume,
450 module_platform_driver(mpc5xxx_can_driver);
452 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
453 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
454 MODULE_LICENSE("GPL v2");