drivers/net/can/m_can/tcan4x5x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // SPI to CAN driver for the Texas Instruments TCAN4x5x
   3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
   4
   5 #include <linux/regmap.h>
   6 #include <linux/spi/spi.h>
   7
   8 #include <linux/regulator/consumer.h>
   9 #include <linux/gpio/consumer.h>
  10
  11 #include "m_can.h"
  12
  13 #define DEVICE_NAME "tcan4x5x"
  14 #define TCAN4X5X_EXT_CLK_DEF 40000000
  15
  16 #define TCAN4X5X_DEV_ID0 0x00
  17 #define TCAN4X5X_DEV_ID1 0x04
  18 #define TCAN4X5X_REV 0x08
  19 #define TCAN4X5X_STATUS 0x0C
  20 #define TCAN4X5X_ERROR_STATUS 0x10
  21 #define TCAN4X5X_CONTROL 0x14
  22
  23 #define TCAN4X5X_CONFIG 0x800
  24 #define TCAN4X5X_TS_PRESCALE 0x804
  25 #define TCAN4X5X_TEST_REG 0x808
  26 #define TCAN4X5X_INT_FLAGS 0x820
  27 #define TCAN4X5X_MCAN_INT_REG 0x824
  28 #define TCAN4X5X_INT_EN 0x830
  29
  30 /* Interrupt bits */
  31 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
  32 #define TCAN4X5X_CANHCANL_INT_EN BIT(29)
  33 #define TCAN4X5X_CANHBAT_INT_EN BIT(28)
  34 #define TCAN4X5X_CANLGND_INT_EN BIT(27)
  35 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
  36 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
  37 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
  38 #define TCAN4X5X_UVSUP_INT_EN BIT(22)
  39 #define TCAN4X5X_UVIO_INT_EN BIT(21)
  40 #define TCAN4X5X_TSD_INT_EN BIT(19)
  41 #define TCAN4X5X_ECCERR_INT_EN BIT(16)
  42 #define TCAN4X5X_CANINT_INT_EN BIT(15)
  43 #define TCAN4X5X_LWU_INT_EN BIT(14)
  44 #define TCAN4X5X_CANSLNT_INT_EN BIT(10)
  45 #define TCAN4X5X_CANDOM_INT_EN BIT(8)
  46 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
  47 #define TCAN4X5X_BUS_FAULT BIT(4)
  48 #define TCAN4X5X_MCAN_INT BIT(1)
  49 #define TCAN4X5X_ENABLE_TCAN_INT \
  50         (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
  51          TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
  52
  53 /* MCAN Interrupt bits */
  54 #define TCAN4X5X_MCAN_IR_ARA BIT(29)
  55 #define TCAN4X5X_MCAN_IR_PED BIT(28)
  56 #define TCAN4X5X_MCAN_IR_PEA BIT(27)
  57 #define TCAN4X5X_MCAN_IR_WD BIT(26)
  58 #define TCAN4X5X_MCAN_IR_BO BIT(25)
  59 #define TCAN4X5X_MCAN_IR_EW BIT(24)
  60 #define TCAN4X5X_MCAN_IR_EP BIT(23)
  61 #define TCAN4X5X_MCAN_IR_ELO BIT(22)
  62 #define TCAN4X5X_MCAN_IR_BEU BIT(21)
  63 #define TCAN4X5X_MCAN_IR_BEC BIT(20)
  64 #define TCAN4X5X_MCAN_IR_DRX BIT(19)
  65 #define TCAN4X5X_MCAN_IR_TOO BIT(18)
  66 #define TCAN4X5X_MCAN_IR_MRAF BIT(17)
  67 #define TCAN4X5X_MCAN_IR_TSW BIT(16)
  68 #define TCAN4X5X_MCAN_IR_TEFL BIT(15)
  69 #define TCAN4X5X_MCAN_IR_TEFF BIT(14)
  70 #define TCAN4X5X_MCAN_IR_TEFW BIT(13)
  71 #define TCAN4X5X_MCAN_IR_TEFN BIT(12)
  72 #define TCAN4X5X_MCAN_IR_TFE BIT(11)
  73 #define TCAN4X5X_MCAN_IR_TCF BIT(10)
  74 #define TCAN4X5X_MCAN_IR_TC BIT(9)
  75 #define TCAN4X5X_MCAN_IR_HPM BIT(8)
  76 #define TCAN4X5X_MCAN_IR_RF1L BIT(7)
  77 #define TCAN4X5X_MCAN_IR_RF1F BIT(6)
  78 #define TCAN4X5X_MCAN_IR_RF1W BIT(5)
  79 #define TCAN4X5X_MCAN_IR_RF1N BIT(4)
  80 #define TCAN4X5X_MCAN_IR_RF0L BIT(3)
  81 #define TCAN4X5X_MCAN_IR_RF0F BIT(2)
  82 #define TCAN4X5X_MCAN_IR_RF0W BIT(1)
  83 #define TCAN4X5X_MCAN_IR_RF0N BIT(0)
  84 #define TCAN4X5X_ENABLE_MCAN_INT \
  85         (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
  86          TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
  87          TCAN4X5X_MCAN_IR_RF1F)
  88
  89 #define TCAN4X5X_MRAM_START 0x8000
  90 #define TCAN4X5X_MCAN_OFFSET 0x1000
  91 #define TCAN4X5X_MAX_REGISTER 0x8ffc
  92
  93 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
  94 #define TCAN4X5X_SET_ALL_INT 0xffffffff
  95
  96 #define TCAN4X5X_WRITE_CMD (0x61 << 24)
  97 #define TCAN4X5X_READ_CMD (0x41 << 24)
  98
  99 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
 100 #define TCAN4X5X_MODE_SLEEP 0x00
 101 #define TCAN4X5X_MODE_STANDBY BIT(6)
 102 #define TCAN4X5X_MODE_NORMAL BIT(7)
 103
 104 #define TCAN4X5X_DISABLE_WAKE_MSK       (BIT(31) | BIT(30))
 105 #define TCAN4X5X_DISABLE_INH_MSK        BIT(9)
 106
 107 #define TCAN4X5X_SW_RESET BIT(2)
 108
 109 #define TCAN4X5X_MCAN_CONFIGURED BIT(5)
 110 #define TCAN4X5X_WATCHDOG_EN BIT(3)
 111 #define TCAN4X5X_WD_60_MS_TIMER 0
 112 #define TCAN4X5X_WD_600_MS_TIMER BIT(28)
 113 #define TCAN4X5X_WD_3_S_TIMER BIT(29)
 114 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
 115
 116 struct tcan4x5x_priv {
 117         struct regmap *regmap;
 118         struct spi_device *spi;
 119
 120         struct m_can_classdev *mcan_dev;
 121
 122         struct gpio_desc *reset_gpio;
 123         struct gpio_desc *device_wake_gpio;
 124         struct gpio_desc *device_state_gpio;
 125         struct regulator *power;
 126
 127         /* Register based ip */
 128         int mram_start;
 129         int reg_offset;
 130 };
 131
 132 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
 133 {
 134         int wake_state = 0;
 135
 136         if (priv->device_state_gpio)
 137                 wake_state = gpiod_get_value(priv->device_state_gpio);
 138
 139         if (priv->device_wake_gpio && wake_state) {
 140                 gpiod_set_value(priv->device_wake_gpio, 0);
 141                 usleep_range(5, 50);
 142                 gpiod_set_value(priv->device_wake_gpio, 1);
 143         }
 144 }
 145
 146 static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
 147 {
 148         int ret = 0;
 149
 150         if (priv->reset_gpio) {
 151                 gpiod_set_value(priv->reset_gpio, 1);
 152
 153                 /* tpulse_width minimum 30us */
 154                 usleep_range(30, 100);
 155                 gpiod_set_value(priv->reset_gpio, 0);
 156         } else {
 157                 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
 158                                    TCAN4X5X_SW_RESET);
 159                 if (ret)
 160                         return ret;
 161         }
 162
 163         usleep_range(700, 1000);
 164
 165         return ret;
 166 }
 167
 168 static int regmap_spi_gather_write(void *context, const void *reg,
 169                                    size_t reg_len, const void *val,
 170                                    size_t val_len)
 171 {
 172         struct device *dev = context;
 173         struct spi_device *spi = to_spi_device(dev);
 174         struct spi_message m;
 175         u32 addr;
 176         struct spi_transfer t[2] = {
 177                 { .tx_buf = &addr, .len = reg_len, .cs_change = 0,},
 178                 { .tx_buf = val, .len = val_len, },
 179         };
 180
 181         addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2;
 182
 183         spi_message_init(&m);
 184         spi_message_add_tail(&t[0], &m);
 185         spi_message_add_tail(&t[1], &m);
 186
 187         return spi_sync(spi, &m);
 188 }
 189
 190 static int tcan4x5x_regmap_write(void *context, const void *data, size_t count)
 191 {
 192         u16 *reg = (u16 *)(data);
 193         const u32 *val = data + 4;
 194
 195         return regmap_spi_gather_write(context, reg, 4, val, count - 4);
 196 }
 197
 198 static int regmap_spi_async_write(void *context,
 199                                   const void *reg, size_t reg_len,
 200                                   const void *val, size_t val_len,
 201                                   struct regmap_async *a)
 202 {
 203         return -ENOTSUPP;
 204 }
 205
 206 static struct regmap_async *regmap_spi_async_alloc(void)
 207 {
 208         return NULL;
 209 }
 210
 211 static int tcan4x5x_regmap_read(void *context,
 212                                 const void *reg, size_t reg_size,
 213                                 void *val, size_t val_size)
 214 {
 215         struct device *dev = context;
 216         struct spi_device *spi = to_spi_device(dev);
 217
 218         u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2;
 219
 220         return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size);
 221 }
 222
 223 static struct regmap_bus tcan4x5x_bus = {
 224         .write = tcan4x5x_regmap_write,
 225         .gather_write = regmap_spi_gather_write,
 226         .async_write = regmap_spi_async_write,
 227         .async_alloc = regmap_spi_async_alloc,
 228         .read = tcan4x5x_regmap_read,
 229         .read_flag_mask = 0x00,
 230         .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
 231         .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
 232 };
 233
 234 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
 235 {
 236         struct tcan4x5x_priv *priv = cdev->device_data;
 237         u32 val;
 238
 239         regmap_read(priv->regmap, priv->reg_offset + reg, &val);
 240
 241         return val;
 242 }
 243
 244 static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
 245 {
 246         struct tcan4x5x_priv *priv = cdev->device_data;
 247         u32 val;
 248
 249         regmap_read(priv->regmap, priv->mram_start + addr_offset, &val);
 250
 251         return val;
 252 }
 253
 254 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
 255 {
 256         struct tcan4x5x_priv *priv = cdev->device_data;
 257
 258         return regmap_write(priv->regmap, priv->reg_offset + reg, val);
 259 }
 260
 261 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
 262                                int addr_offset, int val)
 263 {
 264         struct tcan4x5x_priv *priv = cdev->device_data;
 265
 266         return regmap_write(priv->regmap, priv->mram_start + addr_offset, val);
 267 }
 268
 269 static int tcan4x5x_power_enable(struct regulator *reg, int enable)
 270 {
 271         if (IS_ERR_OR_NULL(reg))
 272                 return 0;
 273
 274         if (enable)
 275                 return regulator_enable(reg);
 276         else
 277                 return regulator_disable(reg);
 278 }
 279
 280 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
 281                                    int reg, int val)
 282 {
 283         struct tcan4x5x_priv *priv = cdev->device_data;
 284
 285         return regmap_write(priv->regmap, reg, val);
 286 }
 287
 288 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
 289 {
 290         int ret;
 291
 292         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
 293                                       TCAN4X5X_CLEAR_ALL_INT);
 294         if (ret)
 295                 return ret;
 296
 297         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
 298                                       TCAN4X5X_ENABLE_MCAN_INT);
 299         if (ret)
 300                 return ret;
 301
 302         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
 303                                       TCAN4X5X_CLEAR_ALL_INT);
 304         if (ret)
 305                 return ret;
 306
 307         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
 308                                       TCAN4X5X_CLEAR_ALL_INT);
 309         if (ret)
 310                 return ret;
 311
 312         return ret;
 313 }
 314
 315 static int tcan4x5x_init(struct m_can_classdev *cdev)
 316 {
 317         struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
 318         int ret;
 319
 320         tcan4x5x_check_wake(tcan4x5x);
 321
 322         ret = tcan4x5x_clear_interrupts(cdev);
 323         if (ret)
 324                 return ret;
 325
 326         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
 327                                       TCAN4X5X_ENABLE_TCAN_INT);
 328         if (ret)
 329                 return ret;
 330
 331         /* Zero out the MCAN buffers */
 332         m_can_init_ram(cdev);
 333
 334         ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 335                                  TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
 336         if (ret)
 337                 return ret;
 338
 339         return ret;
 340 }
 341
 342 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
 343 {
 344         struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
 345
 346         return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 347                                   TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
 348 }
 349
 350 static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
 351 {
 352         struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
 353
 354         return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 355                                   TCAN4X5X_DISABLE_INH_MSK, 0x01);
 356 }
 357
 358 static int tcan4x5x_parse_config(struct m_can_classdev *cdev)
 359 {
 360         struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
 361         int ret;
 362
 363         tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
 364                                                     GPIOD_OUT_HIGH);
 365         if (IS_ERR(tcan4x5x->device_wake_gpio)) {
 366                 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER)
 367                         return -EPROBE_DEFER;
 368
 369                 tcan4x5x_disable_wake(cdev);
 370         }
 371
 372         tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
 373                                                        GPIOD_OUT_LOW);
 374         if (IS_ERR(tcan4x5x->reset_gpio))
 375                 tcan4x5x->reset_gpio = NULL;
 376
 377         ret = tcan4x5x_reset(tcan4x5x);
 378         if (ret)
 379                 return ret;
 380
 381         tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
 382                                                               "device-state",
 383                                                               GPIOD_IN);
 384         if (IS_ERR(tcan4x5x->device_state_gpio)) {
 385                 tcan4x5x->device_state_gpio = NULL;
 386                 tcan4x5x_disable_state(cdev);
 387         }
 388
 389         return 0;
 390 }
 391
 392 static const struct regmap_config tcan4x5x_regmap = {
 393         .reg_bits = 32,
 394         .val_bits = 32,
 395         .cache_type = REGCACHE_NONE,
 396         .max_register = TCAN4X5X_MAX_REGISTER,
 397 };
 398
 399 static struct m_can_ops tcan4x5x_ops = {
 400         .init = tcan4x5x_init,
 401         .read_reg = tcan4x5x_read_reg,
 402         .write_reg = tcan4x5x_write_reg,
 403         .write_fifo = tcan4x5x_write_fifo,
 404         .read_fifo = tcan4x5x_read_fifo,
 405         .clear_interrupts = tcan4x5x_clear_interrupts,
 406 };
 407
 408 static int tcan4x5x_can_probe(struct spi_device *spi)
 409 {
 410         struct tcan4x5x_priv *priv;
 411         struct m_can_classdev *mcan_class;
 412         int freq, ret;
 413
 414         mcan_class = m_can_class_allocate_dev(&spi->dev);
 415         if (!mcan_class)
 416                 return -ENOMEM;
 417
 418         priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
 419         if (!priv) {
 420                 ret = -ENOMEM;
 421                 goto out_m_can_class_free_dev;
 422         }
 423
 424         priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
 425         if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
 426                 ret = -EPROBE_DEFER;
 427                 goto out_m_can_class_free_dev;
 428         } else {
 429                 priv->power = NULL;
 430         }
 431
 432         mcan_class->device_data = priv;
 433
 434         m_can_class_get_clocks(mcan_class);
 435         if (IS_ERR(mcan_class->cclk)) {
 436                 dev_err(&spi->dev, "no CAN clock source defined\n");
 437                 freq = TCAN4X5X_EXT_CLK_DEF;
 438         } else {
 439                 freq = clk_get_rate(mcan_class->cclk);
 440         }
 441
 442         /* Sanity check */
 443         if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) {
 444                 ret = -ERANGE;
 445                 goto out_m_can_class_free_dev;
 446         }
 447
 448         priv->reg_offset = TCAN4X5X_MCAN_OFFSET;
 449         priv->mram_start = TCAN4X5X_MRAM_START;
 450         priv->spi = spi;
 451         priv->mcan_dev = mcan_class;
 452
 453         mcan_class->pm_clock_support = 0;
 454         mcan_class->can.clock.freq = freq;
 455         mcan_class->dev = &spi->dev;
 456         mcan_class->ops = &tcan4x5x_ops;
 457         mcan_class->is_peripheral = true;
 458         mcan_class->net->irq = spi->irq;
 459
 460         spi_set_drvdata(spi, priv);
 461
 462         /* Configure the SPI bus */
 463         spi->bits_per_word = 32;
 464         ret = spi_setup(spi);
 465         if (ret)
 466                 goto out_m_can_class_free_dev;
 467
 468         priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
 469                                         &spi->dev, &tcan4x5x_regmap);
 470         if (IS_ERR(priv->regmap)) {
 471                 ret = PTR_ERR(priv->regmap);
 472                 goto out_m_can_class_free_dev;
 473         }
 474
 475         ret = tcan4x5x_power_enable(priv->power, 1);
 476         if (ret)
 477                 goto out_m_can_class_free_dev;
 478
 479         ret = tcan4x5x_parse_config(mcan_class);
 480         if (ret)
 481                 goto out_power;
 482
 483         ret = tcan4x5x_init(mcan_class);
 484         if (ret)
 485                 goto out_power;
 486
 487         ret = m_can_class_register(mcan_class);
 488         if (ret)
 489                 goto out_power;
 490
 491         netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
 492         return 0;
 493
 494 out_power:
 495         tcan4x5x_power_enable(priv->power, 0);
 496  out_m_can_class_free_dev:
 497         m_can_class_free_dev(mcan_class->net);
 498         dev_err(&spi->dev, "Probe failed, err=%d\n", ret);
 499
 500         return ret;
 501 }
 502
 503 static int tcan4x5x_can_remove(struct spi_device *spi)
 504 {
 505         struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
 506
 507         m_can_class_unregister(priv->mcan_dev);
 508
 509         tcan4x5x_power_enable(priv->power, 0);
 510
 511         m_can_class_free_dev(priv->mcan_dev->net);
 512
 513         return 0;
 514 }
 515
 516 static const struct of_device_id tcan4x5x_of_match[] = {
 517         { .compatible = "ti,tcan4x5x", },
 518         { }
 519 };
 520 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
 521
 522 static const struct spi_device_id tcan4x5x_id_table[] = {
 523         {
 524                 .name           = "tcan4x5x",
 525                 .driver_data    = 0,
 526         },
 527         { }
 528 };
 529 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
 530
 531 static struct spi_driver tcan4x5x_can_driver = {
 532         .driver = {
 533                 .name = DEVICE_NAME,
 534                 .of_match_table = tcan4x5x_of_match,
 535                 .pm = NULL,
 536         },
 537         .id_table = tcan4x5x_id_table,
 538         .probe = tcan4x5x_can_probe,
 539         .remove = tcan4x5x_can_remove,
 540 };
 541 module_spi_driver(tcan4x5x_can_driver);
 542
 543 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
 544 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
 545 MODULE_LICENSE("GPL v2");