2 * CAN bus driver for Bosch M_CAN controller
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/iopoll.h>
27 #include <linux/can/dev.h>
28 #include <linux/pinctrl/consumer.h>
31 #define M_CAN_NAPI_WEIGHT 64
33 /* message ram configuration data length */
34 #define MRAM_CFG_LEN 8
36 /* registers definition */
52 /* TDCR Register only available for version >=3.1.x */
88 /* m_can lec values */
100 enum m_can_mram_cfg {
111 /* Core Release Register (CREL) */
112 #define CREL_REL_SHIFT 28
113 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
114 #define CREL_STEP_SHIFT 24
115 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
116 #define CREL_SUBSTEP_SHIFT 20
117 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
119 /* Data Bit Timing & Prescaler Register (DBTP) */
120 #define DBTP_TDC BIT(23)
121 #define DBTP_DBRP_SHIFT 16
122 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
123 #define DBTP_DTSEG1_SHIFT 8
124 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
125 #define DBTP_DTSEG2_SHIFT 4
126 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
127 #define DBTP_DSJW_SHIFT 0
128 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
130 /* Test Register (TEST) */
131 #define TEST_LBCK BIT(4)
133 /* CC Control Register(CCCR) */
134 #define CCCR_CMR_MASK 0x3
135 #define CCCR_CMR_SHIFT 10
136 #define CCCR_CMR_CANFD 0x1
137 #define CCCR_CMR_CANFD_BRS 0x2
138 #define CCCR_CMR_CAN 0x3
139 #define CCCR_CME_MASK 0x3
140 #define CCCR_CME_SHIFT 8
141 #define CCCR_CME_CAN 0
142 #define CCCR_CME_CANFD 0x1
143 #define CCCR_CME_CANFD_BRS 0x2
144 #define CCCR_TXP BIT(14)
145 #define CCCR_TEST BIT(7)
146 #define CCCR_MON BIT(5)
147 #define CCCR_CSR BIT(4)
148 #define CCCR_CSA BIT(3)
149 #define CCCR_ASM BIT(2)
150 #define CCCR_CCE BIT(1)
151 #define CCCR_INIT BIT(0)
152 #define CCCR_CANFD 0x10
153 /* for version >=3.1.x */
154 #define CCCR_EFBI BIT(13)
155 #define CCCR_PXHD BIT(12)
156 #define CCCR_BRSE BIT(9)
157 #define CCCR_FDOE BIT(8)
158 /* only for version >=3.2.x */
159 #define CCCR_NISO BIT(15)
161 /* Nominal Bit Timing & Prescaler Register (NBTP) */
162 #define NBTP_NSJW_SHIFT 25
163 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
164 #define NBTP_NBRP_SHIFT 16
165 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
166 #define NBTP_NTSEG1_SHIFT 8
167 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
168 #define NBTP_NTSEG2_SHIFT 0
169 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
171 /* Error Counter Register(ECR) */
172 #define ECR_RP BIT(15)
173 #define ECR_REC_SHIFT 8
174 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
175 #define ECR_TEC_SHIFT 0
176 #define ECR_TEC_MASK 0xff
178 /* Protocol Status Register(PSR) */
179 #define PSR_BO BIT(7)
180 #define PSR_EW BIT(6)
181 #define PSR_EP BIT(5)
182 #define PSR_LEC_MASK 0x7
184 /* Interrupt Register(IR) */
185 #define IR_ALL_INT 0xffffffff
187 /* Renamed bits for versions > 3.1.x */
188 #define IR_ARA BIT(29)
189 #define IR_PED BIT(28)
190 #define IR_PEA BIT(27)
192 /* Bits for version 3.0.x */
193 #define IR_STE BIT(31)
194 #define IR_FOE BIT(30)
195 #define IR_ACKE BIT(29)
196 #define IR_BE BIT(28)
197 #define IR_CRCE BIT(27)
198 #define IR_WDI BIT(26)
199 #define IR_BO BIT(25)
200 #define IR_EW BIT(24)
201 #define IR_EP BIT(23)
202 #define IR_ELO BIT(22)
203 #define IR_BEU BIT(21)
204 #define IR_BEC BIT(20)
205 #define IR_DRX BIT(19)
206 #define IR_TOO BIT(18)
207 #define IR_MRAF BIT(17)
208 #define IR_TSW BIT(16)
209 #define IR_TEFL BIT(15)
210 #define IR_TEFF BIT(14)
211 #define IR_TEFW BIT(13)
212 #define IR_TEFN BIT(12)
213 #define IR_TFE BIT(11)
214 #define IR_TCF BIT(10)
216 #define IR_HPM BIT(8)
217 #define IR_RF1L BIT(7)
218 #define IR_RF1F BIT(6)
219 #define IR_RF1W BIT(5)
220 #define IR_RF1N BIT(4)
221 #define IR_RF0L BIT(3)
222 #define IR_RF0F BIT(2)
223 #define IR_RF0W BIT(1)
224 #define IR_RF0N BIT(0)
225 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
227 /* Interrupts for version 3.0.x */
228 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
229 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
230 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
232 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
233 /* Interrupts for version >= 3.1.x */
234 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
235 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
236 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
238 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
240 /* Interrupt Line Select (ILS) */
241 #define ILS_ALL_INT0 0x0
242 #define ILS_ALL_INT1 0xFFFFFFFF
244 /* Interrupt Line Enable (ILE) */
245 #define ILE_EINT1 BIT(1)
246 #define ILE_EINT0 BIT(0)
248 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
249 #define RXFC_FWM_SHIFT 24
250 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
251 #define RXFC_FS_SHIFT 16
252 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
254 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
255 #define RXFS_RFL BIT(25)
256 #define RXFS_FF BIT(24)
257 #define RXFS_FPI_SHIFT 16
258 #define RXFS_FPI_MASK 0x3f0000
259 #define RXFS_FGI_SHIFT 8
260 #define RXFS_FGI_MASK 0x3f00
261 #define RXFS_FFL_MASK 0x7f
263 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
264 #define M_CAN_RXESC_8BYTES 0x0
265 #define M_CAN_RXESC_64BYTES 0x777
267 /* Tx Buffer Configuration(TXBC) */
268 #define TXBC_NDTB_SHIFT 16
269 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
270 #define TXBC_TFQS_SHIFT 24
271 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
273 /* Tx FIFO/Queue Status (TXFQS) */
274 #define TXFQS_TFQF BIT(21)
275 #define TXFQS_TFQPI_SHIFT 16
276 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
277 #define TXFQS_TFGI_SHIFT 8
278 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
279 #define TXFQS_TFFL_SHIFT 0
280 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
282 /* Tx Buffer Element Size Configuration(TXESC) */
283 #define TXESC_TBDS_8BYTES 0x0
284 #define TXESC_TBDS_64BYTES 0x7
286 /* Tx Event FIFO Configuration (TXEFC) */
287 #define TXEFC_EFS_SHIFT 16
288 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
290 /* Tx Event FIFO Status (TXEFS) */
291 #define TXEFS_TEFL BIT(25)
292 #define TXEFS_EFF BIT(24)
293 #define TXEFS_EFGI_SHIFT 8
294 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
295 #define TXEFS_EFFL_SHIFT 0
296 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
298 /* Tx Event FIFO Acknowledge (TXEFA) */
299 #define TXEFA_EFAI_SHIFT 0
300 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
302 /* Message RAM Configuration (in bytes) */
303 #define SIDF_ELEMENT_SIZE 4
304 #define XIDF_ELEMENT_SIZE 8
305 #define RXF0_ELEMENT_SIZE 72
306 #define RXF1_ELEMENT_SIZE 72
307 #define RXB_ELEMENT_SIZE 72
308 #define TXE_ELEMENT_SIZE 8
309 #define TXB_ELEMENT_SIZE 72
311 /* Message RAM Elements */
312 #define M_CAN_FIFO_ID 0x0
313 #define M_CAN_FIFO_DLC 0x4
314 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
316 /* Rx Buffer Element */
318 #define RX_BUF_ESI BIT(31)
319 #define RX_BUF_XTD BIT(30)
320 #define RX_BUF_RTR BIT(29)
322 #define RX_BUF_ANMF BIT(31)
323 #define RX_BUF_FDF BIT(21)
324 #define RX_BUF_BRS BIT(20)
326 /* Tx Buffer Element */
328 #define TX_BUF_ESI BIT(31)
329 #define TX_BUF_XTD BIT(30)
330 #define TX_BUF_RTR BIT(29)
332 #define TX_BUF_EFC BIT(23)
333 #define TX_BUF_FDF BIT(21)
334 #define TX_BUF_BRS BIT(20)
335 #define TX_BUF_MM_SHIFT 24
336 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
338 /* Tx event FIFO Element */
340 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
341 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
343 /* address offset and element number for each FIFO/Buffer in the Message RAM */
349 /* m_can private data structure */
351 struct can_priv can; /* must be the first member */
352 struct napi_struct napi;
353 struct net_device *dev;
354 struct device *device;
361 /* message ram configuration */
362 void __iomem *mram_base;
363 struct mram_cfg mcfg[MRAM_CFG_NUM];
366 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
368 return readl(priv->base + reg);
371 static inline void m_can_write(const struct m_can_priv *priv,
372 enum m_can_reg reg, u32 val)
374 writel(val, priv->base + reg);
377 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
378 u32 fgi, unsigned int offset)
380 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
381 fgi * RXF0_ELEMENT_SIZE + offset);
384 static inline void m_can_fifo_write(const struct m_can_priv *priv,
385 u32 fpi, unsigned int offset, u32 val)
387 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
388 fpi * TXB_ELEMENT_SIZE + offset);
391 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
394 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
395 fgi * TXE_ELEMENT_SIZE + offset);
398 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
400 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
403 static inline void m_can_config_endisable(const struct m_can_priv *priv,
406 u32 cccr = m_can_read(priv, M_CAN_CCCR);
411 /* enable m_can configuration */
412 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
414 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
415 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
417 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
420 /* there's a delay for module initialization */
422 val = CCCR_INIT | CCCR_CCE;
424 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
426 netdev_warn(priv->dev, "Failed to init module\n");
434 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
436 /* Only interrupt line 0 is used in this driver */
437 m_can_write(priv, M_CAN_ILE, ILE_EINT0);
440 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
442 m_can_write(priv, M_CAN_ILE, 0x0);
445 static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
447 struct net_device_stats *stats = &dev->stats;
448 struct m_can_priv *priv = netdev_priv(dev);
449 struct canfd_frame *cf;
454 /* calculate the fifo get index for where to read data */
455 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
456 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
457 if (dlc & RX_BUF_FDF)
458 skb = alloc_canfd_skb(dev, &cf);
460 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
466 if (dlc & RX_BUF_FDF)
467 cf->len = can_dlc2len((dlc >> 16) & 0x0F);
469 cf->len = get_can_dlc((dlc >> 16) & 0x0F);
471 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
473 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
475 cf->can_id = (id >> 18) & CAN_SFF_MASK;
477 if (id & RX_BUF_ESI) {
478 cf->flags |= CANFD_ESI;
479 netdev_dbg(dev, "ESI Error\n");
482 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
483 cf->can_id |= CAN_RTR_FLAG;
485 if (dlc & RX_BUF_BRS)
486 cf->flags |= CANFD_BRS;
488 for (i = 0; i < cf->len; i += 4)
489 *(u32 *)(cf->data + i) =
490 m_can_fifo_read(priv, fgi,
491 M_CAN_FIFO_DATA(i / 4));
494 /* acknowledge rx fifo 0 */
495 m_can_write(priv, M_CAN_RXF0A, fgi);
498 stats->rx_bytes += cf->len;
500 netif_receive_skb(skb);
503 static int m_can_do_rx_poll(struct net_device *dev, int quota)
505 struct m_can_priv *priv = netdev_priv(dev);
509 rxfs = m_can_read(priv, M_CAN_RXF0S);
510 if (!(rxfs & RXFS_FFL_MASK)) {
511 netdev_dbg(dev, "no messages in fifo0\n");
515 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
516 m_can_read_fifo(dev, rxfs);
520 rxfs = m_can_read(priv, M_CAN_RXF0S);
524 can_led_event(dev, CAN_LED_EVENT_RX);
529 static int m_can_handle_lost_msg(struct net_device *dev)
531 struct net_device_stats *stats = &dev->stats;
533 struct can_frame *frame;
535 netdev_err(dev, "msg lost in rxf0\n");
538 stats->rx_over_errors++;
540 skb = alloc_can_err_skb(dev, &frame);
544 frame->can_id |= CAN_ERR_CRTL;
545 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
547 netif_receive_skb(skb);
552 static int m_can_handle_lec_err(struct net_device *dev,
553 enum m_can_lec_type lec_type)
555 struct m_can_priv *priv = netdev_priv(dev);
556 struct net_device_stats *stats = &dev->stats;
557 struct can_frame *cf;
560 priv->can.can_stats.bus_error++;
563 /* propagate the error condition to the CAN stack */
564 skb = alloc_can_err_skb(dev, &cf);
568 /* check for 'last error code' which tells us the
569 * type of the last error to occur on the CAN bus
571 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
574 case LEC_STUFF_ERROR:
575 netdev_dbg(dev, "stuff error\n");
576 cf->data[2] |= CAN_ERR_PROT_STUFF;
579 netdev_dbg(dev, "form error\n");
580 cf->data[2] |= CAN_ERR_PROT_FORM;
583 netdev_dbg(dev, "ack error\n");
584 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
587 netdev_dbg(dev, "bit1 error\n");
588 cf->data[2] |= CAN_ERR_PROT_BIT1;
591 netdev_dbg(dev, "bit0 error\n");
592 cf->data[2] |= CAN_ERR_PROT_BIT0;
595 netdev_dbg(dev, "CRC error\n");
596 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
603 stats->rx_bytes += cf->can_dlc;
604 netif_receive_skb(skb);
609 static int __m_can_get_berr_counter(const struct net_device *dev,
610 struct can_berr_counter *bec)
612 struct m_can_priv *priv = netdev_priv(dev);
615 ecr = m_can_read(priv, M_CAN_ECR);
616 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
617 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
622 static int m_can_clk_start(struct m_can_priv *priv)
626 err = clk_prepare_enable(priv->hclk);
630 err = clk_prepare_enable(priv->cclk);
632 clk_disable_unprepare(priv->hclk);
637 static void m_can_clk_stop(struct m_can_priv *priv)
639 clk_disable_unprepare(priv->cclk);
640 clk_disable_unprepare(priv->hclk);
643 static int m_can_get_berr_counter(const struct net_device *dev,
644 struct can_berr_counter *bec)
646 struct m_can_priv *priv = netdev_priv(dev);
649 err = m_can_clk_start(priv);
653 __m_can_get_berr_counter(dev, bec);
655 m_can_clk_stop(priv);
660 static int m_can_handle_state_change(struct net_device *dev,
661 enum can_state new_state)
663 struct m_can_priv *priv = netdev_priv(dev);
664 struct net_device_stats *stats = &dev->stats;
665 struct can_frame *cf;
667 struct can_berr_counter bec;
671 case CAN_STATE_ERROR_WARNING:
672 /* error warning state */
673 priv->can.can_stats.error_warning++;
674 priv->can.state = CAN_STATE_ERROR_WARNING;
676 case CAN_STATE_ERROR_PASSIVE:
677 /* error passive state */
678 priv->can.can_stats.error_passive++;
679 priv->can.state = CAN_STATE_ERROR_PASSIVE;
681 case CAN_STATE_BUS_OFF:
683 priv->can.state = CAN_STATE_BUS_OFF;
684 m_can_disable_all_interrupts(priv);
685 priv->can.can_stats.bus_off++;
692 /* propagate the error condition to the CAN stack */
693 skb = alloc_can_err_skb(dev, &cf);
697 __m_can_get_berr_counter(dev, &bec);
700 case CAN_STATE_ERROR_WARNING:
701 /* error warning state */
702 cf->can_id |= CAN_ERR_CRTL;
703 cf->data[1] = (bec.txerr > bec.rxerr) ?
704 CAN_ERR_CRTL_TX_WARNING :
705 CAN_ERR_CRTL_RX_WARNING;
706 cf->data[6] = bec.txerr;
707 cf->data[7] = bec.rxerr;
709 case CAN_STATE_ERROR_PASSIVE:
710 /* error passive state */
711 cf->can_id |= CAN_ERR_CRTL;
712 ecr = m_can_read(priv, M_CAN_ECR);
714 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
716 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
717 cf->data[6] = bec.txerr;
718 cf->data[7] = bec.rxerr;
720 case CAN_STATE_BUS_OFF:
722 cf->can_id |= CAN_ERR_BUSOFF;
729 stats->rx_bytes += cf->can_dlc;
730 netif_receive_skb(skb);
735 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
737 struct m_can_priv *priv = netdev_priv(dev);
740 if ((psr & PSR_EW) &&
741 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
742 netdev_dbg(dev, "entered error warning state\n");
743 work_done += m_can_handle_state_change(dev,
744 CAN_STATE_ERROR_WARNING);
747 if ((psr & PSR_EP) &&
748 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
749 netdev_dbg(dev, "entered error passive state\n");
750 work_done += m_can_handle_state_change(dev,
751 CAN_STATE_ERROR_PASSIVE);
754 if ((psr & PSR_BO) &&
755 (priv->can.state != CAN_STATE_BUS_OFF)) {
756 netdev_dbg(dev, "entered error bus off state\n");
757 work_done += m_can_handle_state_change(dev,
764 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
766 if (irqstatus & IR_WDI)
767 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
768 if (irqstatus & IR_ELO)
769 netdev_err(dev, "Error Logging Overflow\n");
770 if (irqstatus & IR_BEU)
771 netdev_err(dev, "Bit Error Uncorrected\n");
772 if (irqstatus & IR_BEC)
773 netdev_err(dev, "Bit Error Corrected\n");
774 if (irqstatus & IR_TOO)
775 netdev_err(dev, "Timeout reached\n");
776 if (irqstatus & IR_MRAF)
777 netdev_err(dev, "Message RAM access failure occurred\n");
780 static inline bool is_lec_err(u32 psr)
784 return psr && (psr != LEC_UNUSED);
787 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
790 struct m_can_priv *priv = netdev_priv(dev);
793 if (irqstatus & IR_RF0L)
794 work_done += m_can_handle_lost_msg(dev);
796 /* handle lec errors on the bus */
797 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
799 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
801 /* other unproccessed error interrupts */
802 m_can_handle_other_err(dev, irqstatus);
807 static int m_can_poll(struct napi_struct *napi, int quota)
809 struct net_device *dev = napi->dev;
810 struct m_can_priv *priv = netdev_priv(dev);
814 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
818 /* Errata workaround for issue "Needless activation of MRAF irq"
819 * During frame reception while the MCAN is in Error Passive state
820 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
821 * it may happen that MCAN_IR.MRAF is set although there was no
822 * Message RAM access failure.
823 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
824 * The Message RAM Access Failure interrupt routine needs to check
825 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
826 * In this case, reset MCAN_IR.MRAF. No further action is required.
828 if ((priv->version <= 31) && (irqstatus & IR_MRAF) &&
829 (m_can_read(priv, M_CAN_ECR) & ECR_RP)) {
830 struct can_berr_counter bec;
832 __m_can_get_berr_counter(dev, &bec);
833 if (bec.rxerr == 127) {
834 m_can_write(priv, M_CAN_IR, IR_MRAF);
835 irqstatus &= ~IR_MRAF;
839 psr = m_can_read(priv, M_CAN_PSR);
840 if (irqstatus & IR_ERR_STATE)
841 work_done += m_can_handle_state_errors(dev, psr);
843 if (irqstatus & IR_ERR_BUS_30X)
844 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
846 if (irqstatus & IR_RF0N)
847 work_done += m_can_do_rx_poll(dev, (quota - work_done));
849 if (work_done < quota) {
850 napi_complete_done(napi, work_done);
851 m_can_enable_all_interrupts(priv);
858 static void m_can_echo_tx_event(struct net_device *dev)
864 unsigned int msg_mark;
866 struct m_can_priv *priv = netdev_priv(dev);
867 struct net_device_stats *stats = &dev->stats;
869 /* read tx event fifo status */
870 m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
872 /* Get Tx Event fifo element count */
873 txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
876 /* Get and process all sent elements */
877 for (i = 0; i < txe_count; i++) {
878 /* retrieve get index */
879 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
882 /* get message marker */
883 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
884 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
886 /* ack txe element */
887 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
888 (fgi << TXEFA_EFAI_SHIFT)));
891 stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
896 static irqreturn_t m_can_isr(int irq, void *dev_id)
898 struct net_device *dev = (struct net_device *)dev_id;
899 struct m_can_priv *priv = netdev_priv(dev);
900 struct net_device_stats *stats = &dev->stats;
903 ir = m_can_read(priv, M_CAN_IR);
909 m_can_write(priv, M_CAN_IR, ir);
911 /* schedule NAPI in case of
914 * - bus error IRQ and bus error reporting
916 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
917 priv->irqstatus = ir;
918 m_can_disable_all_interrupts(priv);
919 napi_schedule(&priv->napi);
922 if (priv->version == 30) {
924 /* Transmission Complete Interrupt*/
925 stats->tx_bytes += can_get_echo_skb(dev, 0);
927 can_led_event(dev, CAN_LED_EVENT_TX);
928 netif_wake_queue(dev);
932 /* New TX FIFO Element arrived */
933 m_can_echo_tx_event(dev);
934 can_led_event(dev, CAN_LED_EVENT_TX);
935 if (netif_queue_stopped(dev) &&
936 !m_can_tx_fifo_full(priv))
937 netif_wake_queue(dev);
944 static const struct can_bittiming_const m_can_bittiming_const_30X = {
945 .name = KBUILD_MODNAME,
946 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
948 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
956 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
957 .name = KBUILD_MODNAME,
958 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
960 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
968 static const struct can_bittiming_const m_can_bittiming_const_31X = {
969 .name = KBUILD_MODNAME,
970 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
972 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */
980 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
981 .name = KBUILD_MODNAME,
982 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
984 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
992 static int m_can_set_bittiming(struct net_device *dev)
994 struct m_can_priv *priv = netdev_priv(dev);
995 const struct can_bittiming *bt = &priv->can.bittiming;
996 const struct can_bittiming *dbt = &priv->can.data_bittiming;
997 u16 brp, sjw, tseg1, tseg2;
1002 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1003 tseg2 = bt->phase_seg2 - 1;
1004 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
1005 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
1006 m_can_write(priv, M_CAN_NBTP, reg_btp);
1008 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1011 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1012 tseg2 = dbt->phase_seg2 - 1;
1013 reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
1014 (tseg1 << DBTP_DTSEG1_SHIFT) |
1015 (tseg2 << DBTP_DTSEG2_SHIFT);
1016 m_can_write(priv, M_CAN_DBTP, reg_btp);
1022 /* Configure M_CAN chip:
1023 * - set rx buffer/fifo element size
1024 * - configure rx fifo
1025 * - accept non-matching frame into fifo 0
1026 * - configure tx buffer
1027 * - >= v3.1.x: TX FIFO is used
1031 static void m_can_chip_config(struct net_device *dev)
1033 struct m_can_priv *priv = netdev_priv(dev);
1036 m_can_config_endisable(priv, true);
1038 /* RX Buffer/FIFO Element Size 64 bytes data field */
1039 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
1041 /* Accept Non-matching Frames Into FIFO 0 */
1042 m_can_write(priv, M_CAN_GFC, 0x0);
1044 if (priv->version == 30) {
1045 /* only support one Tx Buffer currently */
1046 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
1047 priv->mcfg[MRAM_TXB].off);
1049 /* TX FIFO is used for newer IP Core versions */
1050 m_can_write(priv, M_CAN_TXBC,
1051 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
1052 (priv->mcfg[MRAM_TXB].off));
1055 /* support 64 bytes payload */
1056 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
1059 if (priv->version == 30) {
1060 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
1061 priv->mcfg[MRAM_TXE].off);
1063 /* Full TX Event FIFO is used */
1064 m_can_write(priv, M_CAN_TXEFC,
1065 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1067 priv->mcfg[MRAM_TXE].off);
1070 /* rx fifo configuration, blocking mode, fifo size 1 */
1071 m_can_write(priv, M_CAN_RXF0C,
1072 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
1073 priv->mcfg[MRAM_RXF0].off);
1075 m_can_write(priv, M_CAN_RXF1C,
1076 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
1077 priv->mcfg[MRAM_RXF1].off);
1079 cccr = m_can_read(priv, M_CAN_CCCR);
1080 test = m_can_read(priv, M_CAN_TEST);
1082 if (priv->version == 30) {
1085 cccr &= ~(CCCR_TEST | CCCR_MON |
1086 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
1087 (CCCR_CME_MASK << CCCR_CME_SHIFT));
1089 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1090 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1093 /* Version 3.1.x or 3.2.x */
1094 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1097 /* Only 3.2.x has NISO Bit implemented */
1098 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1101 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1102 cccr |= (CCCR_BRSE | CCCR_FDOE);
1106 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1107 cccr |= CCCR_TEST | CCCR_MON;
1111 /* Enable Monitoring (all versions) */
1112 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1116 m_can_write(priv, M_CAN_CCCR, cccr);
1117 m_can_write(priv, M_CAN_TEST, test);
1119 /* Enable interrupts */
1120 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
1121 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1122 if (priv->version == 30)
1123 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1126 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1129 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
1131 /* route all interrupts to INT0 */
1132 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
1134 /* set bittiming params */
1135 m_can_set_bittiming(dev);
1137 m_can_config_endisable(priv, false);
1140 static void m_can_start(struct net_device *dev)
1142 struct m_can_priv *priv = netdev_priv(dev);
1144 /* basic m_can configuration */
1145 m_can_chip_config(dev);
1147 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1149 m_can_enable_all_interrupts(priv);
1152 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1155 case CAN_MODE_START:
1157 netif_wake_queue(dev);
1166 static void free_m_can_dev(struct net_device *dev)
1171 /* Checks core release number of M_CAN
1172 * returns 0 if an unsupported device is detected
1173 * else it returns the release and step coded as:
1174 * return value = 10 * <release> + 1 * <step>
1176 static int m_can_check_core_release(void __iomem *m_can_base)
1182 struct m_can_priv temp_priv = {
1186 /* Read Core Release Version and split into version number
1187 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1189 crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
1190 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1191 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1194 /* M_CAN v3.x.y: create return value */
1197 /* Unsupported M_CAN version */
1204 /* Selectable Non ISO support only in version 3.2.x
1205 * This function checks if the bit is writable.
1207 static bool m_can_niso_supported(const struct m_can_priv *priv)
1209 u32 cccr_reg, cccr_poll;
1212 m_can_config_endisable(priv, true);
1213 cccr_reg = m_can_read(priv, M_CAN_CCCR);
1214 cccr_reg |= CCCR_NISO;
1215 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1217 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
1218 (cccr_poll == cccr_reg), 0, 10);
1221 cccr_reg &= ~(CCCR_NISO);
1222 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1224 m_can_config_endisable(priv, false);
1226 /* return false if time out (-ETIMEDOUT), else return true */
1227 return !niso_timeout;
1230 static struct net_device *alloc_m_can_dev(struct platform_device *pdev,
1231 void __iomem *addr, u32 tx_fifo_size)
1233 struct net_device *dev;
1234 struct m_can_priv *priv;
1236 unsigned int echo_buffer_count;
1238 m_can_version = m_can_check_core_release(addr);
1239 /* return if unsupported version */
1240 if (!m_can_version) {
1245 /* If version < 3.1.x, then only one echo buffer is used */
1246 echo_buffer_count = ((m_can_version == 30)
1248 : (unsigned int)tx_fifo_size);
1250 dev = alloc_candev(sizeof(*priv), echo_buffer_count);
1255 priv = netdev_priv(dev);
1256 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
1258 /* Shared properties of all M_CAN versions */
1259 priv->version = m_can_version;
1262 priv->can.do_set_mode = m_can_set_mode;
1263 priv->can.do_get_berr_counter = m_can_get_berr_counter;
1265 /* Set M_CAN supported operations */
1266 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1267 CAN_CTRLMODE_LISTENONLY |
1268 CAN_CTRLMODE_BERR_REPORTING |
1271 /* Set properties depending on M_CAN version */
1272 switch (priv->version) {
1274 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1275 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1276 priv->can.bittiming_const = &m_can_bittiming_const_30X;
1277 priv->can.data_bittiming_const =
1278 &m_can_data_bittiming_const_30X;
1281 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1282 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1283 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1284 priv->can.data_bittiming_const =
1285 &m_can_data_bittiming_const_31X;
1288 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1289 priv->can.data_bittiming_const =
1290 &m_can_data_bittiming_const_31X;
1291 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv)
1292 ? CAN_CTRLMODE_FD_NON_ISO
1296 /* Unsupported device: free candev */
1297 free_m_can_dev(dev);
1298 dev_err(&pdev->dev, "Unsupported version number: %2d",
1308 static int m_can_open(struct net_device *dev)
1310 struct m_can_priv *priv = netdev_priv(dev);
1313 err = m_can_clk_start(priv);
1317 /* open the can device */
1318 err = open_candev(dev);
1320 netdev_err(dev, "failed to open can device\n");
1321 goto exit_disable_clks;
1324 /* register interrupt handler */
1325 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1328 netdev_err(dev, "failed to request interrupt\n");
1332 /* start the m_can controller */
1335 can_led_event(dev, CAN_LED_EVENT_OPEN);
1336 napi_enable(&priv->napi);
1337 netif_start_queue(dev);
1344 m_can_clk_stop(priv);
1348 static void m_can_stop(struct net_device *dev)
1350 struct m_can_priv *priv = netdev_priv(dev);
1352 /* disable all interrupts */
1353 m_can_disable_all_interrupts(priv);
1355 /* set the state as STOPPED */
1356 priv->can.state = CAN_STATE_STOPPED;
1359 static int m_can_close(struct net_device *dev)
1361 struct m_can_priv *priv = netdev_priv(dev);
1363 netif_stop_queue(dev);
1364 napi_disable(&priv->napi);
1366 m_can_clk_stop(priv);
1367 free_irq(dev->irq, dev);
1369 can_led_event(dev, CAN_LED_EVENT_STOP);
1374 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1376 struct m_can_priv *priv = netdev_priv(dev);
1377 /*get wrap around for loopback skb index */
1378 unsigned int wrap = priv->can.echo_skb_max;
1381 /* calculate next index */
1382 next_idx = (++putidx >= wrap ? 0 : putidx);
1384 /* check if occupied */
1385 return !!priv->can.echo_skb[next_idx];
1388 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1389 struct net_device *dev)
1391 struct m_can_priv *priv = netdev_priv(dev);
1392 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1393 u32 id, cccr, fdflags;
1397 if (can_dropped_invalid_skb(dev, skb))
1398 return NETDEV_TX_OK;
1400 /* Generate ID field for TX buffer Element */
1401 /* Common to all supported M_CAN versions */
1402 if (cf->can_id & CAN_EFF_FLAG) {
1403 id = cf->can_id & CAN_EFF_MASK;
1406 id = ((cf->can_id & CAN_SFF_MASK) << 18);
1409 if (cf->can_id & CAN_RTR_FLAG)
1412 if (priv->version == 30) {
1413 netif_stop_queue(dev);
1415 /* message ram configuration */
1416 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
1417 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
1418 can_len2dlc(cf->len) << 16);
1420 for (i = 0; i < cf->len; i += 4)
1421 m_can_fifo_write(priv, 0,
1422 M_CAN_FIFO_DATA(i / 4),
1423 *(u32 *)(cf->data + i));
1425 can_put_echo_skb(skb, dev, 0);
1427 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1428 cccr = m_can_read(priv, M_CAN_CCCR);
1429 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1430 if (can_is_canfd_skb(skb)) {
1431 if (cf->flags & CANFD_BRS)
1432 cccr |= CCCR_CMR_CANFD_BRS <<
1435 cccr |= CCCR_CMR_CANFD <<
1438 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1440 m_can_write(priv, M_CAN_CCCR, cccr);
1442 m_can_write(priv, M_CAN_TXBTIE, 0x1);
1443 m_can_write(priv, M_CAN_TXBAR, 0x1);
1444 /* End of xmit function for version 3.0.x */
1446 /* Transmit routine for version >= v3.1.x */
1448 /* Check if FIFO full */
1449 if (m_can_tx_fifo_full(priv)) {
1450 /* This shouldn't happen */
1451 netif_stop_queue(dev);
1453 "TX queue active although FIFO is full.");
1454 return NETDEV_TX_BUSY;
1457 /* get put index for frame */
1458 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1459 >> TXFQS_TFQPI_SHIFT);
1460 /* Write ID Field to FIFO Element */
1461 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
1463 /* get CAN FD configuration of frame */
1465 if (can_is_canfd_skb(skb)) {
1466 fdflags |= TX_BUF_FDF;
1467 if (cf->flags & CANFD_BRS)
1468 fdflags |= TX_BUF_BRS;
1471 /* Construct DLC Field. Also contains CAN-FD configuration
1472 * use put index of fifo as message marker
1473 * it is used in TX interrupt for
1474 * sending the correct echo frame
1476 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
1477 ((putidx << TX_BUF_MM_SHIFT) &
1479 (can_len2dlc(cf->len) << 16) |
1480 fdflags | TX_BUF_EFC);
1482 for (i = 0; i < cf->len; i += 4)
1483 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
1484 *(u32 *)(cf->data + i));
1486 /* Push loopback echo.
1487 * Will be looped back on TX interrupt based on message marker
1489 can_put_echo_skb(skb, dev, putidx);
1491 /* Enable TX FIFO element to start transfer */
1492 m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
1494 /* stop network queue if fifo full */
1495 if (m_can_tx_fifo_full(priv) ||
1496 m_can_next_echo_skb_occupied(dev, putidx))
1497 netif_stop_queue(dev);
1500 return NETDEV_TX_OK;
1503 static const struct net_device_ops m_can_netdev_ops = {
1504 .ndo_open = m_can_open,
1505 .ndo_stop = m_can_close,
1506 .ndo_start_xmit = m_can_start_xmit,
1507 .ndo_change_mtu = can_change_mtu,
1510 static int register_m_can_dev(struct net_device *dev)
1512 dev->flags |= IFF_ECHO; /* we support local echo */
1513 dev->netdev_ops = &m_can_netdev_ops;
1515 return register_candev(dev);
1518 static void m_can_init_ram(struct m_can_priv *priv)
1522 /* initialize the entire Message RAM in use to avoid possible
1523 * ECC/parity checksum errors when reading an uninitialized buffer
1525 start = priv->mcfg[MRAM_SIDF].off;
1526 end = priv->mcfg[MRAM_TXB].off +
1527 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1528 for (i = start; i < end; i += 4)
1529 writel(0x0, priv->mram_base + i);
1532 static void m_can_of_parse_mram(struct m_can_priv *priv,
1533 const u32 *mram_config_vals)
1535 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1536 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1537 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1538 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1539 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1540 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1541 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1542 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1543 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1544 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1545 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1546 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1547 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1548 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1549 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1550 priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
1551 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1552 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1553 priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
1554 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1555 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1556 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1557 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
1559 dev_dbg(priv->device,
1560 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1562 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1563 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1564 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1565 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1566 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1567 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1568 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1570 m_can_init_ram(priv);
1573 static int m_can_plat_probe(struct platform_device *pdev)
1575 struct net_device *dev;
1576 struct m_can_priv *priv;
1577 struct resource *res;
1579 void __iomem *mram_addr;
1580 struct clk *hclk, *cclk;
1582 struct device_node *np;
1583 u32 mram_config_vals[MRAM_CFG_LEN];
1586 np = pdev->dev.of_node;
1588 hclk = devm_clk_get(&pdev->dev, "hclk");
1589 cclk = devm_clk_get(&pdev->dev, "cclk");
1591 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1592 dev_err(&pdev->dev, "no clock found\n");
1597 /* Enable clocks. Necessary to read Core Release in order to determine
1600 ret = clk_prepare_enable(hclk);
1602 goto disable_hclk_ret;
1604 ret = clk_prepare_enable(cclk);
1606 goto disable_cclk_ret;
1608 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1609 addr = devm_ioremap_resource(&pdev->dev, res);
1610 irq = platform_get_irq_byname(pdev, "int0");
1612 if (IS_ERR(addr) || irq < 0) {
1614 goto disable_cclk_ret;
1617 /* message ram could be shared */
1618 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1621 goto disable_cclk_ret;
1624 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1627 goto disable_cclk_ret;
1630 /* get message ram configuration */
1631 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1633 sizeof(mram_config_vals) / 4);
1635 dev_err(&pdev->dev, "Could not get Message RAM configuration.");
1636 goto disable_cclk_ret;
1640 * Defines the total amount of echo buffers for loopback
1642 tx_fifo_size = mram_config_vals[7];
1644 /* allocate the m_can device */
1645 dev = alloc_m_can_dev(pdev, addr, tx_fifo_size);
1648 goto disable_cclk_ret;
1650 priv = netdev_priv(dev);
1652 priv->device = &pdev->dev;
1655 priv->can.clock.freq = clk_get_rate(cclk);
1656 priv->mram_base = mram_addr;
1658 platform_set_drvdata(pdev, dev);
1659 SET_NETDEV_DEV(dev, &pdev->dev);
1661 ret = register_m_can_dev(dev);
1663 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1664 KBUILD_MODNAME, ret);
1665 goto failed_free_dev;
1668 m_can_of_parse_mram(priv, mram_config_vals);
1670 devm_can_led_init(dev);
1672 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
1673 KBUILD_MODNAME, dev->irq, priv->version);
1676 * Stop clocks. They will be reactivated once the M_CAN device is opened
1679 goto disable_cclk_ret;
1682 free_m_can_dev(dev);
1684 clk_disable_unprepare(cclk);
1686 clk_disable_unprepare(hclk);
1691 /* TODO: runtime PM with power down or sleep mode */
1693 static __maybe_unused int m_can_suspend(struct device *dev)
1695 struct net_device *ndev = dev_get_drvdata(dev);
1696 struct m_can_priv *priv = netdev_priv(ndev);
1698 if (netif_running(ndev)) {
1699 netif_stop_queue(ndev);
1700 netif_device_detach(ndev);
1702 m_can_clk_stop(priv);
1705 pinctrl_pm_select_sleep_state(dev);
1707 priv->can.state = CAN_STATE_SLEEPING;
1712 static __maybe_unused int m_can_resume(struct device *dev)
1714 struct net_device *ndev = dev_get_drvdata(dev);
1715 struct m_can_priv *priv = netdev_priv(ndev);
1717 pinctrl_pm_select_default_state(dev);
1719 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1721 if (netif_running(ndev)) {
1724 ret = m_can_clk_start(priv);
1728 m_can_init_ram(priv);
1730 netif_device_attach(ndev);
1731 netif_start_queue(ndev);
1737 static void unregister_m_can_dev(struct net_device *dev)
1739 unregister_candev(dev);
1742 static int m_can_plat_remove(struct platform_device *pdev)
1744 struct net_device *dev = platform_get_drvdata(pdev);
1746 unregister_m_can_dev(dev);
1747 platform_set_drvdata(pdev, NULL);
1749 free_m_can_dev(dev);
1754 static const struct dev_pm_ops m_can_pmops = {
1755 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1758 static const struct of_device_id m_can_of_table[] = {
1759 { .compatible = "bosch,m_can", .data = NULL },
1762 MODULE_DEVICE_TABLE(of, m_can_of_table);
1764 static struct platform_driver m_can_plat_driver = {
1766 .name = KBUILD_MODNAME,
1767 .of_match_table = m_can_of_table,
1770 .probe = m_can_plat_probe,
1771 .remove = m_can_plat_remove,
1774 module_platform_driver(m_can_plat_driver);
1776 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1777 MODULE_LICENSE("GPL v2");
1778 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");