1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 /* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved.
3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.25)
5 * - PEAK linux canfd driver
6 * - Altera Avalon EPCS flash controller driver
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/device.h>
12 #include <linux/pci.h>
13 #include <linux/can/dev.h>
14 #include <linux/timer.h>
15 #include <linux/netdevice.h>
16 #include <linux/crc32.h>
17 #include <linux/iopoll.h>
19 MODULE_LICENSE("Dual BSD/GPL");
20 MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
21 MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
23 #define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd"
25 #define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
26 #define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
27 #define KVASER_PCIEFD_MAX_ERR_REP 256
28 #define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17
29 #define KVASER_PCIEFD_MAX_CAN_CHANNELS 4
30 #define KVASER_PCIEFD_DMA_COUNT 2
32 #define KVASER_PCIEFD_DMA_SIZE (4 * 1024)
33 #define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
35 #define KVASER_PCIEFD_VENDOR 0x1a07
36 #define KVASER_PCIEFD_4HS_ID 0x0d
37 #define KVASER_PCIEFD_2HS_ID 0x0e
38 #define KVASER_PCIEFD_HS_ID 0x0f
39 #define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10
40 #define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11
42 /* PCIe IRQ registers */
43 #define KVASER_PCIEFD_IRQ_REG 0x40
44 #define KVASER_PCIEFD_IEN_REG 0x50
46 #define KVASER_PCIEFD_DMA_MAP_BASE 0x1000
47 /* Kvaser KCAN CAN controller registers */
48 #define KVASER_PCIEFD_KCAN0_BASE 0x10000
49 #define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
50 #define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
51 #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
52 #define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
53 #define KVASER_PCIEFD_KCAN_CMD_REG 0x400
54 #define KVASER_PCIEFD_KCAN_IEN_REG 0x408
55 #define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
56 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414
57 #define KVASER_PCIEFD_KCAN_STAT_REG 0x418
58 #define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
59 #define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
60 #define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
61 #define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
62 #define KVASER_PCIEFD_KCAN_PWM_REG 0x430
63 /* Loopback control register */
64 #define KVASER_PCIEFD_LOOP_REG 0x1f000
65 /* System identification and information registers */
66 #define KVASER_PCIEFD_SYSID_BASE 0x1f020
67 #define KVASER_PCIEFD_SYSID_VERSION_REG (KVASER_PCIEFD_SYSID_BASE + 0x8)
68 #define KVASER_PCIEFD_SYSID_CANFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0xc)
69 #define KVASER_PCIEFD_SYSID_BUSFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0x10)
70 #define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)
71 /* Shared receive buffer registers */
72 #define KVASER_PCIEFD_SRB_BASE 0x1f200
73 #define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)
74 #define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)
75 #define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)
76 #define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
77 #define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
78 /* EPCS flash controller registers */
79 #define KVASER_PCIEFD_SPI_BASE 0x1fc00
80 #define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE
81 #define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4)
82 #define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8)
83 #define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc)
84 #define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14)
86 #define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f
87 #define KVASER_PCIEFD_IRQ_SRB BIT(4)
89 #define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24
90 #define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16
91 #define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1
93 /* Reset DMA buffer 0, 1 and FIFO offset */
94 #define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
95 #define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
96 #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
98 /* DMA packet done, buffer 0 and 1 */
99 #define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
100 #define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
101 /* DMA overflow, buffer 0 and 1 */
102 #define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
103 #define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
104 /* DMA underflow, buffer 0 and 1 */
105 #define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
106 #define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
109 #define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
111 #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
114 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
116 /* EPCS flash controller definitions */
117 #define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024)
118 #define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L)
119 #define KVASER_PCIEFD_CFG_MAX_PARAMS 256
120 #define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d
121 #define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24
122 #define KVASER_PCIEFD_CFG_SYS_VER 1
123 #define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130
124 #define KVASER_PCIEFD_SPI_TMT BIT(5)
125 #define KVASER_PCIEFD_SPI_TRDY BIT(6)
126 #define KVASER_PCIEFD_SPI_RRDY BIT(7)
127 #define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14
128 /* Commands for controlling the onboard flash */
129 #define KVASER_PCIEFD_FLASH_RES_CMD 0xab
130 #define KVASER_PCIEFD_FLASH_READ_CMD 0x3
131 #define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5
133 /* Kvaser KCAN definitions */
134 #define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
135 #define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
137 #define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
138 /* Request status packet */
139 #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
140 /* Abort, flush and reset */
141 #define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
143 /* Tx FIFO unaligned read */
144 #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
145 /* Tx FIFO unaligned end */
146 #define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
147 /* Bus parameter protection error */
148 #define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
149 /* FDF bit when controller is in classic mode */
150 #define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
151 /* Rx FIFO overflow */
152 #define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
154 #define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
155 /* Tx buffer flush done */
156 #define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
157 /* Tx FIFO overflow */
158 #define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
160 #define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
161 /* Transmitter unaligned */
162 #define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
164 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16
166 #define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24
168 #define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
169 /* Idle state. Controller in reset mode and no abort or flush pending */
170 #define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
172 #define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
173 /* Reset mode request */
174 #define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
175 /* Controller in reset mode */
176 #define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
177 /* Controller got one-shot capability */
178 #define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
179 /* Controller got CAN FD capability */
180 #define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
181 #define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \
182 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \
183 KVASER_PCIEFD_KCAN_STAT_IRM)
186 #define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
187 /* Listen only mode */
188 #define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
189 /* Error packet enable */
190 #define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
192 #define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
193 /* Acknowledgment packet type */
194 #define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
195 /* Active error flag enable. Clear to force error passive */
196 #define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
197 /* Classic CAN mode */
198 #define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
200 #define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13
201 #define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17
202 #define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26
204 #define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16
206 /* Kvaser KCAN packet types */
207 #define KVASER_PCIEFD_PACK_TYPE_DATA 0
208 #define KVASER_PCIEFD_PACK_TYPE_ACK 1
209 #define KVASER_PCIEFD_PACK_TYPE_TXRQ 2
210 #define KVASER_PCIEFD_PACK_TYPE_ERROR 3
211 #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4
212 #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5
213 #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6
214 #define KVASER_PCIEFD_PACK_TYPE_STATUS 8
215 #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9
217 /* Kvaser KCAN packet common definitions */
218 #define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff
219 #define KVASER_PCIEFD_PACKET_CHID_SHIFT 25
220 #define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28
222 /* Kvaser KCAN TDATA and RDATA first word */
223 #define KVASER_PCIEFD_RPACKET_IDE BIT(30)
224 #define KVASER_PCIEFD_RPACKET_RTR BIT(29)
225 /* Kvaser KCAN TDATA and RDATA second word */
226 #define KVASER_PCIEFD_RPACKET_ESI BIT(13)
227 #define KVASER_PCIEFD_RPACKET_BRS BIT(14)
228 #define KVASER_PCIEFD_RPACKET_FDF BIT(15)
229 #define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
230 /* Kvaser KCAN TDATA second word */
231 #define KVASER_PCIEFD_TPACKET_SMS BIT(16)
232 #define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
234 /* Kvaser KCAN APACKET */
235 #define KVASER_PCIEFD_APACKET_FLU BIT(8)
236 #define KVASER_PCIEFD_APACKET_CT BIT(9)
237 #define KVASER_PCIEFD_APACKET_ABL BIT(10)
238 #define KVASER_PCIEFD_APACKET_NACK BIT(11)
240 /* Kvaser KCAN SPACK first word */
241 #define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
242 #define KVASER_PCIEFD_SPACK_BOFF BIT(16)
243 #define KVASER_PCIEFD_SPACK_IDET BIT(20)
244 #define KVASER_PCIEFD_SPACK_IRM BIT(21)
245 #define KVASER_PCIEFD_SPACK_RMCD BIT(22)
246 /* Kvaser KCAN SPACK second word */
247 #define KVASER_PCIEFD_SPACK_AUTO BIT(21)
248 #define KVASER_PCIEFD_SPACK_EWLR BIT(23)
249 #define KVASER_PCIEFD_SPACK_EPLR BIT(24)
251 /* Kvaser KCAN_EPACK second word */
252 #define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
254 struct kvaser_pciefd;
256 struct kvaser_pciefd_can {
258 struct kvaser_pciefd *kv_pcie;
259 void __iomem *reg_base;
260 struct can_berr_counter bec;
264 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */
265 spinlock_t echo_lock; /* Locks the message echo buffer */
266 struct timer_list bec_poll_timer;
267 struct completion start_comp, flush_comp;
270 struct kvaser_pciefd {
272 void __iomem *reg_base;
273 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS];
274 void *dma_data[KVASER_PCIEFD_DMA_COUNT];
278 u32 freq_to_ticks_div;
281 struct kvaser_pciefd_rx_packet {
286 struct kvaser_pciefd_tx_packet {
291 static const struct can_bittiming_const kvaser_pciefd_bittiming_const = {
292 .name = KVASER_PCIEFD_DRV_NAME,
303 struct kvaser_pciefd_cfg_param {
307 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ];
310 struct kvaser_pciefd_cfg_img {
314 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS];
317 static struct pci_device_id kvaser_pciefd_id_table[] = {
318 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), },
319 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), },
320 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), },
321 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), },
322 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), },
325 MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
327 /* Onboard flash memory functions */
328 static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
333 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
334 res, res & msk, 0, 10);
339 static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx,
340 u32 tx_len, u8 *rx, u32 rx_len)
344 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
345 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
346 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
350 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
353 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
355 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
358 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
363 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
366 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
368 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
371 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
374 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
377 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
380 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
387 static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
388 struct kvaser_pciefd_cfg_img *img)
390 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET;
395 KVASER_PCIEFD_FLASH_READ_CMD,
396 (u8)((offset >> 16) & 0xff),
397 (u8)((offset >> 8) & 0xff),
401 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
402 KVASER_PCIEFD_CFG_IMG_SZ);
406 crc_buff = (u8 *)img->params;
408 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) {
409 dev_err(&pcie->pci->dev,
410 "Config flash corrupted, version number is wrong\n");
414 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) {
415 dev_err(&pcie->pci->dev,
416 "Config flash corrupted, magic number is wrong\n");
420 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params));
421 if (le32_to_cpu(img->crc) != crc) {
422 dev_err(&pcie->pci->dev,
423 "Stored CRC does not match flash image contents\n");
430 static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
431 struct kvaser_pciefd_cfg_img *img)
433 struct kvaser_pciefd_cfg_param *param;
435 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN];
436 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
439 static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)
442 struct kvaser_pciefd_cfg_img *img;
444 /* Read electronic signature */
445 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0};
447 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
451 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL);
455 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) {
456 dev_err(&pcie->pci->dev,
457 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n",
458 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16);
464 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD;
465 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
468 } else if (cmd[0] & 1) {
470 /* No write is ever done, the WIP should never be set */
471 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
475 res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
481 kvaser_pciefd_cfg_read_params(pcie, img);
488 static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
492 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
493 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
494 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
497 static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
502 spin_lock_irqsave(&can->lock, irq);
503 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
504 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) {
505 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
506 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
508 spin_unlock_irqrestore(&can->lock, irq);
511 static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can)
516 spin_lock_irqsave(&can->lock, irq);
517 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
518 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN;
519 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
520 spin_unlock_irqrestore(&can->lock, irq);
523 static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
527 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF |
528 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
529 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
530 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
531 KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD;
533 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
538 static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
543 spin_lock_irqsave(&can->lock, irq);
545 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
546 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
547 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
548 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
549 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN;
551 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
553 mode |= KVASER_PCIEFD_KCAN_MODE_CCM;
554 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
557 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
558 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
560 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
561 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
562 /* Use ACK packet type */
563 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT;
564 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
565 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
567 spin_unlock_irqrestore(&can->lock, irq);
570 static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
575 spin_lock_irqsave(&can->lock, irq);
576 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
577 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,
578 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
580 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
581 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
584 /* If controller is already idle, run abort, flush and reset */
585 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
586 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
587 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
588 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
591 /* Put controller in reset mode */
592 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
593 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
594 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
597 spin_unlock_irqrestore(&can->lock, irq);
600 static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
605 del_timer(&can->bec_poll_timer);
607 if (!completion_done(&can->flush_comp))
608 kvaser_pciefd_start_controller_flush(can);
610 if (!wait_for_completion_timeout(&can->flush_comp,
611 KVASER_PCIEFD_WAIT_TIMEOUT)) {
612 netdev_err(can->can.dev, "Timeout during bus on flush\n");
616 spin_lock_irqsave(&can->lock, irq);
617 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
618 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
620 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,
621 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
623 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
624 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
625 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
626 spin_unlock_irqrestore(&can->lock, irq);
628 if (!wait_for_completion_timeout(&can->start_comp,
629 KVASER_PCIEFD_WAIT_TIMEOUT)) {
630 netdev_err(can->can.dev, "Timeout during bus on reset\n");
633 /* Reset interrupt handling */
634 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
635 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
637 kvaser_pciefd_set_tx_irq(can);
638 kvaser_pciefd_setup_controller(can);
640 can->can.state = CAN_STATE_ERROR_ACTIVE;
641 netif_wake_queue(can->can.dev);
644 can->err_rep_cnt = 0;
649 static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
655 spin_lock_irqsave(&can->lock, irq);
656 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
657 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;
659 /* Set duty cycle to zero */
661 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
662 spin_unlock_irqrestore(&can->lock, irq);
665 static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
671 kvaser_pciefd_pwm_stop(can);
672 spin_lock_irqsave(&can->lock, irq);
674 /* Set frequency to 500 KHz*/
675 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
677 pwm_ctrl = top & 0xff;
678 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
679 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
681 /* Set duty cycle to 95 */
682 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
683 pwm_ctrl = trigger & 0xff;
684 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
685 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
686 spin_unlock_irqrestore(&can->lock, irq);
689 static int kvaser_pciefd_open(struct net_device *netdev)
692 struct kvaser_pciefd_can *can = netdev_priv(netdev);
694 err = open_candev(netdev);
698 err = kvaser_pciefd_bus_on(can);
700 close_candev(netdev);
707 static int kvaser_pciefd_stop(struct net_device *netdev)
709 struct kvaser_pciefd_can *can = netdev_priv(netdev);
712 /* Don't interrupt ongoing flush */
713 if (!completion_done(&can->flush_comp))
714 kvaser_pciefd_start_controller_flush(can);
716 if (!wait_for_completion_timeout(&can->flush_comp,
717 KVASER_PCIEFD_WAIT_TIMEOUT)) {
718 netdev_err(can->can.dev, "Timeout during stop\n");
721 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
722 del_timer(&can->bec_poll_timer);
724 close_candev(netdev);
729 static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
730 struct kvaser_pciefd_can *can,
733 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
735 int seq = can->echo_idx;
737 memset(p, 0, sizeof(*p));
739 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
740 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
742 if (cf->can_id & CAN_RTR_FLAG)
743 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;
745 if (cf->can_id & CAN_EFF_FLAG)
746 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
748 p->header[0] |= cf->can_id & CAN_EFF_MASK;
749 p->header[1] |= can_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
750 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
752 if (can_is_canfd_skb(skb)) {
753 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
754 if (cf->flags & CANFD_BRS)
755 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
756 if (cf->flags & CANFD_ESI)
757 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
760 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;
762 packet_size = cf->len;
763 memcpy(p->data, cf->data, packet_size);
765 return DIV_ROUND_UP(packet_size, 4);
768 static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
769 struct net_device *netdev)
771 struct kvaser_pciefd_can *can = netdev_priv(netdev);
772 unsigned long irq_flags;
773 struct kvaser_pciefd_tx_packet packet;
777 if (can_dropped_invalid_skb(netdev, skb))
780 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
782 spin_lock_irqsave(&can->echo_lock, irq_flags);
784 /* Prepare and save echo skb in internal slot */
785 can_put_echo_skb(skb, netdev, can->echo_idx);
787 /* Move echo index to the next slot */
788 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max;
790 /* Write header to fifo */
791 iowrite32(packet.header[0],
792 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
793 iowrite32(packet.header[1],
794 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
797 u32 data_last = ((u32 *)packet.data)[nwords - 1];
799 /* Write data to fifo, except last word */
800 iowrite32_rep(can->reg_base +
801 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
803 /* Write last word to end of fifo */
804 __raw_writel(data_last, can->reg_base +
805 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
807 /* Complete write to fifo */
808 __raw_writel(0, can->reg_base +
809 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
812 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
813 /* No room for a new message, stop the queue until at least one
814 * successful transmit
816 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT ||
817 can->can.echo_skb[can->echo_idx])
818 netif_stop_queue(netdev);
820 spin_unlock_irqrestore(&can->echo_lock, irq_flags);
825 static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
827 u32 mode, test, btrn;
828 unsigned long irq_flags;
830 struct can_bittiming *bt;
833 bt = &can->can.data_bittiming;
835 bt = &can->can.bittiming;
837 btrn = ((bt->phase_seg2 - 1) & 0x1f) <<
838 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT |
839 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<
840 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT |
841 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT |
842 ((bt->brp - 1) & 0x1fff);
844 spin_lock_irqsave(&can->lock, irq_flags);
845 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
847 /* Put the circuit in reset mode */
848 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
849 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
851 /* Can only set bittiming if in reset mode */
852 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
853 test, test & KVASER_PCIEFD_KCAN_MODE_RM,
857 spin_unlock_irqrestore(&can->lock, irq_flags);
862 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
864 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
866 /* Restore previous reset mode status */
867 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
869 spin_unlock_irqrestore(&can->lock, irq_flags);
873 static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev)
875 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false);
878 static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev)
880 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true);
883 static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode)
885 struct kvaser_pciefd_can *can = netdev_priv(ndev);
890 if (!can->can.restart_ms)
891 ret = kvaser_pciefd_bus_on(can);
900 static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev,
901 struct can_berr_counter *bec)
903 struct kvaser_pciefd_can *can = netdev_priv(ndev);
905 bec->rxerr = can->bec.rxerr;
906 bec->txerr = can->bec.txerr;
910 static void kvaser_pciefd_bec_poll_timer(struct timer_list *data)
912 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer);
914 kvaser_pciefd_enable_err_gen(can);
915 kvaser_pciefd_request_status(can);
916 can->err_rep_cnt = 0;
919 static const struct net_device_ops kvaser_pciefd_netdev_ops = {
920 .ndo_open = kvaser_pciefd_open,
921 .ndo_stop = kvaser_pciefd_stop,
922 .ndo_start_xmit = kvaser_pciefd_start_xmit,
923 .ndo_change_mtu = can_change_mtu,
926 static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
930 for (i = 0; i < pcie->nr_channels; i++) {
931 struct net_device *netdev;
932 struct kvaser_pciefd_can *can;
933 u32 status, tx_npackets;
935 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
936 KVASER_PCIEFD_CAN_TX_MAX_COUNT);
940 can = netdev_priv(netdev);
941 netdev->netdev_ops = &kvaser_pciefd_netdev_ops;
942 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
943 i * KVASER_PCIEFD_KCAN_BASE_OFFSET;
947 can->err_rep_cnt = 0;
951 init_completion(&can->start_comp);
952 init_completion(&can->flush_comp);
953 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer,
956 /* Disable Bus load reporting */
957 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
959 tx_npackets = ioread32(can->reg_base +
960 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
961 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &
962 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
963 dev_err(&pcie->pci->dev,
964 "Max Tx count is smaller than expected\n");
970 can->can.clock.freq = pcie->freq;
971 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT;
973 spin_lock_init(&can->echo_lock);
974 spin_lock_init(&can->lock);
975 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
976 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
978 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
979 can->can.do_set_data_bittiming =
980 kvaser_pciefd_set_data_bittiming;
982 can->can.do_set_mode = kvaser_pciefd_set_mode;
983 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
985 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
987 CAN_CTRLMODE_FD_NON_ISO;
989 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
990 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
991 dev_err(&pcie->pci->dev,
992 "CAN FD not supported as expected %d\n", i);
998 if (status & KVASER_PCIEFD_KCAN_STAT_CAP)
999 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
1001 netdev->flags |= IFF_ECHO;
1003 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1005 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1006 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD |
1007 KVASER_PCIEFD_KCAN_IRQ_TFD,
1008 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1011 kvaser_pciefd_pwm_start(can);
1017 static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
1021 for (i = 0; i < pcie->nr_channels; i++) {
1022 int err = register_candev(pcie->can[i]->can.dev);
1027 /* Unregister all successfully registered devices. */
1028 for (j = 0; j < i; j++)
1029 unregister_candev(pcie->can[j]->can.dev);
1037 static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie,
1038 dma_addr_t addr, int offset)
1042 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1043 word1 = addr | KVASER_PCIEFD_64BIT_DMA_BIT;
1049 iowrite32(word1, pcie->reg_base + offset);
1050 iowrite32(word2, pcie->reg_base + offset + 4);
1053 static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1057 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];
1059 /* Disable the DMA */
1060 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1061 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1062 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;
1065 dmam_alloc_coherent(&pcie->pci->dev,
1066 KVASER_PCIEFD_DMA_SIZE,
1070 if (!pcie->dma_data[i] || !dma_addr[i]) {
1071 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1072 KVASER_PCIEFD_DMA_SIZE);
1076 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1079 /* Reset Rx FIFO, and both DMA buffers */
1080 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1081 KVASER_PCIEFD_SRB_CMD_RDB1,
1082 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1084 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1085 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {
1086 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1090 /* Enable the DMA */
1091 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE,
1092 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1097 static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1099 u32 sysid, srb_status, build;
1103 ret = kvaser_pciefd_read_cfg(pcie);
1107 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1108 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff;
1109 if (pcie->nr_channels != sysid_nr_chan) {
1110 dev_err(&pcie->pci->dev,
1111 "Number of channels does not match: %u vs %u\n",
1117 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)
1118 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;
1120 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1121 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
1122 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,
1124 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);
1126 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1127 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1128 dev_err(&pcie->pci->dev,
1129 "Hardware without DMA is not supported\n");
1133 pcie->bus_freq = ioread32(pcie->reg_base +
1134 KVASER_PCIEFD_SYSID_BUSFREQ_REG);
1135 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1136 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1137 if (pcie->freq_to_ticks_div == 0)
1138 pcie->freq_to_ticks_div = 1;
1140 /* Turn off all loopback functionality */
1141 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1145 static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1146 struct kvaser_pciefd_rx_packet *p,
1149 struct sk_buff *skb;
1150 struct canfd_frame *cf;
1151 struct can_priv *priv;
1152 struct net_device_stats *stats;
1153 struct skb_shared_hwtstamps *shhwtstamps;
1154 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1156 if (ch_id >= pcie->nr_channels)
1159 priv = &pcie->can[ch_id]->can;
1160 stats = &priv->dev->stats;
1162 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1163 skb = alloc_canfd_skb(priv->dev, &cf);
1165 stats->rx_dropped++;
1169 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1170 cf->flags |= CANFD_BRS;
1172 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1173 cf->flags |= CANFD_ESI;
1175 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1177 stats->rx_dropped++;
1182 cf->can_id = p->header[0] & CAN_EFF_MASK;
1183 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1184 cf->can_id |= CAN_EFF_FLAG;
1186 cf->len = can_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1188 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR)
1189 cf->can_id |= CAN_RTR_FLAG;
1191 memcpy(cf->data, data, cf->len);
1193 shhwtstamps = skb_hwtstamps(skb);
1195 shhwtstamps->hwtstamp =
1196 ns_to_ktime(div_u64(p->timestamp * 1000,
1197 pcie->freq_to_ticks_div));
1199 stats->rx_bytes += cf->len;
1200 stats->rx_packets++;
1202 return netif_rx(skb);
1205 static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can,
1206 struct can_frame *cf,
1207 enum can_state new_state,
1208 enum can_state tx_state,
1209 enum can_state rx_state)
1211 can_change_state(can->can.dev, cf, tx_state, rx_state);
1213 if (new_state == CAN_STATE_BUS_OFF) {
1214 struct net_device *ndev = can->can.dev;
1215 unsigned long irq_flags;
1217 spin_lock_irqsave(&can->lock, irq_flags);
1218 netif_stop_queue(can->can.dev);
1219 spin_unlock_irqrestore(&can->lock, irq_flags);
1221 /* Prevent CAN controller from auto recover from bus off */
1222 if (!can->can.restart_ms) {
1223 kvaser_pciefd_start_controller_flush(can);
1229 static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p,
1230 struct can_berr_counter *bec,
1231 enum can_state *new_state,
1232 enum can_state *tx_state,
1233 enum can_state *rx_state)
1235 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1236 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1237 *new_state = CAN_STATE_BUS_OFF;
1238 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1239 *new_state = CAN_STATE_BUS_OFF;
1240 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1241 *new_state = CAN_STATE_ERROR_PASSIVE;
1242 else if (bec->txerr >= 128 || bec->rxerr >= 128)
1243 *new_state = CAN_STATE_ERROR_PASSIVE;
1244 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR)
1245 *new_state = CAN_STATE_ERROR_WARNING;
1246 else if (bec->txerr >= 96 || bec->rxerr >= 96)
1247 *new_state = CAN_STATE_ERROR_WARNING;
1249 *new_state = CAN_STATE_ERROR_ACTIVE;
1251 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;
1252 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
1255 static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
1256 struct kvaser_pciefd_rx_packet *p)
1258 struct can_berr_counter bec;
1259 enum can_state old_state, new_state, tx_state, rx_state;
1260 struct net_device *ndev = can->can.dev;
1261 struct sk_buff *skb;
1262 struct can_frame *cf = NULL;
1263 struct skb_shared_hwtstamps *shhwtstamps;
1264 struct net_device_stats *stats = &ndev->stats;
1266 old_state = can->can.state;
1268 bec.txerr = p->header[0] & 0xff;
1269 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1271 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1274 skb = alloc_can_err_skb(ndev, &cf);
1276 if (new_state != old_state) {
1277 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1280 if (old_state == CAN_STATE_BUS_OFF &&
1281 new_state == CAN_STATE_ERROR_ACTIVE &&
1282 can->can.restart_ms) {
1283 can->can.can_stats.restarts++;
1285 cf->can_id |= CAN_ERR_RESTARTED;
1290 can->can.can_stats.bus_error++;
1291 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1296 can->bec.txerr = bec.txerr;
1297 can->bec.rxerr = bec.rxerr;
1300 stats->rx_dropped++;
1304 shhwtstamps = skb_hwtstamps(skb);
1305 shhwtstamps->hwtstamp =
1306 ns_to_ktime(div_u64(p->timestamp * 1000,
1307 can->kv_pcie->freq_to_ticks_div));
1308 cf->can_id |= CAN_ERR_BUSERROR;
1310 cf->data[6] = bec.txerr;
1311 cf->data[7] = bec.rxerr;
1313 stats->rx_packets++;
1314 stats->rx_bytes += cf->can_dlc;
1320 static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1321 struct kvaser_pciefd_rx_packet *p)
1323 struct kvaser_pciefd_can *can;
1324 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1326 if (ch_id >= pcie->nr_channels)
1329 can = pcie->can[ch_id];
1331 kvaser_pciefd_rx_error_frame(can, p);
1332 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1333 /* Do not report more errors, until bec_poll_timer expires */
1334 kvaser_pciefd_disable_err_gen(can);
1335 /* Start polling the error counters */
1336 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1340 static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
1341 struct kvaser_pciefd_rx_packet *p)
1343 struct can_berr_counter bec;
1344 enum can_state old_state, new_state, tx_state, rx_state;
1346 old_state = can->can.state;
1348 bec.txerr = p->header[0] & 0xff;
1349 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1351 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1354 if (new_state != old_state) {
1355 struct net_device *ndev = can->can.dev;
1356 struct sk_buff *skb;
1357 struct can_frame *cf;
1358 struct skb_shared_hwtstamps *shhwtstamps;
1360 skb = alloc_can_err_skb(ndev, &cf);
1362 struct net_device_stats *stats = &ndev->stats;
1364 stats->rx_dropped++;
1368 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1371 if (old_state == CAN_STATE_BUS_OFF &&
1372 new_state == CAN_STATE_ERROR_ACTIVE &&
1373 can->can.restart_ms) {
1374 can->can.can_stats.restarts++;
1375 cf->can_id |= CAN_ERR_RESTARTED;
1378 shhwtstamps = skb_hwtstamps(skb);
1379 shhwtstamps->hwtstamp =
1380 ns_to_ktime(div_u64(p->timestamp * 1000,
1381 can->kv_pcie->freq_to_ticks_div));
1383 cf->data[6] = bec.txerr;
1384 cf->data[7] = bec.rxerr;
1388 can->bec.txerr = bec.txerr;
1389 can->bec.rxerr = bec.rxerr;
1390 /* Check if we need to poll the error counters */
1391 if (bec.txerr || bec.rxerr)
1392 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1397 static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1398 struct kvaser_pciefd_rx_packet *p)
1400 struct kvaser_pciefd_can *can;
1403 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1405 if (ch_id >= pcie->nr_channels)
1408 can = pcie->can[ch_id];
1410 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1411 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;
1413 /* Reset done, start abort and flush */
1414 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1415 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1416 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1417 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1418 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1421 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1422 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1423 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
1424 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
1425 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
1427 iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD,
1428 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1429 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1430 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1431 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1432 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1433 /* Reset detected, send end of flush if no packet are in FIFO */
1434 u8 count = ioread32(can->reg_base +
1435 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1438 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1439 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1440 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1441 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {
1442 /* Response to status request received */
1443 kvaser_pciefd_handle_status_resp(can, p);
1444 if (can->can.state != CAN_STATE_BUS_OFF &&
1445 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1446 mod_timer(&can->bec_poll_timer,
1447 KVASER_PCIEFD_BEC_POLL_FREQ);
1449 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1450 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) {
1451 /* Reset to bus on detected */
1452 if (!completion_done(&can->start_comp))
1453 complete(&can->start_comp);
1459 static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1460 struct kvaser_pciefd_rx_packet *p)
1462 struct kvaser_pciefd_can *can;
1463 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1465 if (ch_id >= pcie->nr_channels)
1468 can = pcie->can[ch_id];
1470 /* If this is the last flushed packet, send end of flush */
1471 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1472 u8 count = ioread32(can->reg_base +
1473 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1476 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1477 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1479 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1480 int dlc = can_get_echo_skb(can->can.dev, echo_idx);
1481 struct net_device_stats *stats = &can->can.dev->stats;
1483 stats->tx_bytes += dlc;
1484 stats->tx_packets++;
1486 if (netif_queue_stopped(can->can.dev))
1487 netif_wake_queue(can->can.dev);
1493 static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1494 struct kvaser_pciefd_rx_packet *p)
1496 struct sk_buff *skb;
1497 struct net_device_stats *stats = &can->can.dev->stats;
1498 struct can_frame *cf;
1500 skb = alloc_can_err_skb(can->can.dev, &cf);
1503 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1505 cf->can_id |= CAN_ERR_LOSTARB;
1506 can->can.can_stats.arbitration_lost++;
1508 cf->can_id |= CAN_ERR_ACK;
1512 cf->can_id |= CAN_ERR_BUSERROR;
1513 stats->rx_bytes += cf->can_dlc;
1514 stats->rx_packets++;
1517 stats->rx_dropped++;
1518 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1522 static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1523 struct kvaser_pciefd_rx_packet *p)
1525 struct kvaser_pciefd_can *can;
1526 bool one_shot_fail = false;
1527 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1529 if (ch_id >= pcie->nr_channels)
1532 can = pcie->can[ch_id];
1533 /* Ignore control packet ACK */
1534 if (p->header[0] & KVASER_PCIEFD_APACKET_CT)
1537 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {
1538 kvaser_pciefd_handle_nack_packet(can, p);
1539 one_shot_fail = true;
1542 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1543 netdev_dbg(can->can.dev, "Packet was flushed\n");
1545 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1546 int dlc = can_get_echo_skb(can->can.dev, echo_idx);
1547 u8 count = ioread32(can->reg_base +
1548 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1550 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&
1551 netif_queue_stopped(can->can.dev))
1552 netif_wake_queue(can->can.dev);
1554 if (!one_shot_fail) {
1555 struct net_device_stats *stats = &can->can.dev->stats;
1557 stats->tx_bytes += dlc;
1558 stats->tx_packets++;
1565 static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1566 struct kvaser_pciefd_rx_packet *p)
1568 struct kvaser_pciefd_can *can;
1569 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1571 if (ch_id >= pcie->nr_channels)
1574 can = pcie->can[ch_id];
1576 if (!completion_done(&can->flush_comp))
1577 complete(&can->flush_comp);
1582 static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1585 __le32 *buffer = pcie->dma_data[dma_buf];
1587 struct kvaser_pciefd_rx_packet packet;
1588 struct kvaser_pciefd_rx_packet *p = &packet;
1590 int pos = *start_pos;
1594 size = le32_to_cpu(buffer[pos++]);
1600 p->header[0] = le32_to_cpu(buffer[pos++]);
1601 p->header[1] = le32_to_cpu(buffer[pos++]);
1603 /* Read 64-bit timestamp */
1604 memcpy(×tamp, &buffer[pos], sizeof(__le64));
1606 p->timestamp = le64_to_cpu(timestamp);
1608 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;
1610 case KVASER_PCIEFD_PACK_TYPE_DATA:
1611 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1612 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1615 data_len = can_dlc2len(p->header[1] >>
1616 KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1617 pos += DIV_ROUND_UP(data_len, 4);
1621 case KVASER_PCIEFD_PACK_TYPE_ACK:
1622 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1625 case KVASER_PCIEFD_PACK_TYPE_STATUS:
1626 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1629 case KVASER_PCIEFD_PACK_TYPE_ERROR:
1630 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1633 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1634 ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1637 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1638 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1641 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1642 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1643 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1644 dev_info(&pcie->pci->dev,
1645 "Received unexpected packet type 0x%08X\n", type);
1649 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1657 /* Position does not point to the end of the package,
1658 * corrupted packet size?
1660 if ((*start_pos + size) != pos)
1663 /* Point to the next packet header, if any */
1669 static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1675 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1676 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);
1681 static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1685 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1686 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
1687 kvaser_pciefd_read_buffer(pcie, 0);
1688 /* Reset DMA buffer 0 */
1689 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1690 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1693 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
1694 kvaser_pciefd_read_buffer(pcie, 1);
1695 /* Reset DMA buffer 1 */
1696 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1697 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1700 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 ||
1701 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 ||
1702 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 ||
1703 irq & KVASER_PCIEFD_SRB_IRQ_DUF1)
1704 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1706 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1710 static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1712 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1714 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)
1715 netdev_err(can->can.dev, "Tx FIFO overflow\n");
1717 if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) {
1718 u8 count = ioread32(can->reg_base +
1719 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1722 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1723 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1726 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)
1727 netdev_err(can->can.dev,
1728 "Fail to change bittiming, when not in reset mode\n");
1730 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC)
1731 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n");
1733 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF)
1734 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1736 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1740 static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
1742 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1746 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1748 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))
1751 if (board_irq & KVASER_PCIEFD_IRQ_SRB)
1752 kvaser_pciefd_receive_irq(pcie);
1754 for (i = 0; i < pcie->nr_channels; i++) {
1755 if (!pcie->can[i]) {
1756 dev_err(&pcie->pci->dev,
1757 "IRQ mask points to unallocated controller\n");
1761 /* Check that mask matches channel (i) IRQ mask */
1762 if (board_irq & (1 << i))
1763 kvaser_pciefd_transmit_irq(pcie->can[i]);
1766 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1770 static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1773 struct kvaser_pciefd_can *can;
1775 for (i = 0; i < pcie->nr_channels; i++) {
1779 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1780 kvaser_pciefd_pwm_stop(can);
1781 free_candev(can->can.dev);
1786 static int kvaser_pciefd_probe(struct pci_dev *pdev,
1787 const struct pci_device_id *id)
1790 struct kvaser_pciefd *pcie;
1792 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1796 pci_set_drvdata(pdev, pcie);
1799 err = pci_enable_device(pdev);
1803 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME);
1805 goto err_disable_pci;
1807 pcie->reg_base = pci_iomap(pdev, 0, 0);
1808 if (!pcie->reg_base) {
1810 goto err_release_regions;
1813 err = kvaser_pciefd_setup_board(pcie);
1815 goto err_pci_iounmap;
1817 err = kvaser_pciefd_setup_dma(pcie);
1819 goto err_pci_iounmap;
1821 pci_set_master(pdev);
1823 err = kvaser_pciefd_setup_can_ctrls(pcie);
1825 goto err_teardown_can_ctrls;
1827 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,
1828 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1830 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 |
1831 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 |
1832 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1833 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1835 /* Reset IRQ handling, expected to be off before */
1836 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1837 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1838 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1839 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1841 /* Ready the DMA buffers */
1842 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1843 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1844 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1845 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1847 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1848 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1850 goto err_teardown_can_ctrls;
1852 err = kvaser_pciefd_reg_candev(pcie);
1859 free_irq(pcie->pci->irq, pcie);
1861 err_teardown_can_ctrls:
1862 kvaser_pciefd_teardown_can_ctrls(pcie);
1863 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1864 pci_clear_master(pdev);
1867 pci_iounmap(pdev, pcie->reg_base);
1869 err_release_regions:
1870 pci_release_regions(pdev);
1873 pci_disable_device(pdev);
1878 static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1880 struct kvaser_pciefd_can *can;
1883 for (i = 0; i < pcie->nr_channels; i++) {
1887 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1888 unregister_candev(can->can.dev);
1889 del_timer(&can->bec_poll_timer);
1890 kvaser_pciefd_pwm_stop(can);
1891 free_candev(can->can.dev);
1896 static void kvaser_pciefd_remove(struct pci_dev *pdev)
1898 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1900 kvaser_pciefd_remove_all_ctrls(pcie);
1902 /* Turn off IRQ generation */
1903 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1904 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1905 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1906 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1908 free_irq(pcie->pci->irq, pcie);
1910 pci_clear_master(pdev);
1911 pci_iounmap(pdev, pcie->reg_base);
1912 pci_release_regions(pdev);
1913 pci_disable_device(pdev);
1916 static struct pci_driver kvaser_pciefd = {
1917 .name = KVASER_PCIEFD_DRV_NAME,
1918 .id_table = kvaser_pciefd_id_table,
1919 .probe = kvaser_pciefd_probe,
1920 .remove = kvaser_pciefd_remove,
1923 module_pci_driver(kvaser_pciefd)