2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
31 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
37 #define DRV_NAME "flexcan"
39 /* 8 for RX fifo and 2 error handling */
40 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
42 /* FLEXCAN module configuration register (CANMCR) bits */
43 #define FLEXCAN_MCR_MDIS BIT(31)
44 #define FLEXCAN_MCR_FRZ BIT(30)
45 #define FLEXCAN_MCR_FEN BIT(29)
46 #define FLEXCAN_MCR_HALT BIT(28)
47 #define FLEXCAN_MCR_NOT_RDY BIT(27)
48 #define FLEXCAN_MCR_WAK_MSK BIT(26)
49 #define FLEXCAN_MCR_SOFTRST BIT(25)
50 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
51 #define FLEXCAN_MCR_SUPV BIT(23)
52 #define FLEXCAN_MCR_SLF_WAK BIT(22)
53 #define FLEXCAN_MCR_WRN_EN BIT(21)
54 #define FLEXCAN_MCR_LPM_ACK BIT(20)
55 #define FLEXCAN_MCR_WAK_SRC BIT(19)
56 #define FLEXCAN_MCR_DOZE BIT(18)
57 #define FLEXCAN_MCR_SRX_DIS BIT(17)
58 #define FLEXCAN_MCR_BCC BIT(16)
59 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
60 #define FLEXCAN_MCR_AEN BIT(12)
61 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
62 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
63 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
64 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
65 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
67 /* FLEXCAN control register (CANCTRL) bits */
68 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
69 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
70 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
71 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
72 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
73 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
74 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
75 #define FLEXCAN_CTRL_LPB BIT(12)
76 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
77 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
78 #define FLEXCAN_CTRL_SMP BIT(7)
79 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
80 #define FLEXCAN_CTRL_TSYN BIT(5)
81 #define FLEXCAN_CTRL_LBUF BIT(4)
82 #define FLEXCAN_CTRL_LOM BIT(3)
83 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
84 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
85 #define FLEXCAN_CTRL_ERR_STATE \
86 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
87 FLEXCAN_CTRL_BOFF_MSK)
88 #define FLEXCAN_CTRL_ERR_ALL \
89 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
91 /* FLEXCAN control register 2 (CTRL2) bits */
92 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
93 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
94 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
95 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
96 #define FLEXCAN_CTRL2_MRP BIT(18)
97 #define FLEXCAN_CTRL2_RRS BIT(17)
98 #define FLEXCAN_CTRL2_EACEN BIT(16)
100 /* FLEXCAN memory error control register (MECR) bits */
101 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
102 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
103 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
104 #define FLEXCAN_MECR_CEI_MSK BIT(16)
105 #define FLEXCAN_MECR_HAERRIE BIT(15)
106 #define FLEXCAN_MECR_FAERRIE BIT(14)
107 #define FLEXCAN_MECR_EXTERRIE BIT(13)
108 #define FLEXCAN_MECR_RERRDIS BIT(9)
109 #define FLEXCAN_MECR_ECCDIS BIT(8)
110 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
112 /* FLEXCAN error and status register (ESR) bits */
113 #define FLEXCAN_ESR_TWRN_INT BIT(17)
114 #define FLEXCAN_ESR_RWRN_INT BIT(16)
115 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
116 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
117 #define FLEXCAN_ESR_ACK_ERR BIT(13)
118 #define FLEXCAN_ESR_CRC_ERR BIT(12)
119 #define FLEXCAN_ESR_FRM_ERR BIT(11)
120 #define FLEXCAN_ESR_STF_ERR BIT(10)
121 #define FLEXCAN_ESR_TX_WRN BIT(9)
122 #define FLEXCAN_ESR_RX_WRN BIT(8)
123 #define FLEXCAN_ESR_IDLE BIT(7)
124 #define FLEXCAN_ESR_TXRX BIT(6)
125 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
126 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
127 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
128 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
129 #define FLEXCAN_ESR_BOFF_INT BIT(2)
130 #define FLEXCAN_ESR_ERR_INT BIT(1)
131 #define FLEXCAN_ESR_WAK_INT BIT(0)
132 #define FLEXCAN_ESR_ERR_BUS \
133 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
134 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
135 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
136 #define FLEXCAN_ESR_ERR_STATE \
137 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
138 #define FLEXCAN_ESR_ERR_ALL \
139 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
140 #define FLEXCAN_ESR_ALL_INT \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
142 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
144 /* FLEXCAN interrupt flag register (IFLAG) bits */
145 /* Errata ERR005829 step7: Reserve first valid MB */
146 #define FLEXCAN_TX_BUF_RESERVED 8
147 #define FLEXCAN_TX_BUF_ID 9
148 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
149 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
150 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
151 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
152 #define FLEXCAN_IFLAG_DEFAULT \
153 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
154 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
156 /* FLEXCAN message buffers */
157 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
158 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
159 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
160 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
161 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
163 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
164 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
165 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
166 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
168 #define FLEXCAN_MB_CNT_SRR BIT(22)
169 #define FLEXCAN_MB_CNT_IDE BIT(21)
170 #define FLEXCAN_MB_CNT_RTR BIT(20)
171 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
172 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
174 #define FLEXCAN_TIMEOUT_US (250)
176 /* FLEXCAN hardware feature flags
178 * Below is some version info we got:
179 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
180 * Filter? connected? detection ception in MB
181 * MX25 FlexCAN2 03.00.00.00 no no no no
182 * MX28 FlexCAN2 03.00.04.00 yes yes no no
183 * MX35 FlexCAN2 03.00.00.00 no no no no
184 * MX53 FlexCAN2 03.00.00.00 yes no no no
185 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
186 * VF610 FlexCAN3 ? no yes yes yes?
188 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
190 #define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
191 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
192 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
194 /* Structure of the message buffer */
201 /* Structure of the hardware registers */
202 struct flexcan_regs {
205 u32 timer; /* 0x08 */
206 u32 _reserved1; /* 0x0c */
207 u32 rxgmask; /* 0x10 */
208 u32 rx14mask; /* 0x14 */
209 u32 rx15mask; /* 0x18 */
212 u32 imask2; /* 0x24 */
213 u32 imask1; /* 0x28 */
214 u32 iflag2; /* 0x2c */
215 u32 iflag1; /* 0x30 */
216 u32 ctrl2; /* 0x34 */
218 u32 imeur; /* 0x3c */
221 u32 rxfgmask; /* 0x48 */
222 u32 rxfir; /* 0x4c */
223 u32 _reserved3[12]; /* 0x50 */
224 struct flexcan_mb mb[64]; /* 0x80 */
227 * 0x080...0x08f 0 RX message buffer
228 * 0x090...0x0df 1-5 reserverd
229 * 0x0e0...0x0ff 6-7 8 entry ID table
230 * (mx25, mx28, mx35, mx53)
231 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
232 * size conf'ed via ctrl2::RFFN
236 u32 mecr; /* 0xae0 */
237 u32 erriar; /* 0xae4 */
238 u32 erridpr; /* 0xae8 */
239 u32 errippr; /* 0xaec */
240 u32 rerrar; /* 0xaf0 */
241 u32 rerrdr; /* 0xaf4 */
242 u32 rerrsynr; /* 0xaf8 */
243 u32 errsr; /* 0xafc */
246 struct flexcan_devtype_data {
247 u32 quirks; /* quirks needed for different IP cores */
250 struct flexcan_priv {
252 struct napi_struct napi;
254 struct flexcan_regs __iomem *regs;
256 u32 reg_ctrl_default;
260 struct flexcan_platform_data *pdata;
261 const struct flexcan_devtype_data *devtype_data;
262 struct regulator *reg_xceiver;
265 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
266 .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
269 static struct flexcan_devtype_data fsl_imx28_devtype_data;
271 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
272 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
275 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
276 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
279 static const struct can_bittiming_const flexcan_bittiming_const = {
291 /* Abstract off the read/write for arm versus ppc. This
292 * assumes that PPC uses big-endian registers and everything
293 * else uses little-endian registers, independent of CPU
296 #if defined(CONFIG_PPC)
297 static inline u32 flexcan_read(void __iomem *addr)
299 return in_be32(addr);
302 static inline void flexcan_write(u32 val, void __iomem *addr)
307 static inline u32 flexcan_read(void __iomem *addr)
312 static inline void flexcan_write(u32 val, void __iomem *addr)
318 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
320 if (!priv->reg_xceiver)
323 return regulator_enable(priv->reg_xceiver);
326 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
328 if (!priv->reg_xceiver)
331 return regulator_disable(priv->reg_xceiver);
334 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
337 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
338 (reg_esr & FLEXCAN_ESR_ERR_BUS);
341 static int flexcan_chip_enable(struct flexcan_priv *priv)
343 struct flexcan_regs __iomem *regs = priv->regs;
344 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
347 reg = flexcan_read(®s->mcr);
348 reg &= ~FLEXCAN_MCR_MDIS;
349 flexcan_write(reg, ®s->mcr);
351 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
354 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
360 static int flexcan_chip_disable(struct flexcan_priv *priv)
362 struct flexcan_regs __iomem *regs = priv->regs;
363 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
366 reg = flexcan_read(®s->mcr);
367 reg |= FLEXCAN_MCR_MDIS;
368 flexcan_write(reg, ®s->mcr);
370 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
373 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
379 static int flexcan_chip_freeze(struct flexcan_priv *priv)
381 struct flexcan_regs __iomem *regs = priv->regs;
382 unsigned int timeout;
383 u32 bitrate = priv->can.bittiming.bitrate;
387 timeout = 1000 * 1000 * 10 / bitrate;
389 timeout = FLEXCAN_TIMEOUT_US / 10;
391 reg = flexcan_read(®s->mcr);
392 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
393 flexcan_write(reg, ®s->mcr);
395 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
398 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
404 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
406 struct flexcan_regs __iomem *regs = priv->regs;
407 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
410 reg = flexcan_read(®s->mcr);
411 reg &= ~FLEXCAN_MCR_HALT;
412 flexcan_write(reg, ®s->mcr);
414 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
417 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
423 static int flexcan_chip_softreset(struct flexcan_priv *priv)
425 struct flexcan_regs __iomem *regs = priv->regs;
426 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
428 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
429 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
432 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
438 static int __flexcan_get_berr_counter(const struct net_device *dev,
439 struct can_berr_counter *bec)
441 const struct flexcan_priv *priv = netdev_priv(dev);
442 struct flexcan_regs __iomem *regs = priv->regs;
443 u32 reg = flexcan_read(®s->ecr);
445 bec->txerr = (reg >> 0) & 0xff;
446 bec->rxerr = (reg >> 8) & 0xff;
451 static int flexcan_get_berr_counter(const struct net_device *dev,
452 struct can_berr_counter *bec)
454 const struct flexcan_priv *priv = netdev_priv(dev);
457 err = clk_prepare_enable(priv->clk_ipg);
461 err = clk_prepare_enable(priv->clk_per);
463 goto out_disable_ipg;
465 err = __flexcan_get_berr_counter(dev, bec);
467 clk_disable_unprepare(priv->clk_per);
469 clk_disable_unprepare(priv->clk_ipg);
474 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
476 const struct flexcan_priv *priv = netdev_priv(dev);
477 struct flexcan_regs __iomem *regs = priv->regs;
478 struct can_frame *cf = (struct can_frame *)skb->data;
481 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
483 if (can_dropped_invalid_skb(dev, skb))
486 netif_stop_queue(dev);
488 if (cf->can_id & CAN_EFF_FLAG) {
489 can_id = cf->can_id & CAN_EFF_MASK;
490 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
492 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
495 if (cf->can_id & CAN_RTR_FLAG)
496 ctrl |= FLEXCAN_MB_CNT_RTR;
498 if (cf->can_dlc > 0) {
499 data = be32_to_cpup((__be32 *)&cf->data[0]);
500 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[0]);
502 if (cf->can_dlc > 4) {
503 data = be32_to_cpup((__be32 *)&cf->data[4]);
504 flexcan_write(data, ®s->mb[FLEXCAN_TX_BUF_ID].data[1]);
507 can_put_echo_skb(skb, dev, 0);
509 flexcan_write(can_id, ®s->mb[FLEXCAN_TX_BUF_ID].can_id);
510 flexcan_write(ctrl, ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
512 /* Errata ERR005829 step8:
513 * Write twice INACTIVE(0x8) code to first MB.
515 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
516 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
517 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
518 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
523 static void do_bus_err(struct net_device *dev,
524 struct can_frame *cf, u32 reg_esr)
526 struct flexcan_priv *priv = netdev_priv(dev);
527 int rx_errors = 0, tx_errors = 0;
529 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
531 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
532 netdev_dbg(dev, "BIT1_ERR irq\n");
533 cf->data[2] |= CAN_ERR_PROT_BIT1;
536 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
537 netdev_dbg(dev, "BIT0_ERR irq\n");
538 cf->data[2] |= CAN_ERR_PROT_BIT0;
541 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
542 netdev_dbg(dev, "ACK_ERR irq\n");
543 cf->can_id |= CAN_ERR_ACK;
544 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
547 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
548 netdev_dbg(dev, "CRC_ERR irq\n");
549 cf->data[2] |= CAN_ERR_PROT_BIT;
550 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
553 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
554 netdev_dbg(dev, "FRM_ERR irq\n");
555 cf->data[2] |= CAN_ERR_PROT_FORM;
558 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
559 netdev_dbg(dev, "STF_ERR irq\n");
560 cf->data[2] |= CAN_ERR_PROT_STUFF;
564 priv->can.can_stats.bus_error++;
566 dev->stats.rx_errors++;
568 dev->stats.tx_errors++;
571 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
574 struct can_frame *cf;
576 skb = alloc_can_err_skb(dev, &cf);
580 do_bus_err(dev, cf, reg_esr);
582 dev->stats.rx_packets++;
583 dev->stats.rx_bytes += cf->can_dlc;
584 netif_receive_skb(skb);
589 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
591 struct flexcan_priv *priv = netdev_priv(dev);
593 struct can_frame *cf;
594 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
596 struct can_berr_counter bec;
598 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
599 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
600 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
601 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
602 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
603 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
604 new_state = max(tx_state, rx_state);
606 __flexcan_get_berr_counter(dev, &bec);
607 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
608 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
609 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
610 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
613 /* state hasn't changed */
614 if (likely(new_state == priv->can.state))
617 skb = alloc_can_err_skb(dev, &cf);
621 can_change_state(dev, cf, tx_state, rx_state);
623 if (unlikely(new_state == CAN_STATE_BUS_OFF))
626 dev->stats.rx_packets++;
627 dev->stats.rx_bytes += cf->can_dlc;
628 netif_receive_skb(skb);
633 static void flexcan_read_fifo(const struct net_device *dev,
634 struct can_frame *cf)
636 const struct flexcan_priv *priv = netdev_priv(dev);
637 struct flexcan_regs __iomem *regs = priv->regs;
638 struct flexcan_mb __iomem *mb = ®s->mb[0];
639 u32 reg_ctrl, reg_id;
641 reg_ctrl = flexcan_read(&mb->can_ctrl);
642 reg_id = flexcan_read(&mb->can_id);
643 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
644 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
646 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
648 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
649 cf->can_id |= CAN_RTR_FLAG;
650 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
652 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
653 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
656 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
657 flexcan_read(®s->timer);
660 static int flexcan_read_frame(struct net_device *dev)
662 struct net_device_stats *stats = &dev->stats;
663 struct can_frame *cf;
666 skb = alloc_can_skb(dev, &cf);
667 if (unlikely(!skb)) {
672 flexcan_read_fifo(dev, cf);
675 stats->rx_bytes += cf->can_dlc;
676 netif_receive_skb(skb);
678 can_led_event(dev, CAN_LED_EVENT_RX);
683 static int flexcan_poll(struct napi_struct *napi, int quota)
685 struct net_device *dev = napi->dev;
686 const struct flexcan_priv *priv = netdev_priv(dev);
687 struct flexcan_regs __iomem *regs = priv->regs;
688 u32 reg_iflag1, reg_esr;
691 /* The error bits are cleared on read,
692 * use saved value from irq handler.
694 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
696 /* handle state changes */
697 work_done += flexcan_poll_state(dev, reg_esr);
700 reg_iflag1 = flexcan_read(®s->iflag1);
701 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
703 work_done += flexcan_read_frame(dev);
704 reg_iflag1 = flexcan_read(®s->iflag1);
707 /* report bus errors */
708 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
709 work_done += flexcan_poll_bus_err(dev, reg_esr);
711 if (work_done < quota) {
714 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
715 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
721 static irqreturn_t flexcan_irq(int irq, void *dev_id)
723 struct net_device *dev = dev_id;
724 struct net_device_stats *stats = &dev->stats;
725 struct flexcan_priv *priv = netdev_priv(dev);
726 struct flexcan_regs __iomem *regs = priv->regs;
727 u32 reg_iflag1, reg_esr;
729 reg_iflag1 = flexcan_read(®s->iflag1);
730 reg_esr = flexcan_read(®s->esr);
732 /* ACK all bus error and state change IRQ sources */
733 if (reg_esr & FLEXCAN_ESR_ALL_INT)
734 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
736 /* schedule NAPI in case of:
739 * - bus error IRQ and bus error reporting is activated
741 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
742 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
743 flexcan_has_and_handle_berr(priv, reg_esr)) {
744 /* The error bits are cleared on read,
745 * save them for later use.
747 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
748 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
749 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
750 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
752 napi_schedule(&priv->napi);
756 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
757 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
758 dev->stats.rx_over_errors++;
759 dev->stats.rx_errors++;
762 /* transmission complete interrupt */
763 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
764 stats->tx_bytes += can_get_echo_skb(dev, 0);
766 can_led_event(dev, CAN_LED_EVENT_TX);
768 /* after sending a RTR frame MB is in RX mode */
769 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
770 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
771 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
772 netif_wake_queue(dev);
778 static void flexcan_set_bittiming(struct net_device *dev)
780 const struct flexcan_priv *priv = netdev_priv(dev);
781 const struct can_bittiming *bt = &priv->can.bittiming;
782 struct flexcan_regs __iomem *regs = priv->regs;
785 reg = flexcan_read(®s->ctrl);
786 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
787 FLEXCAN_CTRL_RJW(0x3) |
788 FLEXCAN_CTRL_PSEG1(0x7) |
789 FLEXCAN_CTRL_PSEG2(0x7) |
790 FLEXCAN_CTRL_PROPSEG(0x7) |
795 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
796 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
797 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
798 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
799 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
801 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
802 reg |= FLEXCAN_CTRL_LPB;
803 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
804 reg |= FLEXCAN_CTRL_LOM;
805 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
806 reg |= FLEXCAN_CTRL_SMP;
808 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
809 flexcan_write(reg, ®s->ctrl);
811 /* print chip status */
812 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
813 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
816 /* flexcan_chip_start
818 * this functions is entered with clocks enabled
821 static int flexcan_chip_start(struct net_device *dev)
823 struct flexcan_priv *priv = netdev_priv(dev);
824 struct flexcan_regs __iomem *regs = priv->regs;
825 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
829 err = flexcan_chip_enable(priv);
834 err = flexcan_chip_softreset(priv);
836 goto out_chip_disable;
838 flexcan_set_bittiming(dev);
845 * only supervisor access
849 * set max mailbox number
851 reg_mcr = flexcan_read(®s->mcr);
852 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
853 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
854 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
855 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
856 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
857 flexcan_write(reg_mcr, ®s->mcr);
861 * disable timer sync feature
863 * disable auto busoff recovery
864 * transmit lowest buffer first
866 * enable tx and rx warning interrupt
867 * enable bus off interrupt
868 * (== FLEXCAN_CTRL_ERR_STATE)
870 reg_ctrl = flexcan_read(®s->ctrl);
871 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
872 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
873 FLEXCAN_CTRL_ERR_STATE;
875 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
876 * on most Flexcan cores, too. Otherwise we don't get
877 * any error warning or passive interrupts.
879 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
880 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
881 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
883 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
885 /* save for later use */
886 priv->reg_ctrl_default = reg_ctrl;
887 /* leave interrupts disabled for now */
888 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
889 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
890 flexcan_write(reg_ctrl, ®s->ctrl);
892 /* clear and invalidate all mailboxes first */
893 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
894 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
895 ®s->mb[i].can_ctrl);
898 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
899 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
900 ®s->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
902 /* mark TX mailbox as INACTIVE */
903 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
904 ®s->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
906 /* acceptance mask/acceptance code (accept everything) */
907 flexcan_write(0x0, ®s->rxgmask);
908 flexcan_write(0x0, ®s->rx14mask);
909 flexcan_write(0x0, ®s->rx15mask);
911 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
912 flexcan_write(0x0, ®s->rxfgmask);
914 /* On Vybrid, disable memory error detection interrupts
916 * This also works around errata e5295 which generates
917 * false positive memory errors and put the device in
920 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
921 /* Follow the protocol as described in "Detection
922 * and Correction of Memory Errors" to write to
925 reg_ctrl2 = flexcan_read(®s->ctrl2);
926 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
927 flexcan_write(reg_ctrl2, ®s->ctrl2);
929 reg_mecr = flexcan_read(®s->mecr);
930 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
931 flexcan_write(reg_mecr, ®s->mecr);
932 reg_mecr |= FLEXCAN_MECR_ECCDIS;
933 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
934 FLEXCAN_MECR_FANCEI_MSK);
935 flexcan_write(reg_mecr, ®s->mecr);
938 err = flexcan_transceiver_enable(priv);
940 goto out_chip_disable;
942 /* synchronize with the can bus */
943 err = flexcan_chip_unfreeze(priv);
945 goto out_transceiver_disable;
947 priv->can.state = CAN_STATE_ERROR_ACTIVE;
949 /* enable interrupts atomically */
950 disable_irq(dev->irq);
951 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
952 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
953 enable_irq(dev->irq);
955 /* print chip status */
956 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
957 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
961 out_transceiver_disable:
962 flexcan_transceiver_disable(priv);
964 flexcan_chip_disable(priv);
970 * this functions is entered with clocks enabled
972 static void flexcan_chip_stop(struct net_device *dev)
974 struct flexcan_priv *priv = netdev_priv(dev);
975 struct flexcan_regs __iomem *regs = priv->regs;
977 /* freeze + disable module */
978 flexcan_chip_freeze(priv);
979 flexcan_chip_disable(priv);
981 /* Disable all interrupts */
982 flexcan_write(0, ®s->imask1);
983 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
986 flexcan_transceiver_disable(priv);
987 priv->can.state = CAN_STATE_STOPPED;
990 static int flexcan_open(struct net_device *dev)
992 struct flexcan_priv *priv = netdev_priv(dev);
995 err = clk_prepare_enable(priv->clk_ipg);
999 err = clk_prepare_enable(priv->clk_per);
1001 goto out_disable_ipg;
1003 err = open_candev(dev);
1005 goto out_disable_per;
1007 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1011 /* start chip and queuing */
1012 err = flexcan_chip_start(dev);
1016 can_led_event(dev, CAN_LED_EVENT_OPEN);
1018 napi_enable(&priv->napi);
1019 netif_start_queue(dev);
1024 free_irq(dev->irq, dev);
1028 clk_disable_unprepare(priv->clk_per);
1030 clk_disable_unprepare(priv->clk_ipg);
1035 static int flexcan_close(struct net_device *dev)
1037 struct flexcan_priv *priv = netdev_priv(dev);
1039 netif_stop_queue(dev);
1040 napi_disable(&priv->napi);
1041 flexcan_chip_stop(dev);
1043 free_irq(dev->irq, dev);
1044 clk_disable_unprepare(priv->clk_per);
1045 clk_disable_unprepare(priv->clk_ipg);
1049 can_led_event(dev, CAN_LED_EVENT_STOP);
1054 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1059 case CAN_MODE_START:
1060 err = flexcan_chip_start(dev);
1064 netif_wake_queue(dev);
1074 static const struct net_device_ops flexcan_netdev_ops = {
1075 .ndo_open = flexcan_open,
1076 .ndo_stop = flexcan_close,
1077 .ndo_start_xmit = flexcan_start_xmit,
1078 .ndo_change_mtu = can_change_mtu,
1081 static int register_flexcandev(struct net_device *dev)
1083 struct flexcan_priv *priv = netdev_priv(dev);
1084 struct flexcan_regs __iomem *regs = priv->regs;
1087 err = clk_prepare_enable(priv->clk_ipg);
1091 err = clk_prepare_enable(priv->clk_per);
1093 goto out_disable_ipg;
1095 /* select "bus clock", chip must be disabled */
1096 err = flexcan_chip_disable(priv);
1098 goto out_disable_per;
1099 reg = flexcan_read(®s->ctrl);
1100 reg |= FLEXCAN_CTRL_CLK_SRC;
1101 flexcan_write(reg, ®s->ctrl);
1103 err = flexcan_chip_enable(priv);
1105 goto out_chip_disable;
1107 /* set freeze, halt */
1108 err = flexcan_chip_freeze(priv);
1110 goto out_chip_disable;
1112 /* activate FIFO, restrict register access */
1113 reg = flexcan_read(®s->mcr);
1114 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1115 flexcan_write(reg, ®s->mcr);
1117 /* Currently we only support newer versions of this core
1118 * featuring a RX FIFO. Older cores found on some Coldfire
1119 * derivates are not yet supported.
1121 reg = flexcan_read(®s->mcr);
1122 if (!(reg & FLEXCAN_MCR_FEN)) {
1123 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1125 goto out_chip_disable;
1128 err = register_candev(dev);
1130 /* disable core and turn off clocks */
1132 flexcan_chip_disable(priv);
1134 clk_disable_unprepare(priv->clk_per);
1136 clk_disable_unprepare(priv->clk_ipg);
1141 static void unregister_flexcandev(struct net_device *dev)
1143 unregister_candev(dev);
1146 static const struct of_device_id flexcan_of_match[] = {
1147 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1148 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1149 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1150 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1153 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1155 static const struct platform_device_id flexcan_id_table[] = {
1156 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1159 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1161 static int flexcan_probe(struct platform_device *pdev)
1163 const struct of_device_id *of_id;
1164 const struct flexcan_devtype_data *devtype_data;
1165 struct net_device *dev;
1166 struct flexcan_priv *priv;
1167 struct regulator *reg_xceiver;
1168 struct resource *mem;
1169 struct clk *clk_ipg = NULL, *clk_per = NULL;
1170 struct flexcan_regs __iomem *regs;
1174 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1175 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1176 return -EPROBE_DEFER;
1177 else if (IS_ERR(reg_xceiver))
1180 if (pdev->dev.of_node)
1181 of_property_read_u32(pdev->dev.of_node,
1182 "clock-frequency", &clock_freq);
1185 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1186 if (IS_ERR(clk_ipg)) {
1187 dev_err(&pdev->dev, "no ipg clock defined\n");
1188 return PTR_ERR(clk_ipg);
1191 clk_per = devm_clk_get(&pdev->dev, "per");
1192 if (IS_ERR(clk_per)) {
1193 dev_err(&pdev->dev, "no per clock defined\n");
1194 return PTR_ERR(clk_per);
1196 clock_freq = clk_get_rate(clk_per);
1199 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200 irq = platform_get_irq(pdev, 0);
1204 regs = devm_ioremap_resource(&pdev->dev, mem);
1206 return PTR_ERR(regs);
1208 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1210 devtype_data = of_id->data;
1211 } else if (platform_get_device_id(pdev)->driver_data) {
1212 devtype_data = (struct flexcan_devtype_data *)
1213 platform_get_device_id(pdev)->driver_data;
1218 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1222 dev->netdev_ops = &flexcan_netdev_ops;
1224 dev->flags |= IFF_ECHO;
1226 priv = netdev_priv(dev);
1227 priv->can.clock.freq = clock_freq;
1228 priv->can.bittiming_const = &flexcan_bittiming_const;
1229 priv->can.do_set_mode = flexcan_set_mode;
1230 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1231 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1232 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1233 CAN_CTRLMODE_BERR_REPORTING;
1235 priv->clk_ipg = clk_ipg;
1236 priv->clk_per = clk_per;
1237 priv->pdata = dev_get_platdata(&pdev->dev);
1238 priv->devtype_data = devtype_data;
1239 priv->reg_xceiver = reg_xceiver;
1241 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1243 platform_set_drvdata(pdev, dev);
1244 SET_NETDEV_DEV(dev, &pdev->dev);
1246 err = register_flexcandev(dev);
1248 dev_err(&pdev->dev, "registering netdev failed\n");
1249 goto failed_register;
1252 devm_can_led_init(dev);
1254 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1255 priv->regs, dev->irq);
1264 static int flexcan_remove(struct platform_device *pdev)
1266 struct net_device *dev = platform_get_drvdata(pdev);
1267 struct flexcan_priv *priv = netdev_priv(dev);
1269 unregister_flexcandev(dev);
1270 netif_napi_del(&priv->napi);
1276 static int __maybe_unused flexcan_suspend(struct device *device)
1278 struct net_device *dev = dev_get_drvdata(device);
1279 struct flexcan_priv *priv = netdev_priv(dev);
1282 if (netif_running(dev)) {
1283 err = flexcan_chip_disable(priv);
1286 netif_stop_queue(dev);
1287 netif_device_detach(dev);
1289 priv->can.state = CAN_STATE_SLEEPING;
1294 static int __maybe_unused flexcan_resume(struct device *device)
1296 struct net_device *dev = dev_get_drvdata(device);
1297 struct flexcan_priv *priv = netdev_priv(dev);
1300 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1301 if (netif_running(dev)) {
1302 netif_device_attach(dev);
1303 netif_start_queue(dev);
1304 err = flexcan_chip_enable(priv);
1311 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1313 static struct platform_driver flexcan_driver = {
1316 .pm = &flexcan_pm_ops,
1317 .of_match_table = flexcan_of_match,
1319 .probe = flexcan_probe,
1320 .remove = flexcan_remove,
1321 .id_table = flexcan_id_table,
1324 module_platform_driver(flexcan_driver);
1326 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1327 "Marc Kleine-Budde <kernel@pengutronix.de>");
1328 MODULE_LICENSE("GPL v2");
1329 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");