drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/can.h>
  14 #include <linux/can/dev.h>
  15 #include <linux/can/error.h>
  16 #include <linux/can/led.h>
  17 #include <linux/can/rx-offload.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regulator/consumer.h>
  27
  28 #define DRV_NAME                        "flexcan"
  29
  30 /* 8 for RX fifo and 2 error handling */
  31 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  32
  33 /* FLEXCAN module configuration register (CANMCR) bits */
  34 #define FLEXCAN_MCR_MDIS                BIT(31)
  35 #define FLEXCAN_MCR_FRZ                 BIT(30)
  36 #define FLEXCAN_MCR_FEN                 BIT(29)
  37 #define FLEXCAN_MCR_HALT                BIT(28)
  38 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  39 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  40 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  41 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  42 #define FLEXCAN_MCR_SUPV                BIT(23)
  43 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  44 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  45 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  46 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  47 #define FLEXCAN_MCR_DOZE                BIT(18)
  48 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  49 #define FLEXCAN_MCR_IRMQ                BIT(16)
  50 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  51 #define FLEXCAN_MCR_AEN                 BIT(12)
  52 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  53 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  54 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  55 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  56 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  57 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  58
  59 /* FLEXCAN control register (CANCTRL) bits */
  60 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  61 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  62 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  63 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  64 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  65 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  66 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  67 #define FLEXCAN_CTRL_LPB                BIT(12)
  68 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  69 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  70 #define FLEXCAN_CTRL_SMP                BIT(7)
  71 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  72 #define FLEXCAN_CTRL_TSYN               BIT(5)
  73 #define FLEXCAN_CTRL_LBUF               BIT(4)
  74 #define FLEXCAN_CTRL_LOM                BIT(3)
  75 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  76 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  77 #define FLEXCAN_CTRL_ERR_STATE \
  78         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  79          FLEXCAN_CTRL_BOFF_MSK)
  80 #define FLEXCAN_CTRL_ERR_ALL \
  81         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  82
  83 /* FLEXCAN control register 2 (CTRL2) bits */
  84 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  85 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  86 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  87 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  88 #define FLEXCAN_CTRL2_MRP               BIT(18)
  89 #define FLEXCAN_CTRL2_RRS               BIT(17)
  90 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  91
  92 /* FLEXCAN memory error control register (MECR) bits */
  93 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  94 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  95 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  96 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
  97 #define FLEXCAN_MECR_HAERRIE            BIT(15)
  98 #define FLEXCAN_MECR_FAERRIE            BIT(14)
  99 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 100 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 101 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 102 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 103
 104 /* FLEXCAN error and status register (ESR) bits */
 105 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 106 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 107 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 108 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 109 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 110 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 111 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 112 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 113 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 114 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 115 #define FLEXCAN_ESR_IDLE                BIT(7)
 116 #define FLEXCAN_ESR_TXRX                BIT(6)
 117 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 118 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 119 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 120 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 121 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 122 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 123 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 124 #define FLEXCAN_ESR_ERR_BUS \
 125         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 126          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 127          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 128 #define FLEXCAN_ESR_ERR_STATE \
 129         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 130 #define FLEXCAN_ESR_ERR_ALL \
 131         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 132 #define FLEXCAN_ESR_ALL_INT \
 133         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 134          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 135
 136 /* FLEXCAN interrupt flag register (IFLAG) bits */
 137 /* Errata ERR005829 step7: Reserve first valid MB */
 138 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 139 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 140 #define FLEXCAN_TX_MB                           63
 141 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 142 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST        (FLEXCAN_TX_MB - 1)
 143 #define FLEXCAN_IFLAG_MB(x)             BIT((x) & 0x1f)
 144 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 145 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 146 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 147
 148 /* FLEXCAN message buffers */
 149 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 150 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 151 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 152 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 153 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 154 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 155 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 156
 157 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 158 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 159 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 160 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 161
 162 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 163 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 164 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 165 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 166 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 167
 168 #define FLEXCAN_TIMEOUT_US              (250)
 169
 170 /* FLEXCAN hardware feature flags
 171  *
 172  * Below is some version info we got:
 173  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 174  *                                Filter? connected?  Passive detection  ception in MB
 175  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 176  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 177  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 178  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 179  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 180  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 181  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 182  *
 183  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 184  */
 185 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 186 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 187 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 188 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 189 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 190 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 191 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 192
 193 /* Structure of the message buffer */
 194 struct flexcan_mb {
 195         u32 can_ctrl;
 196         u32 can_id;
 197         u32 data[2];
 198 };
 199
 200 /* Structure of the hardware registers */
 201 struct flexcan_regs {
 202         u32 mcr;                /* 0x00 */
 203         u32 ctrl;               /* 0x04 */
 204         u32 timer;              /* 0x08 */
 205         u32 _reserved1;         /* 0x0c */
 206         u32 rxgmask;            /* 0x10 */
 207         u32 rx14mask;           /* 0x14 */
 208         u32 rx15mask;           /* 0x18 */
 209         u32 ecr;                /* 0x1c */
 210         u32 esr;                /* 0x20 */
 211         u32 imask2;             /* 0x24 */
 212         u32 imask1;             /* 0x28 */
 213         u32 iflag2;             /* 0x2c */
 214         u32 iflag1;             /* 0x30 */
 215         union {                 /* 0x34 */
 216                 u32 gfwr_mx28;  /* MX28, MX53 */
 217                 u32 ctrl2;      /* MX6, VF610 */
 218         };
 219         u32 esr2;               /* 0x38 */
 220         u32 imeur;              /* 0x3c */
 221         u32 lrfr;               /* 0x40 */
 222         u32 crcr;               /* 0x44 */
 223         u32 rxfgmask;           /* 0x48 */
 224         u32 rxfir;              /* 0x4c */
 225         u32 _reserved3[12];     /* 0x50 */
 226         struct flexcan_mb mb[64];       /* 0x80 */
 227         /* FIFO-mode:
 228          *                      MB
 229          * 0x080...0x08f        0       RX message buffer
 230          * 0x090...0x0df        1-5     reserverd
 231          * 0x0e0...0x0ff        6-7     8 entry ID table
 232          *                              (mx25, mx28, mx35, mx53)
 233          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 234          *                              size conf'ed via ctrl2::RFFN
 235          *                              (mx6, vf610)
 236          */
 237         u32 _reserved4[256];    /* 0x480 */
 238         u32 rximr[64];          /* 0x880 */
 239         u32 _reserved5[24];     /* 0x980 */
 240         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 241         u32 _reserved6[63];     /* 0x9e4 */
 242         u32 mecr;               /* 0xae0 */
 243         u32 erriar;             /* 0xae4 */
 244         u32 erridpr;            /* 0xae8 */
 245         u32 errippr;            /* 0xaec */
 246         u32 rerrar;             /* 0xaf0 */
 247         u32 rerrdr;             /* 0xaf4 */
 248         u32 rerrsynr;           /* 0xaf8 */
 249         u32 errsr;              /* 0xafc */
 250 };
 251
 252 struct flexcan_devtype_data {
 253         u32 quirks;             /* quirks needed for different IP cores */
 254 };
 255
 256 struct flexcan_priv {
 257         struct can_priv can;
 258         struct can_rx_offload offload;
 259
 260         struct flexcan_regs __iomem *regs;
 261         struct flexcan_mb __iomem *tx_mb_reserved;
 262         u32 reg_ctrl_default;
 263         u32 reg_imask1_default;
 264         u32 reg_imask2_default;
 265
 266         struct clk *clk_ipg;
 267         struct clk *clk_per;
 268         const struct flexcan_devtype_data *devtype_data;
 269         struct regulator *reg_xceiver;
 270
 271         /* Read and Write APIs */
 272         u32 (*read)(void __iomem *addr);
 273         void (*write)(u32 val, void __iomem *addr);
 274 };
 275
 276 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 277         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 278                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 279                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 280 };
 281
 282 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 283         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 284                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 285 };
 286
 287 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 288         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 289 };
 290
 291 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 292         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 293                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 294 };
 295
 296 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 297         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 298                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 299                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 300 };
 301
 302 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 303         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 304                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 305 };
 306
 307 static const struct can_bittiming_const flexcan_bittiming_const = {
 308         .name = DRV_NAME,
 309         .tseg1_min = 4,
 310         .tseg1_max = 16,
 311         .tseg2_min = 2,
 312         .tseg2_max = 8,
 313         .sjw_max = 4,
 314         .brp_min = 1,
 315         .brp_max = 256,
 316         .brp_inc = 1,
 317 };
 318
 319 /* FlexCAN module is essentially modelled as a little-endian IP in most
 320  * SoCs, i.e the registers as well as the message buffer areas are
 321  * implemented in a little-endian fashion.
 322  *
 323  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 324  * module in a big-endian fashion (i.e the registers as well as the
 325  * message buffer areas are implemented in a big-endian way).
 326  *
 327  * In addition, the FlexCAN module can be found on SoCs having ARM or
 328  * PPC cores. So, we need to abstract off the register read/write
 329  * functions, ensuring that these cater to all the combinations of module
 330  * endianness and underlying CPU endianness.
 331  */
 332 static inline u32 flexcan_read_be(void __iomem *addr)
 333 {
 334         return ioread32be(addr);
 335 }
 336
 337 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 338 {
 339         iowrite32be(val, addr);
 340 }
 341
 342 static inline u32 flexcan_read_le(void __iomem *addr)
 343 {
 344         return ioread32(addr);
 345 }
 346
 347 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 348 {
 349         iowrite32(val, addr);
 350 }
 351
 352 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 353 {
 354         struct flexcan_regs __iomem *regs = priv->regs;
 355         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 356
 357         priv->write(reg_ctrl, &regs->ctrl);
 358 }
 359
 360 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 361 {
 362         struct flexcan_regs __iomem *regs = priv->regs;
 363         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 364
 365         priv->write(reg_ctrl, &regs->ctrl);
 366 }
 367
 368 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 369 {
 370         if (!priv->reg_xceiver)
 371                 return 0;
 372
 373         return regulator_enable(priv->reg_xceiver);
 374 }
 375
 376 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 377 {
 378         if (!priv->reg_xceiver)
 379                 return 0;
 380
 381         return regulator_disable(priv->reg_xceiver);
 382 }
 383
 384 static int flexcan_chip_enable(struct flexcan_priv *priv)
 385 {
 386         struct flexcan_regs __iomem *regs = priv->regs;
 387         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 388         u32 reg;
 389
 390         reg = priv->read(&regs->mcr);
 391         reg &= ~FLEXCAN_MCR_MDIS;
 392         priv->write(reg, &regs->mcr);
 393
 394         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 395                 udelay(10);
 396
 397         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 398                 return -ETIMEDOUT;
 399
 400         return 0;
 401 }
 402
 403 static int flexcan_chip_disable(struct flexcan_priv *priv)
 404 {
 405         struct flexcan_regs __iomem *regs = priv->regs;
 406         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 407         u32 reg;
 408
 409         reg = priv->read(&regs->mcr);
 410         reg |= FLEXCAN_MCR_MDIS;
 411         priv->write(reg, &regs->mcr);
 412
 413         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 414                 udelay(10);
 415
 416         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 417                 return -ETIMEDOUT;
 418
 419         return 0;
 420 }
 421
 422 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 423 {
 424         struct flexcan_regs __iomem *regs = priv->regs;
 425         unsigned int timeout;
 426         u32 bitrate = priv->can.bittiming.bitrate;
 427         u32 reg;
 428
 429         if (bitrate)
 430                 timeout = 1000 * 1000 * 10 / bitrate;
 431         else
 432                 timeout = FLEXCAN_TIMEOUT_US / 10;
 433
 434         reg = priv->read(&regs->mcr);
 435         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
 436         priv->write(reg, &regs->mcr);
 437
 438         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 439                 udelay(100);
 440
 441         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 442                 return -ETIMEDOUT;
 443
 444         return 0;
 445 }
 446
 447 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 448 {
 449         struct flexcan_regs __iomem *regs = priv->regs;
 450         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 451         u32 reg;
 452
 453         reg = priv->read(&regs->mcr);
 454         reg &= ~FLEXCAN_MCR_HALT;
 455         priv->write(reg, &regs->mcr);
 456
 457         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 458                 udelay(10);
 459
 460         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 461                 return -ETIMEDOUT;
 462
 463         return 0;
 464 }
 465
 466 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 467 {
 468         struct flexcan_regs __iomem *regs = priv->regs;
 469         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 470
 471         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 472         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 473                 udelay(10);
 474
 475         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 476                 return -ETIMEDOUT;
 477
 478         return 0;
 479 }
 480
 481 static int __flexcan_get_berr_counter(const struct net_device *dev,
 482                                       struct can_berr_counter *bec)
 483 {
 484         const struct flexcan_priv *priv = netdev_priv(dev);
 485         struct flexcan_regs __iomem *regs = priv->regs;
 486         u32 reg = priv->read(&regs->ecr);
 487
 488         bec->txerr = (reg >> 0) & 0xff;
 489         bec->rxerr = (reg >> 8) & 0xff;
 490
 491         return 0;
 492 }
 493
 494 static int flexcan_get_berr_counter(const struct net_device *dev,
 495                                     struct can_berr_counter *bec)
 496 {
 497         const struct flexcan_priv *priv = netdev_priv(dev);
 498         int err;
 499
 500         err = clk_prepare_enable(priv->clk_ipg);
 501         if (err)
 502                 return err;
 503
 504         err = clk_prepare_enable(priv->clk_per);
 505         if (err)
 506                 goto out_disable_ipg;
 507
 508         err = __flexcan_get_berr_counter(dev, bec);
 509
 510         clk_disable_unprepare(priv->clk_per);
 511  out_disable_ipg:
 512         clk_disable_unprepare(priv->clk_ipg);
 513
 514         return err;
 515 }
 516
 517 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 518 {
 519         const struct flexcan_priv *priv = netdev_priv(dev);
 520         struct flexcan_regs __iomem *regs = priv->regs;
 521         struct can_frame *cf = (struct can_frame *)skb->data;
 522         u32 can_id;
 523         u32 data;
 524         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 525
 526         if (can_dropped_invalid_skb(dev, skb))
 527                 return NETDEV_TX_OK;
 528
 529         netif_stop_queue(dev);
 530
 531         if (cf->can_id & CAN_EFF_FLAG) {
 532                 can_id = cf->can_id & CAN_EFF_MASK;
 533                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 534         } else {
 535                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 536         }
 537
 538         if (cf->can_id & CAN_RTR_FLAG)
 539                 ctrl |= FLEXCAN_MB_CNT_RTR;
 540
 541         if (cf->can_dlc > 0) {
 542                 data = be32_to_cpup((__be32 *)&cf->data[0]);
 543                 priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[0]);
 544         }
 545         if (cf->can_dlc > 4) {
 546                 data = be32_to_cpup((__be32 *)&cf->data[4]);
 547                 priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[1]);
 548         }
 549
 550         can_put_echo_skb(skb, dev, 0);
 551
 552         priv->write(can_id, &regs->mb[FLEXCAN_TX_MB].can_id);
 553         priv->write(ctrl, &regs->mb[FLEXCAN_TX_MB].can_ctrl);
 554
 555         /* Errata ERR005829 step8:
 556          * Write twice INACTIVE(0x8) code to first MB.
 557          */
 558         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 559                       &priv->tx_mb_reserved->can_ctrl);
 560         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 561                       &priv->tx_mb_reserved->can_ctrl);
 562
 563         return NETDEV_TX_OK;
 564 }
 565
 566 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 567 {
 568         struct flexcan_priv *priv = netdev_priv(dev);
 569         struct flexcan_regs __iomem *regs = priv->regs;
 570         struct sk_buff *skb;
 571         struct can_frame *cf;
 572         bool rx_errors = false, tx_errors = false;
 573         u32 timestamp;
 574         int err;
 575
 576         timestamp = priv->read(&regs->timer) << 16;
 577
 578         skb = alloc_can_err_skb(dev, &cf);
 579         if (unlikely(!skb))
 580                 return;
 581
 582         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 583
 584         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 585                 netdev_dbg(dev, "BIT1_ERR irq\n");
 586                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 587                 tx_errors = true;
 588         }
 589         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 590                 netdev_dbg(dev, "BIT0_ERR irq\n");
 591                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 592                 tx_errors = true;
 593         }
 594         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 595                 netdev_dbg(dev, "ACK_ERR irq\n");
 596                 cf->can_id |= CAN_ERR_ACK;
 597                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 598                 tx_errors = true;
 599         }
 600         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 601                 netdev_dbg(dev, "CRC_ERR irq\n");
 602                 cf->data[2] |= CAN_ERR_PROT_BIT;
 603                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 604                 rx_errors = true;
 605         }
 606         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 607                 netdev_dbg(dev, "FRM_ERR irq\n");
 608                 cf->data[2] |= CAN_ERR_PROT_FORM;
 609                 rx_errors = true;
 610         }
 611         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 612                 netdev_dbg(dev, "STF_ERR irq\n");
 613                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 614                 rx_errors = true;
 615         }
 616
 617         priv->can.can_stats.bus_error++;
 618         if (rx_errors)
 619                 dev->stats.rx_errors++;
 620         if (tx_errors)
 621                 dev->stats.tx_errors++;
 622
 623         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 624         if (err)
 625                 dev->stats.rx_fifo_errors++;
 626 }
 627
 628 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 629 {
 630         struct flexcan_priv *priv = netdev_priv(dev);
 631         struct flexcan_regs __iomem *regs = priv->regs;
 632         struct sk_buff *skb;
 633         struct can_frame *cf;
 634         enum can_state new_state, rx_state, tx_state;
 635         int flt;
 636         struct can_berr_counter bec;
 637         u32 timestamp;
 638         int err;
 639
 640         timestamp = priv->read(&regs->timer) << 16;
 641
 642         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 643         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 644                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 645                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 646                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 647                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 648                 new_state = max(tx_state, rx_state);
 649         } else {
 650                 __flexcan_get_berr_counter(dev, &bec);
 651                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 652                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 653                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 654                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 655         }
 656
 657         /* state hasn't changed */
 658         if (likely(new_state == priv->can.state))
 659                 return;
 660
 661         skb = alloc_can_err_skb(dev, &cf);
 662         if (unlikely(!skb))
 663                 return;
 664
 665         can_change_state(dev, cf, tx_state, rx_state);
 666
 667         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 668                 can_bus_off(dev);
 669
 670         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 671         if (err)
 672                 dev->stats.rx_fifo_errors++;
 673 }
 674
 675 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 676 {
 677         return container_of(offload, struct flexcan_priv, offload);
 678 }
 679
 680 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 681                                          struct can_frame *cf,
 682                                          u32 *timestamp, unsigned int n)
 683 {
 684         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 685         struct flexcan_regs __iomem *regs = priv->regs;
 686         struct flexcan_mb __iomem *mb = &regs->mb[n];
 687         u32 reg_ctrl, reg_id, reg_iflag1;
 688
 689         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 690                 u32 code;
 691
 692                 do {
 693                         reg_ctrl = priv->read(&mb->can_ctrl);
 694                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 695
 696                 /* is this MB empty? */
 697                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 698                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 699                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 700                         return 0;
 701
 702                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 703                         /* This MB was overrun, we lost data */
 704                         offload->dev->stats.rx_over_errors++;
 705                         offload->dev->stats.rx_errors++;
 706                 }
 707         } else {
 708                 reg_iflag1 = priv->read(&regs->iflag1);
 709                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 710                         return 0;
 711
 712                 reg_ctrl = priv->read(&mb->can_ctrl);
 713         }
 714
 715         /* increase timstamp to full 32 bit */
 716         *timestamp = reg_ctrl << 16;
 717
 718         reg_id = priv->read(&mb->can_id);
 719         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 720                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 721         else
 722                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 723
 724         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 725                 cf->can_id |= CAN_RTR_FLAG;
 726         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 727
 728         *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
 729         *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 730
 731         /* mark as read */
 732         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 733                 /* Clear IRQ */
 734                 if (n < 32)
 735                         priv->write(BIT(n), &regs->iflag1);
 736                 else
 737                         priv->write(BIT(n - 32), &regs->iflag2);
 738         } else {
 739                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 740         }
 741
 742         /* Read the Free Running Timer. It is optional but recommended
 743          * to unlock Mailbox as soon as possible and make it available
 744          * for reception.
 745          */
 746         priv->read(&regs->timer);
 747
 748         return 1;
 749 }
 750
 751
 752 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 753 {
 754         struct flexcan_regs __iomem *regs = priv->regs;
 755         u32 iflag1, iflag2;
 756
 757         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
 758                 ~FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
 759         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
 760
 761         return (u64)iflag2 << 32 | iflag1;
 762 }
 763
 764 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 765 {
 766         struct net_device *dev = dev_id;
 767         struct net_device_stats *stats = &dev->stats;
 768         struct flexcan_priv *priv = netdev_priv(dev);
 769         struct flexcan_regs __iomem *regs = priv->regs;
 770         irqreturn_t handled = IRQ_NONE;
 771         u32 reg_iflag2, reg_esr;
 772         enum can_state last_state = priv->can.state;
 773
 774         /* reception interrupt */
 775         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 776                 u64 reg_iflag;
 777                 int ret;
 778
 779                 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 780                         handled = IRQ_HANDLED;
 781                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 782                                                                    reg_iflag);
 783                         if (!ret)
 784                                 break;
 785                 }
 786         } else {
 787                 u32 reg_iflag1;
 788
 789                 reg_iflag1 = priv->read(&regs->iflag1);
 790                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 791                         handled = IRQ_HANDLED;
 792                         can_rx_offload_irq_offload_fifo(&priv->offload);
 793                 }
 794
 795                 /* FIFO overflow interrupt */
 796                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 797                         handled = IRQ_HANDLED;
 798                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 799                                     &regs->iflag1);
 800                         dev->stats.rx_over_errors++;
 801                         dev->stats.rx_errors++;
 802                 }
 803         }
 804
 805         reg_iflag2 = priv->read(&regs->iflag2);
 806
 807         /* transmission complete interrupt */
 808         if (reg_iflag2 & FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB)) {
 809                 u32 reg_ctrl = priv->read(&regs->mb[FLEXCAN_TX_MB].can_ctrl);
 810
 811                 handled = IRQ_HANDLED;
 812                 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 813                                                                0, reg_ctrl << 16);
 814                 stats->tx_packets++;
 815                 can_led_event(dev, CAN_LED_EVENT_TX);
 816
 817                 /* after sending a RTR frame MB is in RX mode */
 818                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 819                             &regs->mb[FLEXCAN_TX_MB].can_ctrl);
 820                 priv->write(FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB), &regs->iflag2);
 821                 netif_wake_queue(dev);
 822         }
 823
 824         reg_esr = priv->read(&regs->esr);
 825
 826         /* ACK all bus error and state change IRQ sources */
 827         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 828                 handled = IRQ_HANDLED;
 829                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 830         }
 831
 832         /* state change interrupt or broken error state quirk fix is enabled */
 833         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 834             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 835                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 836                 flexcan_irq_state(dev, reg_esr);
 837
 838         /* bus error IRQ - handle if bus error reporting is activated */
 839         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 840             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 841                 flexcan_irq_bus_err(dev, reg_esr);
 842
 843         /* availability of error interrupt among state transitions in case
 844          * bus error reporting is de-activated and
 845          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 846          *  +--------------------------------------------------------------+
 847          *  | +----------------------------------------------+ [stopped /  |
 848          *  | |                                              |  sleeping] -+
 849          *  +-+-> active <-> warning <-> passive -> bus off -+
 850          *        ___________^^^^^^^^^^^^_______________________________
 851          *        disabled(1)  enabled             disabled
 852          *
 853          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 854          */
 855         if ((last_state != priv->can.state) &&
 856             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 857             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 858                 switch (priv->can.state) {
 859                 case CAN_STATE_ERROR_ACTIVE:
 860                         if (priv->devtype_data->quirks &
 861                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 862                                 flexcan_error_irq_enable(priv);
 863                         else
 864                                 flexcan_error_irq_disable(priv);
 865                         break;
 866
 867                 case CAN_STATE_ERROR_WARNING:
 868                         flexcan_error_irq_enable(priv);
 869                         break;
 870
 871                 case CAN_STATE_ERROR_PASSIVE:
 872                 case CAN_STATE_BUS_OFF:
 873                         flexcan_error_irq_disable(priv);
 874                         break;
 875
 876                 default:
 877                         break;
 878                 }
 879         }
 880
 881         return handled;
 882 }
 883
 884 static void flexcan_set_bittiming(struct net_device *dev)
 885 {
 886         const struct flexcan_priv *priv = netdev_priv(dev);
 887         const struct can_bittiming *bt = &priv->can.bittiming;
 888         struct flexcan_regs __iomem *regs = priv->regs;
 889         u32 reg;
 890
 891         reg = priv->read(&regs->ctrl);
 892         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 893                  FLEXCAN_CTRL_RJW(0x3) |
 894                  FLEXCAN_CTRL_PSEG1(0x7) |
 895                  FLEXCAN_CTRL_PSEG2(0x7) |
 896                  FLEXCAN_CTRL_PROPSEG(0x7) |
 897                  FLEXCAN_CTRL_LPB |
 898                  FLEXCAN_CTRL_SMP |
 899                  FLEXCAN_CTRL_LOM);
 900
 901         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 902                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 903                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 904                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 905                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 906
 907         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 908                 reg |= FLEXCAN_CTRL_LPB;
 909         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 910                 reg |= FLEXCAN_CTRL_LOM;
 911         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 912                 reg |= FLEXCAN_CTRL_SMP;
 913
 914         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
 915         priv->write(reg, &regs->ctrl);
 916
 917         /* print chip status */
 918         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 919                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
 920 }
 921
 922 /* flexcan_chip_start
 923  *
 924  * this functions is entered with clocks enabled
 925  *
 926  */
 927 static int flexcan_chip_start(struct net_device *dev)
 928 {
 929         struct flexcan_priv *priv = netdev_priv(dev);
 930         struct flexcan_regs __iomem *regs = priv->regs;
 931         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
 932         int err, i;
 933
 934         /* enable module */
 935         err = flexcan_chip_enable(priv);
 936         if (err)
 937                 return err;
 938
 939         /* soft reset */
 940         err = flexcan_chip_softreset(priv);
 941         if (err)
 942                 goto out_chip_disable;
 943
 944         flexcan_set_bittiming(dev);
 945
 946         /* MCR
 947          *
 948          * enable freeze
 949          * enable fifo
 950          * halt now
 951          * only supervisor access
 952          * enable warning int
 953          * disable local echo
 954          * enable individual RX masking
 955          * choose format C
 956          * set max mailbox number
 957          */
 958         reg_mcr = priv->read(&regs->mcr);
 959         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 960         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
 961                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
 962                 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_MB);
 963
 964         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
 965                 reg_mcr &= ~FLEXCAN_MCR_FEN;
 966         else
 967                 reg_mcr |= FLEXCAN_MCR_FEN;
 968
 969         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 970         priv->write(reg_mcr, &regs->mcr);
 971
 972         /* CTRL
 973          *
 974          * disable timer sync feature
 975          *
 976          * disable auto busoff recovery
 977          * transmit lowest buffer first
 978          *
 979          * enable tx and rx warning interrupt
 980          * enable bus off interrupt
 981          * (== FLEXCAN_CTRL_ERR_STATE)
 982          */
 983         reg_ctrl = priv->read(&regs->ctrl);
 984         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 985         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 986                 FLEXCAN_CTRL_ERR_STATE;
 987
 988         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
 989          * on most Flexcan cores, too. Otherwise we don't get
 990          * any error warning or passive interrupts.
 991          */
 992         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
 993             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
 994                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
 995         else
 996                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
 997
 998         /* save for later use */
 999         priv->reg_ctrl_default = reg_ctrl;
1000         /* leave interrupts disabled for now */
1001         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1002         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1003         priv->write(reg_ctrl, &regs->ctrl);
1004
1005         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1006                 reg_ctrl2 = priv->read(&regs->ctrl2);
1007                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1008                 priv->write(reg_ctrl2, &regs->ctrl2);
1009         }
1010
1011         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1012                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1013                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1014                                     &regs->mb[i].can_ctrl);
1015                 }
1016         } else {
1017                 /* clear and invalidate unused mailboxes first */
1018                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < ARRAY_SIZE(regs->mb); i++) {
1019                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1020                                     &regs->mb[i].can_ctrl);
1021                 }
1022         }
1023
1024         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1025         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1026                     &priv->tx_mb_reserved->can_ctrl);
1027
1028         /* mark TX mailbox as INACTIVE */
1029         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1030                     &regs->mb[FLEXCAN_TX_MB].can_ctrl);
1031
1032         /* acceptance mask/acceptance code (accept everything) */
1033         priv->write(0x0, &regs->rxgmask);
1034         priv->write(0x0, &regs->rx14mask);
1035         priv->write(0x0, &regs->rx15mask);
1036
1037         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1038                 priv->write(0x0, &regs->rxfgmask);
1039
1040         /* clear acceptance filters */
1041         for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1042                 priv->write(0, &regs->rximr[i]);
1043
1044         /* On Vybrid, disable memory error detection interrupts
1045          * and freeze mode.
1046          * This also works around errata e5295 which generates
1047          * false positive memory errors and put the device in
1048          * freeze mode.
1049          */
1050         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1051                 /* Follow the protocol as described in "Detection
1052                  * and Correction of Memory Errors" to write to
1053                  * MECR register
1054                  */
1055                 reg_ctrl2 = priv->read(&regs->ctrl2);
1056                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1057                 priv->write(reg_ctrl2, &regs->ctrl2);
1058
1059                 reg_mecr = priv->read(&regs->mecr);
1060                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1061                 priv->write(reg_mecr, &regs->mecr);
1062                 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1063                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1064                               FLEXCAN_MECR_FANCEI_MSK);
1065                 priv->write(reg_mecr, &regs->mecr);
1066         }
1067
1068         err = flexcan_transceiver_enable(priv);
1069         if (err)
1070                 goto out_chip_disable;
1071
1072         /* synchronize with the can bus */
1073         err = flexcan_chip_unfreeze(priv);
1074         if (err)
1075                 goto out_transceiver_disable;
1076
1077         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1078
1079         /* enable interrupts atomically */
1080         disable_irq(dev->irq);
1081         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1082         priv->write(priv->reg_imask1_default, &regs->imask1);
1083         priv->write(priv->reg_imask2_default, &regs->imask2);
1084         enable_irq(dev->irq);
1085
1086         /* print chip status */
1087         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1088                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1089
1090         return 0;
1091
1092  out_transceiver_disable:
1093         flexcan_transceiver_disable(priv);
1094  out_chip_disable:
1095         flexcan_chip_disable(priv);
1096         return err;
1097 }
1098
1099 /* __flexcan_chip_stop
1100  *
1101  * this function is entered with clocks enabled
1102  */
1103 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1104 {
1105         struct flexcan_priv *priv = netdev_priv(dev);
1106         struct flexcan_regs __iomem *regs = priv->regs;
1107         int err;
1108
1109         /* freeze + disable module */
1110         err = flexcan_chip_freeze(priv);
1111         if (err && !disable_on_error)
1112                 return err;
1113         err = flexcan_chip_disable(priv);
1114         if (err && !disable_on_error)
1115                 goto out_chip_unfreeze;
1116
1117         /* Disable all interrupts */
1118         priv->write(0, &regs->imask2);
1119         priv->write(0, &regs->imask1);
1120         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1121                     &regs->ctrl);
1122
1123         flexcan_transceiver_disable(priv);
1124         priv->can.state = CAN_STATE_STOPPED;
1125
1126         return 0;
1127
1128  out_chip_unfreeze:
1129         flexcan_chip_unfreeze(priv);
1130
1131         return err;
1132 }
1133
1134 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1135 {
1136         return __flexcan_chip_stop(dev, true);
1137 }
1138
1139 static inline int flexcan_chip_stop(struct net_device *dev)
1140 {
1141         return __flexcan_chip_stop(dev, false);
1142 }
1143
1144 static int flexcan_open(struct net_device *dev)
1145 {
1146         struct flexcan_priv *priv = netdev_priv(dev);
1147         int err;
1148
1149         err = clk_prepare_enable(priv->clk_ipg);
1150         if (err)
1151                 return err;
1152
1153         err = clk_prepare_enable(priv->clk_per);
1154         if (err)
1155                 goto out_disable_ipg;
1156
1157         err = open_candev(dev);
1158         if (err)
1159                 goto out_disable_per;
1160
1161         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1162         if (err)
1163                 goto out_close;
1164
1165         /* start chip and queuing */
1166         err = flexcan_chip_start(dev);
1167         if (err)
1168                 goto out_free_irq;
1169
1170         can_led_event(dev, CAN_LED_EVENT_OPEN);
1171
1172         can_rx_offload_enable(&priv->offload);
1173         netif_start_queue(dev);
1174
1175         return 0;
1176
1177  out_free_irq:
1178         free_irq(dev->irq, dev);
1179  out_close:
1180         close_candev(dev);
1181  out_disable_per:
1182         clk_disable_unprepare(priv->clk_per);
1183  out_disable_ipg:
1184         clk_disable_unprepare(priv->clk_ipg);
1185
1186         return err;
1187 }
1188
1189 static int flexcan_close(struct net_device *dev)
1190 {
1191         struct flexcan_priv *priv = netdev_priv(dev);
1192
1193         netif_stop_queue(dev);
1194         can_rx_offload_disable(&priv->offload);
1195         flexcan_chip_stop_disable_on_error(dev);
1196
1197         free_irq(dev->irq, dev);
1198         clk_disable_unprepare(priv->clk_per);
1199         clk_disable_unprepare(priv->clk_ipg);
1200
1201         close_candev(dev);
1202
1203         can_led_event(dev, CAN_LED_EVENT_STOP);
1204
1205         return 0;
1206 }
1207
1208 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1209 {
1210         int err;
1211
1212         switch (mode) {
1213         case CAN_MODE_START:
1214                 err = flexcan_chip_start(dev);
1215                 if (err)
1216                         return err;
1217
1218                 netif_wake_queue(dev);
1219                 break;
1220
1221         default:
1222                 return -EOPNOTSUPP;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static const struct net_device_ops flexcan_netdev_ops = {
1229         .ndo_open       = flexcan_open,
1230         .ndo_stop       = flexcan_close,
1231         .ndo_start_xmit = flexcan_start_xmit,
1232         .ndo_change_mtu = can_change_mtu,
1233 };
1234
1235 static int register_flexcandev(struct net_device *dev)
1236 {
1237         struct flexcan_priv *priv = netdev_priv(dev);
1238         struct flexcan_regs __iomem *regs = priv->regs;
1239         u32 reg, err;
1240
1241         err = clk_prepare_enable(priv->clk_ipg);
1242         if (err)
1243                 return err;
1244
1245         err = clk_prepare_enable(priv->clk_per);
1246         if (err)
1247                 goto out_disable_ipg;
1248
1249         /* select "bus clock", chip must be disabled */
1250         err = flexcan_chip_disable(priv);
1251         if (err)
1252                 goto out_disable_per;
1253         reg = priv->read(&regs->ctrl);
1254         reg |= FLEXCAN_CTRL_CLK_SRC;
1255         priv->write(reg, &regs->ctrl);
1256
1257         err = flexcan_chip_enable(priv);
1258         if (err)
1259                 goto out_chip_disable;
1260
1261         /* set freeze, halt */
1262         err = flexcan_chip_freeze(priv);
1263         if (err)
1264                 goto out_chip_disable;
1265
1266         /* activate FIFO, restrict register access */
1267         reg = priv->read(&regs->mcr);
1268         reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1269         priv->write(reg, &regs->mcr);
1270
1271         /* Currently we only support newer versions of this core
1272          * featuring a RX hardware FIFO (although this driver doesn't
1273          * make use of it on some cores). Older cores, found on some
1274          * Coldfire derivates are not tested.
1275          */
1276         reg = priv->read(&regs->mcr);
1277         if (!(reg & FLEXCAN_MCR_FEN)) {
1278                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1279                 err = -ENODEV;
1280                 goto out_chip_disable;
1281         }
1282
1283         err = register_candev(dev);
1284
1285         /* disable core and turn off clocks */
1286  out_chip_disable:
1287         flexcan_chip_disable(priv);
1288  out_disable_per:
1289         clk_disable_unprepare(priv->clk_per);
1290  out_disable_ipg:
1291         clk_disable_unprepare(priv->clk_ipg);
1292
1293         return err;
1294 }
1295
1296 static void unregister_flexcandev(struct net_device *dev)
1297 {
1298         unregister_candev(dev);
1299 }
1300
1301 static const struct of_device_id flexcan_of_match[] = {
1302         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1303         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1304         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1305         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1306         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1307         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1308         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1309         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1310         { /* sentinel */ },
1311 };
1312 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1313
1314 static const struct platform_device_id flexcan_id_table[] = {
1315         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1316         { /* sentinel */ },
1317 };
1318 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1319
1320 static int flexcan_probe(struct platform_device *pdev)
1321 {
1322         const struct of_device_id *of_id;
1323         const struct flexcan_devtype_data *devtype_data;
1324         struct net_device *dev;
1325         struct flexcan_priv *priv;
1326         struct regulator *reg_xceiver;
1327         struct resource *mem;
1328         struct clk *clk_ipg = NULL, *clk_per = NULL;
1329         struct flexcan_regs __iomem *regs;
1330         int err, irq;
1331         u32 clock_freq = 0;
1332
1333         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1334         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1335                 return -EPROBE_DEFER;
1336         else if (IS_ERR(reg_xceiver))
1337                 reg_xceiver = NULL;
1338
1339         if (pdev->dev.of_node)
1340                 of_property_read_u32(pdev->dev.of_node,
1341                                      "clock-frequency", &clock_freq);
1342
1343         if (!clock_freq) {
1344                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1345                 if (IS_ERR(clk_ipg)) {
1346                         dev_err(&pdev->dev, "no ipg clock defined\n");
1347                         return PTR_ERR(clk_ipg);
1348                 }
1349
1350                 clk_per = devm_clk_get(&pdev->dev, "per");
1351                 if (IS_ERR(clk_per)) {
1352                         dev_err(&pdev->dev, "no per clock defined\n");
1353                         return PTR_ERR(clk_per);
1354                 }
1355                 clock_freq = clk_get_rate(clk_per);
1356         }
1357
1358         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359         irq = platform_get_irq(pdev, 0);
1360         if (irq <= 0)
1361                 return -ENODEV;
1362
1363         regs = devm_ioremap_resource(&pdev->dev, mem);
1364         if (IS_ERR(regs))
1365                 return PTR_ERR(regs);
1366
1367         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1368         if (of_id) {
1369                 devtype_data = of_id->data;
1370         } else if (platform_get_device_id(pdev)->driver_data) {
1371                 devtype_data = (struct flexcan_devtype_data *)
1372                         platform_get_device_id(pdev)->driver_data;
1373         } else {
1374                 return -ENODEV;
1375         }
1376
1377         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1378         if (!dev)
1379                 return -ENOMEM;
1380
1381         platform_set_drvdata(pdev, dev);
1382         SET_NETDEV_DEV(dev, &pdev->dev);
1383
1384         dev->netdev_ops = &flexcan_netdev_ops;
1385         dev->irq = irq;
1386         dev->flags |= IFF_ECHO;
1387
1388         priv = netdev_priv(dev);
1389
1390         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1391             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1392                 priv->read = flexcan_read_be;
1393                 priv->write = flexcan_write_be;
1394         } else {
1395                 priv->read = flexcan_read_le;
1396                 priv->write = flexcan_write_le;
1397         }
1398
1399         priv->can.clock.freq = clock_freq;
1400         priv->can.bittiming_const = &flexcan_bittiming_const;
1401         priv->can.do_set_mode = flexcan_set_mode;
1402         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1403         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1404                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1405                 CAN_CTRLMODE_BERR_REPORTING;
1406         priv->regs = regs;
1407         priv->clk_ipg = clk_ipg;
1408         priv->clk_per = clk_per;
1409         priv->devtype_data = devtype_data;
1410         priv->reg_xceiver = reg_xceiver;
1411
1412         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1413                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1414         else
1415                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1416
1417         priv->reg_imask1_default = 0;
1418         priv->reg_imask2_default = FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
1419
1420         priv->offload.mailbox_read = flexcan_mailbox_read;
1421
1422         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1423                 u64 imask;
1424
1425                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1426                 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1427
1428                 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1429                 priv->reg_imask1_default |= imask;
1430                 priv->reg_imask2_default |= imask >> 32;
1431
1432                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1433         } else {
1434                 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1435                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1436                 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1437         }
1438         if (err)
1439                 goto failed_offload;
1440
1441         err = register_flexcandev(dev);
1442         if (err) {
1443                 dev_err(&pdev->dev, "registering netdev failed\n");
1444                 goto failed_register;
1445         }
1446
1447         devm_can_led_init(dev);
1448
1449         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1450                  priv->regs, dev->irq);
1451
1452         return 0;
1453
1454  failed_offload:
1455  failed_register:
1456         free_candev(dev);
1457         return err;
1458 }
1459
1460 static int flexcan_remove(struct platform_device *pdev)
1461 {
1462         struct net_device *dev = platform_get_drvdata(pdev);
1463         struct flexcan_priv *priv = netdev_priv(dev);
1464
1465         unregister_flexcandev(dev);
1466         can_rx_offload_del(&priv->offload);
1467         free_candev(dev);
1468
1469         return 0;
1470 }
1471
1472 static int __maybe_unused flexcan_suspend(struct device *device)
1473 {
1474         struct net_device *dev = dev_get_drvdata(device);
1475         struct flexcan_priv *priv = netdev_priv(dev);
1476         int err;
1477
1478         if (netif_running(dev)) {
1479                 err = flexcan_chip_disable(priv);
1480                 if (err)
1481                         return err;
1482                 netif_stop_queue(dev);
1483                 netif_device_detach(dev);
1484         }
1485         priv->can.state = CAN_STATE_SLEEPING;
1486
1487         return 0;
1488 }
1489
1490 static int __maybe_unused flexcan_resume(struct device *device)
1491 {
1492         struct net_device *dev = dev_get_drvdata(device);
1493         struct flexcan_priv *priv = netdev_priv(dev);
1494         int err;
1495
1496         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1497         if (netif_running(dev)) {
1498                 netif_device_attach(dev);
1499                 netif_start_queue(dev);
1500                 err = flexcan_chip_enable(priv);
1501                 if (err)
1502                         return err;
1503         }
1504         return 0;
1505 }
1506
1507 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1508
1509 static struct platform_driver flexcan_driver = {
1510         .driver = {
1511                 .name = DRV_NAME,
1512                 .pm = &flexcan_pm_ops,
1513                 .of_match_table = flexcan_of_match,
1514         },
1515         .probe = flexcan_probe,
1516         .remove = flexcan_remove,
1517         .id_table = flexcan_id_table,
1518 };
1519
1520 module_platform_driver(flexcan_driver);
1521
1522 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1523               "Marc Kleine-Budde <kernel@pengutronix.de>");
1524 MODULE_LICENSE("GPL v2");
1525 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");