2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <linux/netdevice.h>
24 #include <linux/can.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/can/rx-offload.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
33 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
39 #define DRV_NAME "flexcan"
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_IRMQ BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94 /* FLEXCAN control register 2 (CTRL2) bits */
95 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
96 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99 #define FLEXCAN_CTRL2_MRP BIT(18)
100 #define FLEXCAN_CTRL2_RRS BIT(17)
101 #define FLEXCAN_CTRL2_EACEN BIT(16)
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
147 /* FLEXCAN interrupt flag register (IFLAG) bits */
148 /* Errata ERR005829 step7: Reserve first valid MB */
149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150 #define FLEXCAN_TX_MB_OFF_FIFO 9
151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155 #define FLEXCAN_IFLAG_MB(x) BIT(x)
156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
169 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
174 #define FLEXCAN_MB_CNT_SRR BIT(22)
175 #define FLEXCAN_MB_CNT_IDE BIT(21)
176 #define FLEXCAN_MB_CNT_RTR BIT(20)
177 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
180 #define FLEXCAN_TIMEOUT_US (250)
182 /* FLEXCAN hardware feature flags
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
186 * Filter? connected? Passive detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no ? no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
189 * MX35 FlexCAN2 03.00.00.00 no no ? no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
192 * VF610 FlexCAN3 ? no yes no yes yes?
194 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
196 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
197 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
198 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
199 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
200 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
201 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
203 /* Structure of the message buffer */
210 /* Structure of the hardware registers */
211 struct flexcan_regs {
214 u32 timer; /* 0x08 */
215 u32 _reserved1; /* 0x0c */
216 u32 rxgmask; /* 0x10 */
217 u32 rx14mask; /* 0x14 */
218 u32 rx15mask; /* 0x18 */
221 u32 imask2; /* 0x24 */
222 u32 imask1; /* 0x28 */
223 u32 iflag2; /* 0x2c */
224 u32 iflag1; /* 0x30 */
226 u32 gfwr_mx28; /* MX28, MX53 */
227 u32 ctrl2; /* MX6, VF610 */
230 u32 imeur; /* 0x3c */
233 u32 rxfgmask; /* 0x48 */
234 u32 rxfir; /* 0x4c */
235 u32 _reserved3[12]; /* 0x50 */
236 struct flexcan_mb mb[64]; /* 0x80 */
239 * 0x080...0x08f 0 RX message buffer
240 * 0x090...0x0df 1-5 reserverd
241 * 0x0e0...0x0ff 6-7 8 entry ID table
242 * (mx25, mx28, mx35, mx53)
243 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
244 * size conf'ed via ctrl2::RFFN
247 u32 _reserved4[256]; /* 0x480 */
248 u32 rximr[64]; /* 0x880 */
249 u32 _reserved5[24]; /* 0x980 */
250 u32 gfwr_mx6; /* 0x9e0 - MX6 */
251 u32 _reserved6[63]; /* 0x9e4 */
252 u32 mecr; /* 0xae0 */
253 u32 erriar; /* 0xae4 */
254 u32 erridpr; /* 0xae8 */
255 u32 errippr; /* 0xaec */
256 u32 rerrar; /* 0xaf0 */
257 u32 rerrdr; /* 0xaf4 */
258 u32 rerrsynr; /* 0xaf8 */
259 u32 errsr; /* 0xafc */
262 struct flexcan_devtype_data {
263 u32 quirks; /* quirks needed for different IP cores */
266 struct flexcan_priv {
268 struct can_rx_offload offload;
270 struct flexcan_regs __iomem *regs;
271 struct flexcan_mb __iomem *tx_mb;
272 struct flexcan_mb __iomem *tx_mb_reserved;
274 u32 reg_ctrl_default;
275 u32 reg_imask1_default;
276 u32 reg_imask2_default;
280 const struct flexcan_devtype_data *devtype_data;
281 struct regulator *reg_xceiver;
284 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
285 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
286 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
289 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
290 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
293 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
294 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
295 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
298 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
299 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
300 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
301 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
304 static const struct can_bittiming_const flexcan_bittiming_const = {
316 /* Abstract off the read/write for arm versus ppc. This
317 * assumes that PPC uses big-endian registers and everything
318 * else uses little-endian registers, independent of CPU
321 #if defined(CONFIG_PPC)
322 static inline u32 flexcan_read(void __iomem *addr)
324 return in_be32(addr);
327 static inline void flexcan_write(u32 val, void __iomem *addr)
332 static inline u32 flexcan_read(void __iomem *addr)
337 static inline void flexcan_write(u32 val, void __iomem *addr)
343 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
345 struct flexcan_regs __iomem *regs = priv->regs;
346 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
348 flexcan_write(reg_ctrl, ®s->ctrl);
351 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
353 struct flexcan_regs __iomem *regs = priv->regs;
354 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
356 flexcan_write(reg_ctrl, ®s->ctrl);
359 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
361 if (!priv->reg_xceiver)
364 return regulator_enable(priv->reg_xceiver);
367 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
369 if (!priv->reg_xceiver)
372 return regulator_disable(priv->reg_xceiver);
375 static int flexcan_chip_enable(struct flexcan_priv *priv)
377 struct flexcan_regs __iomem *regs = priv->regs;
378 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
381 reg = flexcan_read(®s->mcr);
382 reg &= ~FLEXCAN_MCR_MDIS;
383 flexcan_write(reg, ®s->mcr);
385 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
388 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
394 static int flexcan_chip_disable(struct flexcan_priv *priv)
396 struct flexcan_regs __iomem *regs = priv->regs;
397 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
400 reg = flexcan_read(®s->mcr);
401 reg |= FLEXCAN_MCR_MDIS;
402 flexcan_write(reg, ®s->mcr);
404 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
407 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
413 static int flexcan_chip_freeze(struct flexcan_priv *priv)
415 struct flexcan_regs __iomem *regs = priv->regs;
416 unsigned int timeout;
417 u32 bitrate = priv->can.bittiming.bitrate;
421 timeout = 1000 * 1000 * 10 / bitrate;
423 timeout = FLEXCAN_TIMEOUT_US / 10;
425 reg = flexcan_read(®s->mcr);
426 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
427 flexcan_write(reg, ®s->mcr);
429 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
432 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
438 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
440 struct flexcan_regs __iomem *regs = priv->regs;
441 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
444 reg = flexcan_read(®s->mcr);
445 reg &= ~FLEXCAN_MCR_HALT;
446 flexcan_write(reg, ®s->mcr);
448 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
451 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
457 static int flexcan_chip_softreset(struct flexcan_priv *priv)
459 struct flexcan_regs __iomem *regs = priv->regs;
460 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
462 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
463 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
466 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
472 static int __flexcan_get_berr_counter(const struct net_device *dev,
473 struct can_berr_counter *bec)
475 const struct flexcan_priv *priv = netdev_priv(dev);
476 struct flexcan_regs __iomem *regs = priv->regs;
477 u32 reg = flexcan_read(®s->ecr);
479 bec->txerr = (reg >> 0) & 0xff;
480 bec->rxerr = (reg >> 8) & 0xff;
485 static int flexcan_get_berr_counter(const struct net_device *dev,
486 struct can_berr_counter *bec)
488 const struct flexcan_priv *priv = netdev_priv(dev);
491 err = clk_prepare_enable(priv->clk_ipg);
495 err = clk_prepare_enable(priv->clk_per);
497 goto out_disable_ipg;
499 err = __flexcan_get_berr_counter(dev, bec);
501 clk_disable_unprepare(priv->clk_per);
503 clk_disable_unprepare(priv->clk_ipg);
508 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
510 const struct flexcan_priv *priv = netdev_priv(dev);
511 struct can_frame *cf = (struct can_frame *)skb->data;
514 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
516 if (can_dropped_invalid_skb(dev, skb))
519 netif_stop_queue(dev);
521 if (cf->can_id & CAN_EFF_FLAG) {
522 can_id = cf->can_id & CAN_EFF_MASK;
523 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
525 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
528 if (cf->can_id & CAN_RTR_FLAG)
529 ctrl |= FLEXCAN_MB_CNT_RTR;
531 if (cf->can_dlc > 0) {
532 data = be32_to_cpup((__be32 *)&cf->data[0]);
533 flexcan_write(data, &priv->tx_mb->data[0]);
535 if (cf->can_dlc > 4) {
536 data = be32_to_cpup((__be32 *)&cf->data[4]);
537 flexcan_write(data, &priv->tx_mb->data[1]);
540 can_put_echo_skb(skb, dev, 0);
542 flexcan_write(can_id, &priv->tx_mb->can_id);
543 flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
545 /* Errata ERR005829 step8:
546 * Write twice INACTIVE(0x8) code to first MB.
548 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
549 &priv->tx_mb_reserved->can_ctrl);
550 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
551 &priv->tx_mb_reserved->can_ctrl);
556 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
558 struct flexcan_priv *priv = netdev_priv(dev);
560 struct can_frame *cf;
561 bool rx_errors = false, tx_errors = false;
563 skb = alloc_can_err_skb(dev, &cf);
567 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
569 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
570 netdev_dbg(dev, "BIT1_ERR irq\n");
571 cf->data[2] |= CAN_ERR_PROT_BIT1;
574 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
575 netdev_dbg(dev, "BIT0_ERR irq\n");
576 cf->data[2] |= CAN_ERR_PROT_BIT0;
579 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
580 netdev_dbg(dev, "ACK_ERR irq\n");
581 cf->can_id |= CAN_ERR_ACK;
582 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
585 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
586 netdev_dbg(dev, "CRC_ERR irq\n");
587 cf->data[2] |= CAN_ERR_PROT_BIT;
588 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
591 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
592 netdev_dbg(dev, "FRM_ERR irq\n");
593 cf->data[2] |= CAN_ERR_PROT_FORM;
596 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
597 netdev_dbg(dev, "STF_ERR irq\n");
598 cf->data[2] |= CAN_ERR_PROT_STUFF;
602 priv->can.can_stats.bus_error++;
604 dev->stats.rx_errors++;
606 dev->stats.tx_errors++;
608 can_rx_offload_queue_tail(&priv->offload, skb);
611 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
613 struct flexcan_priv *priv = netdev_priv(dev);
615 struct can_frame *cf;
616 enum can_state new_state, rx_state, tx_state;
618 struct can_berr_counter bec;
620 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
621 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
622 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
623 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
624 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
625 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
626 new_state = max(tx_state, rx_state);
628 __flexcan_get_berr_counter(dev, &bec);
629 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
630 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
631 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
632 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
635 /* state hasn't changed */
636 if (likely(new_state == priv->can.state))
639 skb = alloc_can_err_skb(dev, &cf);
643 can_change_state(dev, cf, tx_state, rx_state);
645 if (unlikely(new_state == CAN_STATE_BUS_OFF))
648 can_rx_offload_queue_tail(&priv->offload, skb);
651 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
653 return container_of(offload, struct flexcan_priv, offload);
656 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
657 struct can_frame *cf,
658 u32 *timestamp, unsigned int n)
660 struct flexcan_priv *priv = rx_offload_to_priv(offload);
661 struct flexcan_regs __iomem *regs = priv->regs;
662 struct flexcan_mb __iomem *mb = ®s->mb[n];
663 u32 reg_ctrl, reg_id, reg_iflag1;
665 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
669 reg_ctrl = flexcan_read(&mb->can_ctrl);
670 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
672 /* is this MB empty? */
673 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
674 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
675 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
678 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
679 /* This MB was overrun, we lost data */
680 offload->dev->stats.rx_over_errors++;
681 offload->dev->stats.rx_errors++;
684 reg_iflag1 = flexcan_read(®s->iflag1);
685 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
688 reg_ctrl = flexcan_read(&mb->can_ctrl);
691 /* increase timstamp to full 32 bit */
692 *timestamp = reg_ctrl << 16;
694 reg_id = flexcan_read(&mb->can_id);
695 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
696 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
698 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
700 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
701 cf->can_id |= CAN_RTR_FLAG;
702 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
704 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
705 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
708 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
711 flexcan_write(BIT(n), ®s->iflag1);
713 flexcan_write(BIT(n - 32), ®s->iflag2);
715 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
716 flexcan_read(®s->timer);
723 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
725 struct flexcan_regs __iomem *regs = priv->regs;
728 iflag2 = flexcan_read(®s->iflag2) & priv->reg_imask2_default;
729 iflag1 = flexcan_read(®s->iflag1) & priv->reg_imask1_default &
730 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
732 return (u64)iflag2 << 32 | iflag1;
735 static irqreturn_t flexcan_irq(int irq, void *dev_id)
737 struct net_device *dev = dev_id;
738 struct net_device_stats *stats = &dev->stats;
739 struct flexcan_priv *priv = netdev_priv(dev);
740 struct flexcan_regs __iomem *regs = priv->regs;
741 irqreturn_t handled = IRQ_NONE;
742 u32 reg_iflag1, reg_esr;
743 enum can_state last_state = priv->can.state;
745 reg_iflag1 = flexcan_read(®s->iflag1);
747 /* reception interrupt */
748 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
752 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
753 handled = IRQ_HANDLED;
754 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
760 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
761 handled = IRQ_HANDLED;
762 can_rx_offload_irq_offload_fifo(&priv->offload);
765 /* FIFO overflow interrupt */
766 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
767 handled = IRQ_HANDLED;
768 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
769 dev->stats.rx_over_errors++;
770 dev->stats.rx_errors++;
774 /* transmission complete interrupt */
775 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
776 handled = IRQ_HANDLED;
777 stats->tx_bytes += can_get_echo_skb(dev, 0);
779 can_led_event(dev, CAN_LED_EVENT_TX);
781 /* after sending a RTR frame MB is in RX mode */
782 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
783 &priv->tx_mb->can_ctrl);
784 flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
785 netif_wake_queue(dev);
788 reg_esr = flexcan_read(®s->esr);
790 /* ACK all bus error and state change IRQ sources */
791 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
792 handled = IRQ_HANDLED;
793 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
796 /* state change interrupt or broken error state quirk fix is enabled */
797 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
798 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
799 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
800 flexcan_irq_state(dev, reg_esr);
802 /* bus error IRQ - handle if bus error reporting is activated */
803 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
804 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
805 flexcan_irq_bus_err(dev, reg_esr);
807 /* availability of error interrupt among state transitions in case
808 * bus error reporting is de-activated and
809 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
810 * +--------------------------------------------------------------+
811 * | +----------------------------------------------+ [stopped / |
813 * +-+-> active <-> warning <-> passive -> bus off -+
814 * ___________^^^^^^^^^^^^_______________________________
815 * disabled(1) enabled disabled
817 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
819 if ((last_state != priv->can.state) &&
820 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
821 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
822 switch (priv->can.state) {
823 case CAN_STATE_ERROR_ACTIVE:
824 if (priv->devtype_data->quirks &
825 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
826 flexcan_error_irq_enable(priv);
828 flexcan_error_irq_disable(priv);
831 case CAN_STATE_ERROR_WARNING:
832 flexcan_error_irq_enable(priv);
835 case CAN_STATE_ERROR_PASSIVE:
836 case CAN_STATE_BUS_OFF:
837 flexcan_error_irq_disable(priv);
848 static void flexcan_set_bittiming(struct net_device *dev)
850 const struct flexcan_priv *priv = netdev_priv(dev);
851 const struct can_bittiming *bt = &priv->can.bittiming;
852 struct flexcan_regs __iomem *regs = priv->regs;
855 reg = flexcan_read(®s->ctrl);
856 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
857 FLEXCAN_CTRL_RJW(0x3) |
858 FLEXCAN_CTRL_PSEG1(0x7) |
859 FLEXCAN_CTRL_PSEG2(0x7) |
860 FLEXCAN_CTRL_PROPSEG(0x7) |
865 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
866 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
867 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
868 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
869 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
871 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
872 reg |= FLEXCAN_CTRL_LPB;
873 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
874 reg |= FLEXCAN_CTRL_LOM;
875 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
876 reg |= FLEXCAN_CTRL_SMP;
878 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
879 flexcan_write(reg, ®s->ctrl);
881 /* print chip status */
882 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
883 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
886 /* flexcan_chip_start
888 * this functions is entered with clocks enabled
891 static int flexcan_chip_start(struct net_device *dev)
893 struct flexcan_priv *priv = netdev_priv(dev);
894 struct flexcan_regs __iomem *regs = priv->regs;
895 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
899 err = flexcan_chip_enable(priv);
904 err = flexcan_chip_softreset(priv);
906 goto out_chip_disable;
908 flexcan_set_bittiming(dev);
915 * only supervisor access
918 * enable individual RX masking
920 * set max mailbox number
922 reg_mcr = flexcan_read(®s->mcr);
923 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
924 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
925 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
928 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
929 reg_mcr &= ~FLEXCAN_MCR_FEN;
930 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
932 reg_mcr |= FLEXCAN_MCR_FEN |
933 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
935 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
936 flexcan_write(reg_mcr, ®s->mcr);
940 * disable timer sync feature
942 * disable auto busoff recovery
943 * transmit lowest buffer first
945 * enable tx and rx warning interrupt
946 * enable bus off interrupt
947 * (== FLEXCAN_CTRL_ERR_STATE)
949 reg_ctrl = flexcan_read(®s->ctrl);
950 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
951 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
952 FLEXCAN_CTRL_ERR_STATE;
954 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
955 * on most Flexcan cores, too. Otherwise we don't get
956 * any error warning or passive interrupts.
958 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
959 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
960 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
962 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
964 /* save for later use */
965 priv->reg_ctrl_default = reg_ctrl;
966 /* leave interrupts disabled for now */
967 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
968 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
969 flexcan_write(reg_ctrl, ®s->ctrl);
971 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
972 reg_ctrl2 = flexcan_read(®s->ctrl2);
973 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
974 flexcan_write(reg_ctrl2, ®s->ctrl2);
977 /* clear and invalidate all mailboxes first */
978 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
979 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
980 ®s->mb[i].can_ctrl);
983 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
984 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
985 flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
986 ®s->mb[i].can_ctrl);
989 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
990 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
991 &priv->tx_mb_reserved->can_ctrl);
993 /* mark TX mailbox as INACTIVE */
994 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
995 &priv->tx_mb->can_ctrl);
997 /* acceptance mask/acceptance code (accept everything) */
998 flexcan_write(0x0, ®s->rxgmask);
999 flexcan_write(0x0, ®s->rx14mask);
1000 flexcan_write(0x0, ®s->rx15mask);
1002 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1003 flexcan_write(0x0, ®s->rxfgmask);
1005 /* clear acceptance filters */
1006 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1007 flexcan_write(0, ®s->rximr[i]);
1009 /* On Vybrid, disable memory error detection interrupts
1011 * This also works around errata e5295 which generates
1012 * false positive memory errors and put the device in
1015 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1016 /* Follow the protocol as described in "Detection
1017 * and Correction of Memory Errors" to write to
1020 reg_ctrl2 = flexcan_read(®s->ctrl2);
1021 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1022 flexcan_write(reg_ctrl2, ®s->ctrl2);
1024 reg_mecr = flexcan_read(®s->mecr);
1025 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1026 flexcan_write(reg_mecr, ®s->mecr);
1027 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1028 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1029 FLEXCAN_MECR_FANCEI_MSK);
1030 flexcan_write(reg_mecr, ®s->mecr);
1033 err = flexcan_transceiver_enable(priv);
1035 goto out_chip_disable;
1037 /* synchronize with the can bus */
1038 err = flexcan_chip_unfreeze(priv);
1040 goto out_transceiver_disable;
1042 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1044 /* enable interrupts atomically */
1045 disable_irq(dev->irq);
1046 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
1047 flexcan_write(priv->reg_imask1_default, ®s->imask1);
1048 flexcan_write(priv->reg_imask2_default, ®s->imask2);
1049 enable_irq(dev->irq);
1051 /* print chip status */
1052 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1053 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
1057 out_transceiver_disable:
1058 flexcan_transceiver_disable(priv);
1060 flexcan_chip_disable(priv);
1064 /* __flexcan_chip_stop
1066 * this function is entered with clocks enabled
1068 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1070 struct flexcan_priv *priv = netdev_priv(dev);
1071 struct flexcan_regs __iomem *regs = priv->regs;
1074 /* freeze + disable module */
1075 err = flexcan_chip_freeze(priv);
1076 if (err && !disable_on_error)
1078 err = flexcan_chip_disable(priv);
1079 if (err && !disable_on_error)
1080 goto out_chip_unfreeze;
1082 /* Disable all interrupts */
1083 flexcan_write(0, ®s->imask2);
1084 flexcan_write(0, ®s->imask1);
1085 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1088 flexcan_transceiver_disable(priv);
1089 priv->can.state = CAN_STATE_STOPPED;
1094 flexcan_chip_unfreeze(priv);
1099 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1101 return __flexcan_chip_stop(dev, true);
1104 static inline int flexcan_chip_stop(struct net_device *dev)
1106 return __flexcan_chip_stop(dev, false);
1109 static int flexcan_open(struct net_device *dev)
1111 struct flexcan_priv *priv = netdev_priv(dev);
1114 err = clk_prepare_enable(priv->clk_ipg);
1118 err = clk_prepare_enable(priv->clk_per);
1120 goto out_disable_ipg;
1122 err = open_candev(dev);
1124 goto out_disable_per;
1126 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1130 /* start chip and queuing */
1131 err = flexcan_chip_start(dev);
1135 can_led_event(dev, CAN_LED_EVENT_OPEN);
1137 can_rx_offload_enable(&priv->offload);
1138 netif_start_queue(dev);
1143 free_irq(dev->irq, dev);
1147 clk_disable_unprepare(priv->clk_per);
1149 clk_disable_unprepare(priv->clk_ipg);
1154 static int flexcan_close(struct net_device *dev)
1156 struct flexcan_priv *priv = netdev_priv(dev);
1158 netif_stop_queue(dev);
1159 can_rx_offload_disable(&priv->offload);
1160 flexcan_chip_stop_disable_on_error(dev);
1162 free_irq(dev->irq, dev);
1163 clk_disable_unprepare(priv->clk_per);
1164 clk_disable_unprepare(priv->clk_ipg);
1168 can_led_event(dev, CAN_LED_EVENT_STOP);
1173 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1178 case CAN_MODE_START:
1179 err = flexcan_chip_start(dev);
1183 netif_wake_queue(dev);
1193 static const struct net_device_ops flexcan_netdev_ops = {
1194 .ndo_open = flexcan_open,
1195 .ndo_stop = flexcan_close,
1196 .ndo_start_xmit = flexcan_start_xmit,
1197 .ndo_change_mtu = can_change_mtu,
1200 static int register_flexcandev(struct net_device *dev)
1202 struct flexcan_priv *priv = netdev_priv(dev);
1203 struct flexcan_regs __iomem *regs = priv->regs;
1206 err = clk_prepare_enable(priv->clk_ipg);
1210 err = clk_prepare_enable(priv->clk_per);
1212 goto out_disable_ipg;
1214 /* select "bus clock", chip must be disabled */
1215 err = flexcan_chip_disable(priv);
1217 goto out_disable_per;
1218 reg = flexcan_read(®s->ctrl);
1219 reg |= FLEXCAN_CTRL_CLK_SRC;
1220 flexcan_write(reg, ®s->ctrl);
1222 err = flexcan_chip_enable(priv);
1224 goto out_chip_disable;
1226 /* set freeze, halt */
1227 err = flexcan_chip_freeze(priv);
1229 goto out_chip_disable;
1231 /* activate FIFO, restrict register access */
1232 reg = flexcan_read(®s->mcr);
1233 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1234 flexcan_write(reg, ®s->mcr);
1236 /* Currently we only support newer versions of this core
1237 * featuring a RX hardware FIFO (although this driver doesn't
1238 * make use of it on some cores). Older cores, found on some
1239 * Coldfire derivates are not tested.
1241 reg = flexcan_read(®s->mcr);
1242 if (!(reg & FLEXCAN_MCR_FEN)) {
1243 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1245 goto out_chip_disable;
1248 err = register_candev(dev);
1250 /* disable core and turn off clocks */
1252 flexcan_chip_disable(priv);
1254 clk_disable_unprepare(priv->clk_per);
1256 clk_disable_unprepare(priv->clk_ipg);
1261 static void unregister_flexcandev(struct net_device *dev)
1263 unregister_candev(dev);
1266 static const struct of_device_id flexcan_of_match[] = {
1267 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1268 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1269 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1270 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1273 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1275 static const struct platform_device_id flexcan_id_table[] = {
1276 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1279 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1281 static int flexcan_probe(struct platform_device *pdev)
1283 const struct of_device_id *of_id;
1284 const struct flexcan_devtype_data *devtype_data;
1285 struct net_device *dev;
1286 struct flexcan_priv *priv;
1287 struct regulator *reg_xceiver;
1288 struct resource *mem;
1289 struct clk *clk_ipg = NULL, *clk_per = NULL;
1290 struct flexcan_regs __iomem *regs;
1294 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1295 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1296 return -EPROBE_DEFER;
1297 else if (IS_ERR(reg_xceiver))
1300 if (pdev->dev.of_node)
1301 of_property_read_u32(pdev->dev.of_node,
1302 "clock-frequency", &clock_freq);
1305 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1306 if (IS_ERR(clk_ipg)) {
1307 dev_err(&pdev->dev, "no ipg clock defined\n");
1308 return PTR_ERR(clk_ipg);
1311 clk_per = devm_clk_get(&pdev->dev, "per");
1312 if (IS_ERR(clk_per)) {
1313 dev_err(&pdev->dev, "no per clock defined\n");
1314 return PTR_ERR(clk_per);
1316 clock_freq = clk_get_rate(clk_per);
1319 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1320 irq = platform_get_irq(pdev, 0);
1324 regs = devm_ioremap_resource(&pdev->dev, mem);
1326 return PTR_ERR(regs);
1328 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1330 devtype_data = of_id->data;
1331 } else if (platform_get_device_id(pdev)->driver_data) {
1332 devtype_data = (struct flexcan_devtype_data *)
1333 platform_get_device_id(pdev)->driver_data;
1338 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1342 platform_set_drvdata(pdev, dev);
1343 SET_NETDEV_DEV(dev, &pdev->dev);
1345 dev->netdev_ops = &flexcan_netdev_ops;
1347 dev->flags |= IFF_ECHO;
1349 priv = netdev_priv(dev);
1350 priv->can.clock.freq = clock_freq;
1351 priv->can.bittiming_const = &flexcan_bittiming_const;
1352 priv->can.do_set_mode = flexcan_set_mode;
1353 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1354 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1355 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1356 CAN_CTRLMODE_BERR_REPORTING;
1358 priv->clk_ipg = clk_ipg;
1359 priv->clk_per = clk_per;
1360 priv->devtype_data = devtype_data;
1361 priv->reg_xceiver = reg_xceiver;
1363 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1364 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1365 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1367 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1368 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1370 priv->tx_mb = ®s->mb[priv->tx_mb_idx];
1372 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1373 priv->reg_imask2_default = 0;
1375 priv->offload.mailbox_read = flexcan_mailbox_read;
1377 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1380 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1381 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1383 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1384 priv->reg_imask1_default |= imask;
1385 priv->reg_imask2_default |= imask >> 32;
1387 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1389 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1390 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1391 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1394 goto failed_offload;
1396 err = register_flexcandev(dev);
1398 dev_err(&pdev->dev, "registering netdev failed\n");
1399 goto failed_register;
1402 devm_can_led_init(dev);
1404 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1405 priv->regs, dev->irq);
1415 static int flexcan_remove(struct platform_device *pdev)
1417 struct net_device *dev = platform_get_drvdata(pdev);
1418 struct flexcan_priv *priv = netdev_priv(dev);
1420 unregister_flexcandev(dev);
1421 can_rx_offload_del(&priv->offload);
1427 static int __maybe_unused flexcan_suspend(struct device *device)
1429 struct net_device *dev = dev_get_drvdata(device);
1430 struct flexcan_priv *priv = netdev_priv(dev);
1433 if (netif_running(dev)) {
1434 err = flexcan_chip_disable(priv);
1437 netif_stop_queue(dev);
1438 netif_device_detach(dev);
1440 priv->can.state = CAN_STATE_SLEEPING;
1445 static int __maybe_unused flexcan_resume(struct device *device)
1447 struct net_device *dev = dev_get_drvdata(device);
1448 struct flexcan_priv *priv = netdev_priv(dev);
1451 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1452 if (netif_running(dev)) {
1453 netif_device_attach(dev);
1454 netif_start_queue(dev);
1455 err = flexcan_chip_enable(priv);
1462 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1464 static struct platform_driver flexcan_driver = {
1467 .pm = &flexcan_pm_ops,
1468 .of_match_table = flexcan_of_match,
1470 .probe = flexcan_probe,
1471 .remove = flexcan_remove,
1472 .id_table = flexcan_id_table,
1475 module_platform_driver(flexcan_driver);
1477 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1478 "Marc Kleine-Budde <kernel@pengutronix.de>");
1479 MODULE_LICENSE("GPL v2");
1480 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");