drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <dt-bindings/firmware/imx/rsrc.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/can.h>
  15 #include <linux/can/dev.h>
  16 #include <linux/can/error.h>
  17 #include <linux/can/led.h>
  18 #include <linux/can/rx-offload.h>
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/firmware/imx/sci.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pinctrl/consumer.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/can/platform/flexcan.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/regmap.h>
  34 #include <linux/regulator/consumer.h>
  35
  36 #define DRV_NAME                        "flexcan"
  37
  38 /* 8 for RX fifo and 2 error handling */
  39 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  40
  41 /* FLEXCAN module configuration register (CANMCR) bits */
  42 #define FLEXCAN_MCR_MDIS                BIT(31)
  43 #define FLEXCAN_MCR_FRZ                 BIT(30)
  44 #define FLEXCAN_MCR_FEN                 BIT(29)
  45 #define FLEXCAN_MCR_HALT                BIT(28)
  46 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  47 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  48 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  49 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  50 #define FLEXCAN_MCR_SUPV                BIT(23)
  51 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  52 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  53 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  54 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  55 #define FLEXCAN_MCR_DOZE                BIT(18)
  56 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  57 #define FLEXCAN_MCR_IRMQ                BIT(16)
  58 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  59 #define FLEXCAN_MCR_AEN                 BIT(12)
  60 #define FLEXCAN_MCR_FDEN                BIT(11)
  61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  62 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  63 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  64 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  65 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  66 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  67
  68 /* FLEXCAN control register (CANCTRL) bits */
  69 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  70 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  71 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  72 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  73 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  74 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  75 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  76 #define FLEXCAN_CTRL_LPB                BIT(12)
  77 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  78 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  79 #define FLEXCAN_CTRL_SMP                BIT(7)
  80 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  81 #define FLEXCAN_CTRL_TSYN               BIT(5)
  82 #define FLEXCAN_CTRL_LBUF               BIT(4)
  83 #define FLEXCAN_CTRL_LOM                BIT(3)
  84 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  85 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  86 #define FLEXCAN_CTRL_ERR_STATE \
  87         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  88          FLEXCAN_CTRL_BOFF_MSK)
  89 #define FLEXCAN_CTRL_ERR_ALL \
  90         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  91
  92 /* FLEXCAN control register 2 (CTRL2) bits */
  93 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  94 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  95 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  96 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  97 #define FLEXCAN_CTRL2_MRP               BIT(18)
  98 #define FLEXCAN_CTRL2_RRS               BIT(17)
  99 #define FLEXCAN_CTRL2_EACEN             BIT(16)
 100 #define FLEXCAN_CTRL2_ISOCANFDEN        BIT(12)
 101
 102 /* FLEXCAN memory error control register (MECR) bits */
 103 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
 104 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
 105 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
 106 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 107 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 108 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 109 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 110 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 111 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 112 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 113
 114 /* FLEXCAN error and status register (ESR) bits */
 115 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 116 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 117 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 118 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 119 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 120 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 121 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 122 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 123 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 124 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 125 #define FLEXCAN_ESR_IDLE                BIT(7)
 126 #define FLEXCAN_ESR_TXRX                BIT(6)
 127 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 128 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 131 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 132 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 133 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 134 #define FLEXCAN_ESR_ERR_BUS \
 135         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 136          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 137          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 138 #define FLEXCAN_ESR_ERR_STATE \
 139         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 140 #define FLEXCAN_ESR_ERR_ALL \
 141         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 142 #define FLEXCAN_ESR_ALL_INT \
 143         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 144          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 145
 146 /* FLEXCAN Bit Timing register (CBT) bits */
 147 #define FLEXCAN_CBT_BTF                 BIT(31)
 148 #define FLEXCAN_CBT_EPRESDIV_MASK       GENMASK(30, 21)
 149 #define FLEXCAN_CBT_ERJW_MASK           GENMASK(20, 16)
 150 #define FLEXCAN_CBT_EPROPSEG_MASK       GENMASK(15, 10)
 151 #define FLEXCAN_CBT_EPSEG1_MASK         GENMASK(9, 5)
 152 #define FLEXCAN_CBT_EPSEG2_MASK         GENMASK(4, 0)
 153
 154 /* FLEXCAN FD control register (FDCTRL) bits */
 155 #define FLEXCAN_FDCTRL_FDRATE           BIT(31)
 156 #define FLEXCAN_FDCTRL_MBDSR1           GENMASK(20, 19)
 157 #define FLEXCAN_FDCTRL_MBDSR0           GENMASK(17, 16)
 158 #define FLEXCAN_FDCTRL_MBDSR_8          0x0
 159 #define FLEXCAN_FDCTRL_MBDSR_12         0x1
 160 #define FLEXCAN_FDCTRL_MBDSR_32         0x2
 161 #define FLEXCAN_FDCTRL_MBDSR_64         0x3
 162 #define FLEXCAN_FDCTRL_TDCEN            BIT(15)
 163 #define FLEXCAN_FDCTRL_TDCFAIL          BIT(14)
 164 #define FLEXCAN_FDCTRL_TDCOFF           GENMASK(12, 8)
 165 #define FLEXCAN_FDCTRL_TDCVAL           GENMASK(5, 0)
 166
 167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
 168 #define FLEXCAN_FDCBT_FPRESDIV_MASK     GENMASK(29, 20)
 169 #define FLEXCAN_FDCBT_FRJW_MASK         GENMASK(18, 16)
 170 #define FLEXCAN_FDCBT_FPROPSEG_MASK     GENMASK(14, 10)
 171 #define FLEXCAN_FDCBT_FPSEG1_MASK       GENMASK(7, 5)
 172 #define FLEXCAN_FDCBT_FPSEG2_MASK       GENMASK(2, 0)
 173
 174 /* FLEXCAN interrupt flag register (IFLAG) bits */
 175 /* Errata ERR005829 step7: Reserve first valid MB */
 176 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO  8
 177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX       0
 178 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST  (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
 179 #define FLEXCAN_IFLAG_MB(x)             BIT_ULL(x)
 180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 181 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 183
 184 /* FLEXCAN message buffers */
 185 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 187 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 188 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 189 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 190 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 191 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 192
 193 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 194 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 195 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 196 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 197
 198 #define FLEXCAN_MB_CNT_EDL              BIT(31)
 199 #define FLEXCAN_MB_CNT_BRS              BIT(30)
 200 #define FLEXCAN_MB_CNT_ESI              BIT(29)
 201 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 202 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 203 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 204 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 205 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 206
 207 #define FLEXCAN_TIMEOUT_US              (250)
 208
 209 /* FLEXCAN hardware feature flags
 210  *
 211  * Below is some version info we got:
 212  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
 213  *                                Filter? connected?  Passive detection  ption in MB Supported?
 214  * MCF5441X FlexCAN2  ?               no       yes        no       no       yes           no     16
 215  *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
 216  *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
 217  *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
 218  *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
 219  *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
 220  *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
 221  *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
 222  *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
 223  *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
 224  *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
 225  *
 226  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 227  */
 228
 229 /* [TR]WRN_INT not connected */
 230 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
 231  /* Disable RX FIFO Global mask */
 232 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
 233 /* Enable EACEN and RRS bit in ctrl2 */
 234 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3)
 235 /* Disable non-correctable errors interrupt and freeze mode */
 236 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
 237 /* Use mailboxes (not FIFO) for RX path */
 238 #define FLEXCAN_QUIRK_USE_RX_MAILBOX BIT(5)
 239 /* No interrupt for error passive */
 240 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
 241 /* default to BE register access */
 242 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
 243 /* Setup stop mode with GPR to support wakeup */
 244 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
 245 /* Support CAN-FD mode */
 246 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
 247 /* support memory detection and correction */
 248 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
 249 /* Setup stop mode with SCU firmware to support wakeup */
 250 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
 251 /* Setup 3 separate interrupts, main, boff and err */
 252 #define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
 253 /* Setup 16 mailboxes */
 254 #define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
 255 /* Device supports RX via mailboxes */
 256 #define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX BIT(14)
 257 /* Device supports RTR reception via mailboxes */
 258 #define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR BIT(15)
 259 /* Device supports RX via FIFO */
 260 #define FLEXCAN_QUIRK_SUPPPORT_RX_FIFO BIT(16)
 261
 262 /* Structure of the message buffer */
 263 struct flexcan_mb {
 264         u32 can_ctrl;
 265         u32 can_id;
 266         u32 data[];
 267 };
 268
 269 /* Structure of the hardware registers */
 270 struct flexcan_regs {
 271         u32 mcr;                /* 0x00 */
 272         u32 ctrl;               /* 0x04 - Not affected by Soft Reset */
 273         u32 timer;              /* 0x08 */
 274         u32 tcr;                /* 0x0c */
 275         u32 rxgmask;            /* 0x10 - Not affected by Soft Reset */
 276         u32 rx14mask;           /* 0x14 - Not affected by Soft Reset */
 277         u32 rx15mask;           /* 0x18 - Not affected by Soft Reset */
 278         u32 ecr;                /* 0x1c */
 279         u32 esr;                /* 0x20 */
 280         u32 imask2;             /* 0x24 */
 281         u32 imask1;             /* 0x28 */
 282         u32 iflag2;             /* 0x2c */
 283         u32 iflag1;             /* 0x30 */
 284         union {                 /* 0x34 */
 285                 u32 gfwr_mx28;  /* MX28, MX53 */
 286                 u32 ctrl2;      /* MX6, VF610 - Not affected by Soft Reset */
 287         };
 288         u32 esr2;               /* 0x38 */
 289         u32 imeur;              /* 0x3c */
 290         u32 lrfr;               /* 0x40 */
 291         u32 crcr;               /* 0x44 */
 292         u32 rxfgmask;           /* 0x48 */
 293         u32 rxfir;              /* 0x4c - Not affected by Soft Reset */
 294         u32 cbt;                /* 0x50 - Not affected by Soft Reset */
 295         u32 _reserved2;         /* 0x54 */
 296         u32 dbg1;               /* 0x58 */
 297         u32 dbg2;               /* 0x5c */
 298         u32 _reserved3[8];      /* 0x60 */
 299         u8 mb[2][512];          /* 0x80 - Not affected by Soft Reset */
 300         /* FIFO-mode:
 301          *                      MB
 302          * 0x080...0x08f        0       RX message buffer
 303          * 0x090...0x0df        1-5     reserved
 304          * 0x0e0...0x0ff        6-7     8 entry ID table
 305          *                              (mx25, mx28, mx35, mx53)
 306          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 307          *                              size conf'ed via ctrl2::RFFN
 308          *                              (mx6, vf610)
 309          */
 310         u32 _reserved4[256];    /* 0x480 */
 311         u32 rximr[64];          /* 0x880 - Not affected by Soft Reset */
 312         u32 _reserved5[24];     /* 0x980 */
 313         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 314         u32 _reserved6[39];     /* 0x9e4 */
 315         u32 _rxfir[6];          /* 0xa80 */
 316         u32 _reserved8[2];      /* 0xa98 */
 317         u32 _rxmgmask;          /* 0xaa0 */
 318         u32 _rxfgmask;          /* 0xaa4 */
 319         u32 _rx14mask;          /* 0xaa8 */
 320         u32 _rx15mask;          /* 0xaac */
 321         u32 tx_smb[4];          /* 0xab0 */
 322         u32 rx_smb0[4];         /* 0xac0 */
 323         u32 rx_smb1[4];         /* 0xad0 */
 324         u32 mecr;               /* 0xae0 */
 325         u32 erriar;             /* 0xae4 */
 326         u32 erridpr;            /* 0xae8 */
 327         u32 errippr;            /* 0xaec */
 328         u32 rerrar;             /* 0xaf0 */
 329         u32 rerrdr;             /* 0xaf4 */
 330         u32 rerrsynr;           /* 0xaf8 */
 331         u32 errsr;              /* 0xafc */
 332         u32 _reserved7[64];     /* 0xb00 */
 333         u32 fdctrl;             /* 0xc00 - Not affected by Soft Reset */
 334         u32 fdcbt;              /* 0xc04 - Not affected by Soft Reset */
 335         u32 fdcrc;              /* 0xc08 */
 336         u32 _reserved9[199];    /* 0xc0c */
 337         u32 tx_smb_fd[18];      /* 0xf28 */
 338         u32 rx_smb0_fd[18];     /* 0xf70 */
 339         u32 rx_smb1_fd[18];     /* 0xfb8 */
 340 };
 341
 342 static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
 343
 344 struct flexcan_devtype_data {
 345         u32 quirks;             /* quirks needed for different IP cores */
 346 };
 347
 348 struct flexcan_stop_mode {
 349         struct regmap *gpr;
 350         u8 req_gpr;
 351         u8 req_bit;
 352 };
 353
 354 struct flexcan_priv {
 355         struct can_priv can;
 356         struct can_rx_offload offload;
 357         struct device *dev;
 358
 359         struct flexcan_regs __iomem *regs;
 360         struct flexcan_mb __iomem *tx_mb;
 361         struct flexcan_mb __iomem *tx_mb_reserved;
 362         u8 tx_mb_idx;
 363         u8 mb_count;
 364         u8 mb_size;
 365         u8 clk_src;     /* clock source of CAN Protocol Engine */
 366         u8 scu_idx;
 367
 368         u64 rx_mask;
 369         u64 tx_mask;
 370         u32 reg_ctrl_default;
 371
 372         struct clk *clk_ipg;
 373         struct clk *clk_per;
 374         struct flexcan_devtype_data devtype_data;
 375         struct regulator *reg_xceiver;
 376         struct flexcan_stop_mode stm;
 377
 378         int irq_boff;
 379         int irq_err;
 380
 381         /* IPC handle when setup stop mode by System Controller firmware(scfw) */
 382         struct imx_sc_ipc *sc_ipc_handle;
 383
 384         /* Read and Write APIs */
 385         u32 (*read)(void __iomem *addr);
 386         void (*write)(u32 val, void __iomem *addr);
 387 };
 388
 389 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
 390         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 391                 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
 392                 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 393 };
 394
 395 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 396         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 397                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 398                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
 399                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 400                 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 401 };
 402
 403 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 404         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 405                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 406                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 407                 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 408 };
 409
 410 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 411         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 412                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 413                 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 414 };
 415
 416 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 417         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 418                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 419                 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 420                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 421                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 422 };
 423
 424 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
 425         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 426                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 427                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
 428                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 429                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 430 };
 431
 432 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
 433         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 434                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 435                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 436                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
 437                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 438                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 439 };
 440
 441 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 442         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 443                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 444                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
 445                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 446                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 447 };
 448
 449 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 450         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 451                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
 452                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 453                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 454 };
 455
 456 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 457         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 458                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 459                 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
 460                 FLEXCAN_QUIRK_SUPPORT_ECC |
 461                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
 462                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 463 };
 464
 465 static const struct can_bittiming_const flexcan_bittiming_const = {
 466         .name = DRV_NAME,
 467         .tseg1_min = 4,
 468         .tseg1_max = 16,
 469         .tseg2_min = 2,
 470         .tseg2_max = 8,
 471         .sjw_max = 4,
 472         .brp_min = 1,
 473         .brp_max = 256,
 474         .brp_inc = 1,
 475 };
 476
 477 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
 478         .name = DRV_NAME,
 479         .tseg1_min = 2,
 480         .tseg1_max = 96,
 481         .tseg2_min = 2,
 482         .tseg2_max = 32,
 483         .sjw_max = 16,
 484         .brp_min = 1,
 485         .brp_max = 1024,
 486         .brp_inc = 1,
 487 };
 488
 489 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
 490         .name = DRV_NAME,
 491         .tseg1_min = 2,
 492         .tseg1_max = 39,
 493         .tseg2_min = 2,
 494         .tseg2_max = 8,
 495         .sjw_max = 4,
 496         .brp_min = 1,
 497         .brp_max = 1024,
 498         .brp_inc = 1,
 499 };
 500
 501 /* FlexCAN module is essentially modelled as a little-endian IP in most
 502  * SoCs, i.e the registers as well as the message buffer areas are
 503  * implemented in a little-endian fashion.
 504  *
 505  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 506  * module in a big-endian fashion (i.e the registers as well as the
 507  * message buffer areas are implemented in a big-endian way).
 508  *
 509  * In addition, the FlexCAN module can be found on SoCs having ARM or
 510  * PPC cores. So, we need to abstract off the register read/write
 511  * functions, ensuring that these cater to all the combinations of module
 512  * endianness and underlying CPU endianness.
 513  */
 514 static inline u32 flexcan_read_be(void __iomem *addr)
 515 {
 516         return ioread32be(addr);
 517 }
 518
 519 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 520 {
 521         iowrite32be(val, addr);
 522 }
 523
 524 static inline u32 flexcan_read_le(void __iomem *addr)
 525 {
 526         return ioread32(addr);
 527 }
 528
 529 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 530 {
 531         iowrite32(val, addr);
 532 }
 533
 534 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 535                                                  u8 mb_index)
 536 {
 537         u8 bank_size;
 538         bool bank;
 539
 540         if (WARN_ON(mb_index >= priv->mb_count))
 541                 return NULL;
 542
 543         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 544
 545         bank = mb_index >= bank_size;
 546         if (bank)
 547                 mb_index -= bank_size;
 548
 549         return (struct flexcan_mb __iomem *)
 550                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 551 }
 552
 553 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 554 {
 555         struct flexcan_regs __iomem *regs = priv->regs;
 556         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 557
 558         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 559                 udelay(10);
 560
 561         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 562                 return -ETIMEDOUT;
 563
 564         return 0;
 565 }
 566
 567 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 568 {
 569         struct flexcan_regs __iomem *regs = priv->regs;
 570         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 571
 572         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 573                 udelay(10);
 574
 575         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 576                 return -ETIMEDOUT;
 577
 578         return 0;
 579 }
 580
 581 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 582 {
 583         struct flexcan_regs __iomem *regs = priv->regs;
 584         u32 reg_mcr;
 585
 586         reg_mcr = priv->read(&regs->mcr);
 587
 588         if (enable)
 589                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 590         else
 591                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 592
 593         priv->write(reg_mcr, &regs->mcr);
 594 }
 595
 596 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
 597 {
 598         u8 idx = priv->scu_idx;
 599         u32 rsrc_id, val;
 600
 601         rsrc_id = IMX_SC_R_CAN(idx);
 602
 603         if (enabled)
 604                 val = 1;
 605         else
 606                 val = 0;
 607
 608         /* stop mode request via scu firmware */
 609         return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
 610                                        IMX_SC_C_IPG_STOP, val);
 611 }
 612
 613 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 614 {
 615         struct flexcan_regs __iomem *regs = priv->regs;
 616         u32 reg_mcr;
 617         int ret;
 618
 619         reg_mcr = priv->read(&regs->mcr);
 620         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 621         priv->write(reg_mcr, &regs->mcr);
 622
 623         /* enable stop request */
 624         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 625                 ret = flexcan_stop_mode_enable_scfw(priv, true);
 626                 if (ret < 0)
 627                         return ret;
 628         } else {
 629                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 630                                    1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 631         }
 632
 633         return flexcan_low_power_enter_ack(priv);
 634 }
 635
 636 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 637 {
 638         struct flexcan_regs __iomem *regs = priv->regs;
 639         u32 reg_mcr;
 640         int ret;
 641
 642         /* remove stop request */
 643         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 644                 ret = flexcan_stop_mode_enable_scfw(priv, false);
 645                 if (ret < 0)
 646                         return ret;
 647         } else {
 648                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 649                                    1 << priv->stm.req_bit, 0);
 650         }
 651
 652         reg_mcr = priv->read(&regs->mcr);
 653         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 654         priv->write(reg_mcr, &regs->mcr);
 655
 656         return flexcan_low_power_exit_ack(priv);
 657 }
 658
 659 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 660 {
 661         struct flexcan_regs __iomem *regs = priv->regs;
 662         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 663
 664         priv->write(reg_ctrl, &regs->ctrl);
 665 }
 666
 667 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 668 {
 669         struct flexcan_regs __iomem *regs = priv->regs;
 670         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 671
 672         priv->write(reg_ctrl, &regs->ctrl);
 673 }
 674
 675 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 676 {
 677         int err = 0;
 678
 679         if (priv->clk_ipg) {
 680                 err = clk_prepare_enable(priv->clk_ipg);
 681                 if (err)
 682                         return err;
 683         }
 684
 685         if (priv->clk_per) {
 686                 err = clk_prepare_enable(priv->clk_per);
 687                 if (err)
 688                         clk_disable_unprepare(priv->clk_ipg);
 689         }
 690
 691         return err;
 692 }
 693
 694 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 695 {
 696         clk_disable_unprepare(priv->clk_per);
 697         clk_disable_unprepare(priv->clk_ipg);
 698 }
 699
 700 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 701 {
 702         if (!priv->reg_xceiver)
 703                 return 0;
 704
 705         return regulator_enable(priv->reg_xceiver);
 706 }
 707
 708 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 709 {
 710         if (!priv->reg_xceiver)
 711                 return 0;
 712
 713         return regulator_disable(priv->reg_xceiver);
 714 }
 715
 716 static int flexcan_chip_enable(struct flexcan_priv *priv)
 717 {
 718         struct flexcan_regs __iomem *regs = priv->regs;
 719         u32 reg;
 720
 721         reg = priv->read(&regs->mcr);
 722         reg &= ~FLEXCAN_MCR_MDIS;
 723         priv->write(reg, &regs->mcr);
 724
 725         return flexcan_low_power_exit_ack(priv);
 726 }
 727
 728 static int flexcan_chip_disable(struct flexcan_priv *priv)
 729 {
 730         struct flexcan_regs __iomem *regs = priv->regs;
 731         u32 reg;
 732
 733         reg = priv->read(&regs->mcr);
 734         reg |= FLEXCAN_MCR_MDIS;
 735         priv->write(reg, &regs->mcr);
 736
 737         return flexcan_low_power_enter_ack(priv);
 738 }
 739
 740 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 741 {
 742         struct flexcan_regs __iomem *regs = priv->regs;
 743         unsigned int timeout;
 744         u32 bitrate = priv->can.bittiming.bitrate;
 745         u32 reg;
 746
 747         if (bitrate)
 748                 timeout = 1000 * 1000 * 10 / bitrate;
 749         else
 750                 timeout = FLEXCAN_TIMEOUT_US / 10;
 751
 752         reg = priv->read(&regs->mcr);
 753         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
 754         priv->write(reg, &regs->mcr);
 755
 756         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 757                 udelay(100);
 758
 759         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 760                 return -ETIMEDOUT;
 761
 762         return 0;
 763 }
 764
 765 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 766 {
 767         struct flexcan_regs __iomem *regs = priv->regs;
 768         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 769         u32 reg;
 770
 771         reg = priv->read(&regs->mcr);
 772         reg &= ~FLEXCAN_MCR_HALT;
 773         priv->write(reg, &regs->mcr);
 774
 775         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 776                 udelay(10);
 777
 778         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 779                 return -ETIMEDOUT;
 780
 781         return 0;
 782 }
 783
 784 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 785 {
 786         struct flexcan_regs __iomem *regs = priv->regs;
 787         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 788
 789         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 790         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 791                 udelay(10);
 792
 793         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 794                 return -ETIMEDOUT;
 795
 796         return 0;
 797 }
 798
 799 static int __flexcan_get_berr_counter(const struct net_device *dev,
 800                                       struct can_berr_counter *bec)
 801 {
 802         const struct flexcan_priv *priv = netdev_priv(dev);
 803         struct flexcan_regs __iomem *regs = priv->regs;
 804         u32 reg = priv->read(&regs->ecr);
 805
 806         bec->txerr = (reg >> 0) & 0xff;
 807         bec->rxerr = (reg >> 8) & 0xff;
 808
 809         return 0;
 810 }
 811
 812 static int flexcan_get_berr_counter(const struct net_device *dev,
 813                                     struct can_berr_counter *bec)
 814 {
 815         const struct flexcan_priv *priv = netdev_priv(dev);
 816         int err;
 817
 818         err = pm_runtime_get_sync(priv->dev);
 819         if (err < 0) {
 820                 pm_runtime_put_noidle(priv->dev);
 821                 return err;
 822         }
 823
 824         err = __flexcan_get_berr_counter(dev, bec);
 825
 826         pm_runtime_put(priv->dev);
 827
 828         return err;
 829 }
 830
 831 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 832 {
 833         const struct flexcan_priv *priv = netdev_priv(dev);
 834         struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
 835         u32 can_id;
 836         u32 data;
 837         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
 838         int i;
 839
 840         if (can_dropped_invalid_skb(dev, skb))
 841                 return NETDEV_TX_OK;
 842
 843         netif_stop_queue(dev);
 844
 845         if (cfd->can_id & CAN_EFF_FLAG) {
 846                 can_id = cfd->can_id & CAN_EFF_MASK;
 847                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 848         } else {
 849                 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
 850         }
 851
 852         if (cfd->can_id & CAN_RTR_FLAG)
 853                 ctrl |= FLEXCAN_MB_CNT_RTR;
 854
 855         if (can_is_canfd_skb(skb)) {
 856                 ctrl |= FLEXCAN_MB_CNT_EDL;
 857
 858                 if (cfd->flags & CANFD_BRS)
 859                         ctrl |= FLEXCAN_MB_CNT_BRS;
 860         }
 861
 862         for (i = 0; i < cfd->len; i += sizeof(u32)) {
 863                 data = be32_to_cpup((__be32 *)&cfd->data[i]);
 864                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 865         }
 866
 867         can_put_echo_skb(skb, dev, 0, 0);
 868
 869         priv->write(can_id, &priv->tx_mb->can_id);
 870         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 871
 872         /* Errata ERR005829 step8:
 873          * Write twice INACTIVE(0x8) code to first MB.
 874          */
 875         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 876                     &priv->tx_mb_reserved->can_ctrl);
 877         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 878                     &priv->tx_mb_reserved->can_ctrl);
 879
 880         return NETDEV_TX_OK;
 881 }
 882
 883 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 884 {
 885         struct flexcan_priv *priv = netdev_priv(dev);
 886         struct flexcan_regs __iomem *regs = priv->regs;
 887         struct sk_buff *skb;
 888         struct can_frame *cf;
 889         bool rx_errors = false, tx_errors = false;
 890         u32 timestamp;
 891         int err;
 892
 893         timestamp = priv->read(&regs->timer) << 16;
 894
 895         skb = alloc_can_err_skb(dev, &cf);
 896         if (unlikely(!skb))
 897                 return;
 898
 899         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 900
 901         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 902                 netdev_dbg(dev, "BIT1_ERR irq\n");
 903                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 904                 tx_errors = true;
 905         }
 906         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 907                 netdev_dbg(dev, "BIT0_ERR irq\n");
 908                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 909                 tx_errors = true;
 910         }
 911         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 912                 netdev_dbg(dev, "ACK_ERR irq\n");
 913                 cf->can_id |= CAN_ERR_ACK;
 914                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 915                 tx_errors = true;
 916         }
 917         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 918                 netdev_dbg(dev, "CRC_ERR irq\n");
 919                 cf->data[2] |= CAN_ERR_PROT_BIT;
 920                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 921                 rx_errors = true;
 922         }
 923         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 924                 netdev_dbg(dev, "FRM_ERR irq\n");
 925                 cf->data[2] |= CAN_ERR_PROT_FORM;
 926                 rx_errors = true;
 927         }
 928         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 929                 netdev_dbg(dev, "STF_ERR irq\n");
 930                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 931                 rx_errors = true;
 932         }
 933
 934         priv->can.can_stats.bus_error++;
 935         if (rx_errors)
 936                 dev->stats.rx_errors++;
 937         if (tx_errors)
 938                 dev->stats.tx_errors++;
 939
 940         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 941         if (err)
 942                 dev->stats.rx_fifo_errors++;
 943 }
 944
 945 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 946 {
 947         struct flexcan_priv *priv = netdev_priv(dev);
 948         struct flexcan_regs __iomem *regs = priv->regs;
 949         struct sk_buff *skb;
 950         struct can_frame *cf;
 951         enum can_state new_state, rx_state, tx_state;
 952         int flt;
 953         struct can_berr_counter bec;
 954         u32 timestamp;
 955         int err;
 956
 957         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 958         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 959                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 960                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 961                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 962                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 963                 new_state = max(tx_state, rx_state);
 964         } else {
 965                 __flexcan_get_berr_counter(dev, &bec);
 966                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 967                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 968                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 969                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 970         }
 971
 972         /* state hasn't changed */
 973         if (likely(new_state == priv->can.state))
 974                 return;
 975
 976         timestamp = priv->read(&regs->timer) << 16;
 977
 978         skb = alloc_can_err_skb(dev, &cf);
 979         if (unlikely(!skb))
 980                 return;
 981
 982         can_change_state(dev, cf, tx_state, rx_state);
 983
 984         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 985                 can_bus_off(dev);
 986
 987         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 988         if (err)
 989                 dev->stats.rx_fifo_errors++;
 990 }
 991
 992 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 993 {
 994         u64 reg = 0;
 995
 996         if (upper_32_bits(mask))
 997                 reg = (u64)priv->read(addr - 4) << 32;
 998         if (lower_32_bits(mask))
 999                 reg |= priv->read(addr);
1000
1001         return reg & mask;
1002 }
1003
1004 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
1005 {
1006         if (upper_32_bits(val))
1007                 priv->write(upper_32_bits(val), addr - 4);
1008         if (lower_32_bits(val))
1009                 priv->write(lower_32_bits(val), addr);
1010 }
1011
1012 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
1013 {
1014         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
1015 }
1016
1017 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
1018 {
1019         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
1020 }
1021
1022 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
1023 {
1024         return container_of(offload, struct flexcan_priv, offload);
1025 }
1026
1027 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
1028                                             unsigned int n, u32 *timestamp,
1029                                             bool drop)
1030 {
1031         struct flexcan_priv *priv = rx_offload_to_priv(offload);
1032         struct flexcan_regs __iomem *regs = priv->regs;
1033         struct flexcan_mb __iomem *mb;
1034         struct sk_buff *skb;
1035         struct canfd_frame *cfd;
1036         u32 reg_ctrl, reg_id, reg_iflag1;
1037         int i;
1038
1039         if (unlikely(drop)) {
1040                 skb = ERR_PTR(-ENOBUFS);
1041                 goto mark_as_read;
1042         }
1043
1044         mb = flexcan_get_mb(priv, n);
1045
1046         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1047                 u32 code;
1048
1049                 do {
1050                         reg_ctrl = priv->read(&mb->can_ctrl);
1051                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
1052
1053                 /* is this MB empty? */
1054                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
1055                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
1056                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
1057                         return NULL;
1058
1059                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
1060                         /* This MB was overrun, we lost data */
1061                         offload->dev->stats.rx_over_errors++;
1062                         offload->dev->stats.rx_errors++;
1063                 }
1064         } else {
1065                 reg_iflag1 = priv->read(&regs->iflag1);
1066                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
1067                         return NULL;
1068
1069                 reg_ctrl = priv->read(&mb->can_ctrl);
1070         }
1071
1072         if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1073                 skb = alloc_canfd_skb(offload->dev, &cfd);
1074         else
1075                 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1076         if (unlikely(!skb)) {
1077                 skb = ERR_PTR(-ENOMEM);
1078                 goto mark_as_read;
1079         }
1080
1081         /* increase timstamp to full 32 bit */
1082         *timestamp = reg_ctrl << 16;
1083
1084         reg_id = priv->read(&mb->can_id);
1085         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1086                 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1087         else
1088                 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1089
1090         if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1091                 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1092
1093                 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1094                         cfd->flags |= CANFD_BRS;
1095         } else {
1096                 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1097
1098                 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1099                         cfd->can_id |= CAN_RTR_FLAG;
1100         }
1101
1102         if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1103                 cfd->flags |= CANFD_ESI;
1104
1105         for (i = 0; i < cfd->len; i += sizeof(u32)) {
1106                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1107                 *(__be32 *)(cfd->data + i) = data;
1108         }
1109
1110  mark_as_read:
1111         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1112                 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1113         else
1114                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1115
1116         /* Read the Free Running Timer. It is optional but recommended
1117          * to unlock Mailbox as soon as possible and make it available
1118          * for reception.
1119          */
1120         priv->read(&regs->timer);
1121
1122         return skb;
1123 }
1124
1125 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1126 {
1127         struct net_device *dev = dev_id;
1128         struct net_device_stats *stats = &dev->stats;
1129         struct flexcan_priv *priv = netdev_priv(dev);
1130         struct flexcan_regs __iomem *regs = priv->regs;
1131         irqreturn_t handled = IRQ_NONE;
1132         u64 reg_iflag_tx;
1133         u32 reg_esr;
1134         enum can_state last_state = priv->can.state;
1135
1136         /* reception interrupt */
1137         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1138                 u64 reg_iflag_rx;
1139                 int ret;
1140
1141                 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1142                         handled = IRQ_HANDLED;
1143                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1144                                                                    reg_iflag_rx);
1145                         if (!ret)
1146                                 break;
1147                 }
1148         } else {
1149                 u32 reg_iflag1;
1150
1151                 reg_iflag1 = priv->read(&regs->iflag1);
1152                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1153                         handled = IRQ_HANDLED;
1154                         can_rx_offload_irq_offload_fifo(&priv->offload);
1155                 }
1156
1157                 /* FIFO overflow interrupt */
1158                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1159                         handled = IRQ_HANDLED;
1160                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1161                                     &regs->iflag1);
1162                         dev->stats.rx_over_errors++;
1163                         dev->stats.rx_errors++;
1164                 }
1165         }
1166
1167         reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1168
1169         /* transmission complete interrupt */
1170         if (reg_iflag_tx & priv->tx_mask) {
1171                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1172
1173                 handled = IRQ_HANDLED;
1174                 stats->tx_bytes +=
1175                         can_rx_offload_get_echo_skb(&priv->offload, 0,
1176                                                     reg_ctrl << 16, NULL);
1177                 stats->tx_packets++;
1178                 can_led_event(dev, CAN_LED_EVENT_TX);
1179
1180                 /* after sending a RTR frame MB is in RX mode */
1181                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1182                             &priv->tx_mb->can_ctrl);
1183                 flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1184                 netif_wake_queue(dev);
1185         }
1186
1187         reg_esr = priv->read(&regs->esr);
1188
1189         /* ACK all bus error, state change and wake IRQ sources */
1190         if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1191                 handled = IRQ_HANDLED;
1192                 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1193         }
1194
1195         /* state change interrupt or broken error state quirk fix is enabled */
1196         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1197             (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1198                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1199                 flexcan_irq_state(dev, reg_esr);
1200
1201         /* bus error IRQ - handle if bus error reporting is activated */
1202         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1203             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1204                 flexcan_irq_bus_err(dev, reg_esr);
1205
1206         /* availability of error interrupt among state transitions in case
1207          * bus error reporting is de-activated and
1208          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1209          *  +--------------------------------------------------------------+
1210          *  | +----------------------------------------------+ [stopped /  |
1211          *  | |                                              |  sleeping] -+
1212          *  +-+-> active <-> warning <-> passive -> bus off -+
1213          *        ___________^^^^^^^^^^^^_______________________________
1214          *        disabled(1)  enabled             disabled
1215          *
1216          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1217          */
1218         if ((last_state != priv->can.state) &&
1219             (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1220             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1221                 switch (priv->can.state) {
1222                 case CAN_STATE_ERROR_ACTIVE:
1223                         if (priv->devtype_data.quirks &
1224                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1225                                 flexcan_error_irq_enable(priv);
1226                         else
1227                                 flexcan_error_irq_disable(priv);
1228                         break;
1229
1230                 case CAN_STATE_ERROR_WARNING:
1231                         flexcan_error_irq_enable(priv);
1232                         break;
1233
1234                 case CAN_STATE_ERROR_PASSIVE:
1235                 case CAN_STATE_BUS_OFF:
1236                         flexcan_error_irq_disable(priv);
1237                         break;
1238
1239                 default:
1240                         break;
1241                 }
1242         }
1243
1244         if (handled)
1245                 can_rx_offload_irq_finish(&priv->offload);
1246
1247         return handled;
1248 }
1249
1250 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1251 {
1252         const struct flexcan_priv *priv = netdev_priv(dev);
1253         const struct can_bittiming *bt = &priv->can.bittiming;
1254         struct flexcan_regs __iomem *regs = priv->regs;
1255         u32 reg;
1256
1257         reg = priv->read(&regs->ctrl);
1258         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1259                  FLEXCAN_CTRL_RJW(0x3) |
1260                  FLEXCAN_CTRL_PSEG1(0x7) |
1261                  FLEXCAN_CTRL_PSEG2(0x7) |
1262                  FLEXCAN_CTRL_PROPSEG(0x7));
1263
1264         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1265                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1266                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1267                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1268                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1269
1270         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1271         priv->write(reg, &regs->ctrl);
1272
1273         /* print chip status */
1274         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1275                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1276 }
1277
1278 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1279 {
1280         struct flexcan_priv *priv = netdev_priv(dev);
1281         struct can_bittiming *bt = &priv->can.bittiming;
1282         struct can_bittiming *dbt = &priv->can.data_bittiming;
1283         struct flexcan_regs __iomem *regs = priv->regs;
1284         u32 reg_cbt, reg_fdctrl;
1285
1286         /* CBT */
1287         /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1288          * long. The can_calc_bittiming() tries to divide the tseg1
1289          * equally between phase_seg1 and prop_seg, which may not fit
1290          * in CBT register. Therefore, if phase_seg1 is more than
1291          * possible value, increase prop_seg and decrease phase_seg1.
1292          */
1293         if (bt->phase_seg1 > 0x20) {
1294                 bt->prop_seg += (bt->phase_seg1 - 0x20);
1295                 bt->phase_seg1 = 0x20;
1296         }
1297
1298         reg_cbt = FLEXCAN_CBT_BTF |
1299                 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1300                 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1301                 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1302                 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1303                 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1304
1305         netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1306         priv->write(reg_cbt, &regs->cbt);
1307
1308         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1309                 u32 reg_fdcbt, reg_ctrl2;
1310
1311                 if (bt->brp != dbt->brp)
1312                         netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1313                                     dbt->brp, bt->brp);
1314
1315                 /* FDCBT */
1316                 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1317                  * 5 bit long. The can_calc_bittiming tries to divide
1318                  * the tseg1 equally between phase_seg1 and prop_seg,
1319                  * which may not fit in FDCBT register. Therefore, if
1320                  * phase_seg1 is more than possible value, increase
1321                  * prop_seg and decrease phase_seg1
1322                  */
1323                 if (dbt->phase_seg1 > 0x8) {
1324                         dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1325                         dbt->phase_seg1 = 0x8;
1326                 }
1327
1328                 reg_fdcbt = priv->read(&regs->fdcbt);
1329                 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1330                                FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1331                                FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1332                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1333                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1334
1335                 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1336                         FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1337                         FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1338                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1339                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1340
1341                 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1342                 priv->write(reg_fdcbt, &regs->fdcbt);
1343
1344                 /* CTRL2 */
1345                 reg_ctrl2 = priv->read(&regs->ctrl2);
1346                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1347                 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1348                         reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1349
1350                 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1351                 priv->write(reg_ctrl2, &regs->ctrl2);
1352         }
1353
1354         /* FDCTRL */
1355         reg_fdctrl = priv->read(&regs->fdctrl);
1356         reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1357                         FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1358
1359         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1360                 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1361
1362                 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1363                         /* TDC must be disabled for Loop Back mode */
1364                         reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1365                 } else {
1366                         reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1367                                 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1368                                            ((dbt->phase_seg1 - 1) +
1369                                             dbt->prop_seg + 2) *
1370                                            ((dbt->brp - 1 ) + 1));
1371                 }
1372         }
1373
1374         netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1375         priv->write(reg_fdctrl, &regs->fdctrl);
1376
1377         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1378                    __func__,
1379                    priv->read(&regs->mcr), priv->read(&regs->ctrl),
1380                    priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1381                    priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1382 }
1383
1384 static void flexcan_set_bittiming(struct net_device *dev)
1385 {
1386         const struct flexcan_priv *priv = netdev_priv(dev);
1387         struct flexcan_regs __iomem *regs = priv->regs;
1388         u32 reg;
1389
1390         reg = priv->read(&regs->ctrl);
1391         reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1392                  FLEXCAN_CTRL_LOM);
1393
1394         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1395                 reg |= FLEXCAN_CTRL_LPB;
1396         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1397                 reg |= FLEXCAN_CTRL_LOM;
1398         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1399                 reg |= FLEXCAN_CTRL_SMP;
1400
1401         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1402         priv->write(reg, &regs->ctrl);
1403
1404         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1405                 return flexcan_set_bittiming_cbt(dev);
1406         else
1407                 return flexcan_set_bittiming_ctrl(dev);
1408 }
1409
1410 static void flexcan_ram_init(struct net_device *dev)
1411 {
1412         struct flexcan_priv *priv = netdev_priv(dev);
1413         struct flexcan_regs __iomem *regs = priv->regs;
1414         u32 reg_ctrl2;
1415
1416         /* 11.8.3.13 Detection and correction of memory errors:
1417          * CTRL2[WRMFRZ] grants write access to all memory positions
1418          * that require initialization, ranging from 0x080 to 0xADF
1419          * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1420          * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1421          * need to be initialized as well. MCR[RFEN] must not be set
1422          * during memory initialization.
1423          */
1424         reg_ctrl2 = priv->read(&regs->ctrl2);
1425         reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1426         priv->write(reg_ctrl2, &regs->ctrl2);
1427
1428         memset_io(&regs->mb[0][0], 0,
1429                   offsetof(struct flexcan_regs, rx_smb1[3]) -
1430                   offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1431
1432         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1433                 memset_io(&regs->tx_smb_fd[0], 0,
1434                           offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1435                           offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1436
1437         reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1438         priv->write(reg_ctrl2, &regs->ctrl2);
1439 }
1440
1441 static int flexcan_rx_offload_setup(struct net_device *dev)
1442 {
1443         struct flexcan_priv *priv = netdev_priv(dev);
1444         int err;
1445
1446         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1447                 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1448         else
1449                 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1450
1451         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1452                 priv->mb_count = 16;
1453         else
1454                 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1455                                  (sizeof(priv->regs->mb[1]) / priv->mb_size);
1456
1457         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1458                 priv->tx_mb_reserved =
1459                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1460         else
1461                 priv->tx_mb_reserved =
1462                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1463         priv->tx_mb_idx = priv->mb_count - 1;
1464         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1465         priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1466
1467         priv->offload.mailbox_read = flexcan_mailbox_read;
1468
1469         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1470                 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1471                 priv->offload.mb_last = priv->mb_count - 2;
1472
1473                 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1474                                             priv->offload.mb_first);
1475                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1476         } else {
1477                 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1478                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1479                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1480                                               FLEXCAN_NAPI_WEIGHT);
1481         }
1482
1483         return err;
1484 }
1485
1486 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1487 {
1488         const struct flexcan_priv *priv = netdev_priv(dev);
1489         struct flexcan_regs __iomem *regs = priv->regs;
1490         u64 reg_imask;
1491
1492         disable_irq(dev->irq);
1493         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1494         reg_imask = priv->rx_mask | priv->tx_mask;
1495         priv->write(upper_32_bits(reg_imask), &regs->imask2);
1496         priv->write(lower_32_bits(reg_imask), &regs->imask1);
1497         enable_irq(dev->irq);
1498 }
1499
1500 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1501 {
1502         const struct flexcan_priv *priv = netdev_priv(dev);
1503         struct flexcan_regs __iomem *regs = priv->regs;
1504
1505         priv->write(0, &regs->imask2);
1506         priv->write(0, &regs->imask1);
1507         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1508                     &regs->ctrl);
1509 }
1510
1511 /* flexcan_chip_start
1512  *
1513  * this functions is entered with clocks enabled
1514  *
1515  */
1516 static int flexcan_chip_start(struct net_device *dev)
1517 {
1518         struct flexcan_priv *priv = netdev_priv(dev);
1519         struct flexcan_regs __iomem *regs = priv->regs;
1520         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1521         int err, i;
1522         struct flexcan_mb __iomem *mb;
1523
1524         /* enable module */
1525         err = flexcan_chip_enable(priv);
1526         if (err)
1527                 return err;
1528
1529         /* soft reset */
1530         err = flexcan_chip_softreset(priv);
1531         if (err)
1532                 goto out_chip_disable;
1533
1534         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1535                 flexcan_ram_init(dev);
1536
1537         flexcan_set_bittiming(dev);
1538
1539         /* set freeze, halt */
1540         err = flexcan_chip_freeze(priv);
1541         if (err)
1542                 goto out_chip_disable;
1543
1544         /* MCR
1545          *
1546          * only supervisor access
1547          * enable warning int
1548          * enable individual RX masking
1549          * choose format C
1550          * set max mailbox number
1551          */
1552         reg_mcr = priv->read(&regs->mcr);
1553         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1554         reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1555                 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1556
1557         /* MCR
1558          *
1559          * FIFO:
1560          * - disable for mailbox mode
1561          * - enable for FIFO mode
1562          */
1563         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1564                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1565         else
1566                 reg_mcr |= FLEXCAN_MCR_FEN;
1567
1568         /* MCR
1569          *
1570          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1571          *       asserted because this will impede the self reception
1572          *       of a transmitted message. This is not documented in
1573          *       earlier versions of flexcan block guide.
1574          *
1575          * Self Reception:
1576          * - enable Self Reception for loopback mode
1577          *   (by clearing "Self Reception Disable" bit)
1578          * - disable for normal operation
1579          */
1580         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1581                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1582         else
1583                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1584
1585         /* MCR - CAN-FD */
1586         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1587                 reg_mcr |= FLEXCAN_MCR_FDEN;
1588         else
1589                 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1590
1591         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1592         priv->write(reg_mcr, &regs->mcr);
1593
1594         /* CTRL
1595          *
1596          * disable timer sync feature
1597          *
1598          * disable auto busoff recovery
1599          * transmit lowest buffer first
1600          *
1601          * enable tx and rx warning interrupt
1602          * enable bus off interrupt
1603          * (== FLEXCAN_CTRL_ERR_STATE)
1604          */
1605         reg_ctrl = priv->read(&regs->ctrl);
1606         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1607         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1608                 FLEXCAN_CTRL_ERR_STATE;
1609
1610         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1611          * on most Flexcan cores, too. Otherwise we don't get
1612          * any error warning or passive interrupts.
1613          */
1614         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1615             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1616                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1617         else
1618                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1619
1620         /* save for later use */
1621         priv->reg_ctrl_default = reg_ctrl;
1622         /* leave interrupts disabled for now */
1623         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1624         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1625         priv->write(reg_ctrl, &regs->ctrl);
1626
1627         if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1628                 reg_ctrl2 = priv->read(&regs->ctrl2);
1629                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1630                 priv->write(reg_ctrl2, &regs->ctrl2);
1631         }
1632
1633         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1634                 u32 reg_fdctrl;
1635
1636                 reg_fdctrl = priv->read(&regs->fdctrl);
1637                 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1638                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1639
1640                 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1641                         reg_fdctrl |=
1642                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1643                                            FLEXCAN_FDCTRL_MBDSR_64) |
1644                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1645                                            FLEXCAN_FDCTRL_MBDSR_64);
1646                 } else {
1647                         reg_fdctrl |=
1648                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1649                                            FLEXCAN_FDCTRL_MBDSR_8) |
1650                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1651                                            FLEXCAN_FDCTRL_MBDSR_8);
1652                 }
1653
1654                 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1655                            __func__, reg_fdctrl);
1656                 priv->write(reg_fdctrl, &regs->fdctrl);
1657         }
1658
1659         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1660                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1661                         mb = flexcan_get_mb(priv, i);
1662                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1663                                     &mb->can_ctrl);
1664                 }
1665         } else {
1666                 /* clear and invalidate unused mailboxes first */
1667                 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1668                         mb = flexcan_get_mb(priv, i);
1669                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1670                                     &mb->can_ctrl);
1671                 }
1672         }
1673
1674         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1675         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1676                     &priv->tx_mb_reserved->can_ctrl);
1677
1678         /* mark TX mailbox as INACTIVE */
1679         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1680                     &priv->tx_mb->can_ctrl);
1681
1682         /* acceptance mask/acceptance code (accept everything) */
1683         priv->write(0x0, &regs->rxgmask);
1684         priv->write(0x0, &regs->rx14mask);
1685         priv->write(0x0, &regs->rx15mask);
1686
1687         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1688                 priv->write(0x0, &regs->rxfgmask);
1689
1690         /* clear acceptance filters */
1691         for (i = 0; i < priv->mb_count; i++)
1692                 priv->write(0, &regs->rximr[i]);
1693
1694         /* On Vybrid, disable non-correctable errors interrupt and
1695          * freeze mode. It still can correct the correctable errors
1696          * when HW supports ECC.
1697          *
1698          * This also works around errata e5295 which generates false
1699          * positive memory errors and put the device in freeze mode.
1700          */
1701         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1702                 /* Follow the protocol as described in "Detection
1703                  * and Correction of Memory Errors" to write to
1704                  * MECR register (step 1 - 5)
1705                  *
1706                  * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1707                  * 2. set CTRL2[ECRWRE]
1708                  */
1709                 reg_ctrl2 = priv->read(&regs->ctrl2);
1710                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1711                 priv->write(reg_ctrl2, &regs->ctrl2);
1712
1713                 /* 3. clear MECR[ECRWRDIS] */
1714                 reg_mecr = priv->read(&regs->mecr);
1715                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1716                 priv->write(reg_mecr, &regs->mecr);
1717
1718                 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1719                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1720                               FLEXCAN_MECR_FANCEI_MSK);
1721                 priv->write(reg_mecr, &regs->mecr);
1722
1723                 /* 5. after configuration done, lock MECR by either
1724                  * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1725                  */
1726                 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1727                 priv->write(reg_mecr, &regs->mecr);
1728
1729                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1730                 priv->write(reg_ctrl2, &regs->ctrl2);
1731         }
1732
1733         /* synchronize with the can bus */
1734         err = flexcan_chip_unfreeze(priv);
1735         if (err)
1736                 goto out_chip_disable;
1737
1738         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1739
1740         /* print chip status */
1741         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1742                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1743
1744         return 0;
1745
1746  out_chip_disable:
1747         flexcan_chip_disable(priv);
1748         return err;
1749 }
1750
1751 /* __flexcan_chip_stop
1752  *
1753  * this function is entered with clocks enabled
1754  */
1755 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1756 {
1757         struct flexcan_priv *priv = netdev_priv(dev);
1758         int err;
1759
1760         /* freeze + disable module */
1761         err = flexcan_chip_freeze(priv);
1762         if (err && !disable_on_error)
1763                 return err;
1764         err = flexcan_chip_disable(priv);
1765         if (err && !disable_on_error)
1766                 goto out_chip_unfreeze;
1767
1768         priv->can.state = CAN_STATE_STOPPED;
1769
1770         return 0;
1771
1772  out_chip_unfreeze:
1773         flexcan_chip_unfreeze(priv);
1774
1775         return err;
1776 }
1777
1778 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1779 {
1780         return __flexcan_chip_stop(dev, true);
1781 }
1782
1783 static inline int flexcan_chip_stop(struct net_device *dev)
1784 {
1785         return __flexcan_chip_stop(dev, false);
1786 }
1787
1788 static int flexcan_open(struct net_device *dev)
1789 {
1790         struct flexcan_priv *priv = netdev_priv(dev);
1791         int err;
1792
1793         if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1794             (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1795                 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1796                 return -EINVAL;
1797         }
1798
1799         err = pm_runtime_get_sync(priv->dev);
1800         if (err < 0) {
1801                 pm_runtime_put_noidle(priv->dev);
1802                 return err;
1803         }
1804
1805         err = open_candev(dev);
1806         if (err)
1807                 goto out_runtime_put;
1808
1809         err = flexcan_transceiver_enable(priv);
1810         if (err)
1811                 goto out_close;
1812
1813         err = flexcan_rx_offload_setup(dev);
1814         if (err)
1815                 goto out_transceiver_disable;
1816
1817         err = flexcan_chip_start(dev);
1818         if (err)
1819                 goto out_can_rx_offload_del;
1820
1821         can_rx_offload_enable(&priv->offload);
1822
1823         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1824         if (err)
1825                 goto out_can_rx_offload_disable;
1826
1827         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1828                 err = request_irq(priv->irq_boff,
1829                                   flexcan_irq, IRQF_SHARED, dev->name, dev);
1830                 if (err)
1831                         goto out_free_irq;
1832
1833                 err = request_irq(priv->irq_err,
1834                                   flexcan_irq, IRQF_SHARED, dev->name, dev);
1835                 if (err)
1836                         goto out_free_irq_boff;
1837         }
1838
1839         flexcan_chip_interrupts_enable(dev);
1840
1841         can_led_event(dev, CAN_LED_EVENT_OPEN);
1842
1843         netif_start_queue(dev);
1844
1845         return 0;
1846
1847  out_free_irq_boff:
1848         free_irq(priv->irq_boff, dev);
1849  out_free_irq:
1850         free_irq(dev->irq, dev);
1851  out_can_rx_offload_disable:
1852         can_rx_offload_disable(&priv->offload);
1853         flexcan_chip_stop(dev);
1854  out_can_rx_offload_del:
1855         can_rx_offload_del(&priv->offload);
1856  out_transceiver_disable:
1857         flexcan_transceiver_disable(priv);
1858  out_close:
1859         close_candev(dev);
1860  out_runtime_put:
1861         pm_runtime_put(priv->dev);
1862
1863         return err;
1864 }
1865
1866 static int flexcan_close(struct net_device *dev)
1867 {
1868         struct flexcan_priv *priv = netdev_priv(dev);
1869
1870         netif_stop_queue(dev);
1871         flexcan_chip_interrupts_disable(dev);
1872
1873         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1874                 free_irq(priv->irq_err, dev);
1875                 free_irq(priv->irq_boff, dev);
1876         }
1877
1878         free_irq(dev->irq, dev);
1879         can_rx_offload_disable(&priv->offload);
1880         flexcan_chip_stop_disable_on_error(dev);
1881
1882         can_rx_offload_del(&priv->offload);
1883         flexcan_transceiver_disable(priv);
1884         close_candev(dev);
1885
1886         pm_runtime_put(priv->dev);
1887
1888         can_led_event(dev, CAN_LED_EVENT_STOP);
1889
1890         return 0;
1891 }
1892
1893 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1894 {
1895         int err;
1896
1897         switch (mode) {
1898         case CAN_MODE_START:
1899                 err = flexcan_chip_start(dev);
1900                 if (err)
1901                         return err;
1902
1903                 flexcan_chip_interrupts_enable(dev);
1904
1905                 netif_wake_queue(dev);
1906                 break;
1907
1908         default:
1909                 return -EOPNOTSUPP;
1910         }
1911
1912         return 0;
1913 }
1914
1915 static const struct net_device_ops flexcan_netdev_ops = {
1916         .ndo_open       = flexcan_open,
1917         .ndo_stop       = flexcan_close,
1918         .ndo_start_xmit = flexcan_start_xmit,
1919         .ndo_change_mtu = can_change_mtu,
1920 };
1921
1922 static int register_flexcandev(struct net_device *dev)
1923 {
1924         struct flexcan_priv *priv = netdev_priv(dev);
1925         struct flexcan_regs __iomem *regs = priv->regs;
1926         u32 reg, err;
1927
1928         err = flexcan_clks_enable(priv);
1929         if (err)
1930                 return err;
1931
1932         /* select "bus clock", chip must be disabled */
1933         err = flexcan_chip_disable(priv);
1934         if (err)
1935                 goto out_clks_disable;
1936
1937         reg = priv->read(&regs->ctrl);
1938         if (priv->clk_src)
1939                 reg |= FLEXCAN_CTRL_CLK_SRC;
1940         else
1941                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1942         priv->write(reg, &regs->ctrl);
1943
1944         err = flexcan_chip_enable(priv);
1945         if (err)
1946                 goto out_chip_disable;
1947
1948         /* set freeze, halt */
1949         err = flexcan_chip_freeze(priv);
1950         if (err)
1951                 goto out_chip_disable;
1952
1953         /* activate FIFO, restrict register access */
1954         reg = priv->read(&regs->mcr);
1955         reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1956         priv->write(reg, &regs->mcr);
1957
1958         /* Currently we only support newer versions of this core
1959          * featuring a RX hardware FIFO (although this driver doesn't
1960          * make use of it on some cores). Older cores, found on some
1961          * Coldfire derivates are not tested.
1962          */
1963         reg = priv->read(&regs->mcr);
1964         if (!(reg & FLEXCAN_MCR_FEN)) {
1965                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1966                 err = -ENODEV;
1967                 goto out_chip_disable;
1968         }
1969
1970         err = register_candev(dev);
1971         if (err)
1972                 goto out_chip_disable;
1973
1974         /* Disable core and let pm_runtime_put() disable the clocks.
1975          * If CONFIG_PM is not enabled, the clocks will stay powered.
1976          */
1977         flexcan_chip_disable(priv);
1978         pm_runtime_put(priv->dev);
1979
1980         return 0;
1981
1982  out_chip_disable:
1983         flexcan_chip_disable(priv);
1984  out_clks_disable:
1985         flexcan_clks_disable(priv);
1986         return err;
1987 }
1988
1989 static void unregister_flexcandev(struct net_device *dev)
1990 {
1991         unregister_candev(dev);
1992 }
1993
1994 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1995 {
1996         struct net_device *dev = platform_get_drvdata(pdev);
1997         struct device_node *np = pdev->dev.of_node;
1998         struct device_node *gpr_np;
1999         struct flexcan_priv *priv;
2000         phandle phandle;
2001         u32 out_val[3];
2002         int ret;
2003
2004         if (!np)
2005                 return -EINVAL;
2006
2007         /* stop mode property format is:
2008          * <&gpr req_gpr req_bit>.
2009          */
2010         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
2011                                          ARRAY_SIZE(out_val));
2012         if (ret) {
2013                 dev_dbg(&pdev->dev, "no stop-mode property\n");
2014                 return ret;
2015         }
2016         phandle = *out_val;
2017
2018         gpr_np = of_find_node_by_phandle(phandle);
2019         if (!gpr_np) {
2020                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
2021                 return -ENODEV;
2022         }
2023
2024         priv = netdev_priv(dev);
2025         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
2026         if (IS_ERR(priv->stm.gpr)) {
2027                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
2028                 ret = PTR_ERR(priv->stm.gpr);
2029                 goto out_put_node;
2030         }
2031
2032         priv->stm.req_gpr = out_val[1];
2033         priv->stm.req_bit = out_val[2];
2034
2035         dev_dbg(&pdev->dev,
2036                 "gpr %s req_gpr=0x02%x req_bit=%u\n",
2037                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
2038
2039         return 0;
2040
2041 out_put_node:
2042         of_node_put(gpr_np);
2043         return ret;
2044 }
2045
2046 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
2047 {
2048         struct net_device *dev = platform_get_drvdata(pdev);
2049         struct flexcan_priv *priv;
2050         u8 scu_idx;
2051         int ret;
2052
2053         ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
2054         if (ret < 0) {
2055                 dev_dbg(&pdev->dev, "failed to get scu index\n");
2056                 return ret;
2057         }
2058
2059         priv = netdev_priv(dev);
2060         priv->scu_idx = scu_idx;
2061
2062         /* this function could be deferred probe, return -EPROBE_DEFER */
2063         return imx_scu_get_handle(&priv->sc_ipc_handle);
2064 }
2065
2066 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
2067  *
2068  * Return: = 0 setup stop mode successfully or doesn't support this feature
2069  *         < 0 fail to setup stop mode (could be deferred probe)
2070  */
2071 static int flexcan_setup_stop_mode(struct platform_device *pdev)
2072 {
2073         struct net_device *dev = platform_get_drvdata(pdev);
2074         struct flexcan_priv *priv;
2075         int ret;
2076
2077         priv = netdev_priv(dev);
2078
2079         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
2080                 ret = flexcan_setup_stop_mode_scfw(pdev);
2081         else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
2082                 ret = flexcan_setup_stop_mode_gpr(pdev);
2083         else
2084                 /* return 0 directly if doesn't support stop mode feature */
2085                 return 0;
2086
2087         if (ret)
2088                 return ret;
2089
2090         device_set_wakeup_capable(&pdev->dev, true);
2091
2092         if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2093                 device_set_wakeup_enable(&pdev->dev, true);
2094
2095         return 0;
2096 }
2097
2098 static const struct of_device_id flexcan_of_match[] = {
2099         { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2100         { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2101         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2102         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2103         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2104         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2105         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2106         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2107         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2108         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2109         { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2110         { /* sentinel */ },
2111 };
2112 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2113
2114 static const struct platform_device_id flexcan_id_table[] = {
2115         {
2116                 .name = "flexcan-mcf5441x",
2117                 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2118         }, {
2119                 /* sentinel */
2120         },
2121 };
2122 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2123
2124 static int flexcan_probe(struct platform_device *pdev)
2125 {
2126         const struct of_device_id *of_id;
2127         const struct flexcan_devtype_data *devtype_data;
2128         struct net_device *dev;
2129         struct flexcan_priv *priv;
2130         struct regulator *reg_xceiver;
2131         struct clk *clk_ipg = NULL, *clk_per = NULL;
2132         struct flexcan_regs __iomem *regs;
2133         struct flexcan_platform_data *pdata;
2134         int err, irq;
2135         u8 clk_src = 1;
2136         u32 clock_freq = 0;
2137
2138         reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2139         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2140                 return -EPROBE_DEFER;
2141         else if (PTR_ERR(reg_xceiver) == -ENODEV)
2142                 reg_xceiver = NULL;
2143         else if (IS_ERR(reg_xceiver))
2144                 return PTR_ERR(reg_xceiver);
2145
2146         if (pdev->dev.of_node) {
2147                 of_property_read_u32(pdev->dev.of_node,
2148                                      "clock-frequency", &clock_freq);
2149                 of_property_read_u8(pdev->dev.of_node,
2150                                     "fsl,clk-source", &clk_src);
2151         } else {
2152                 pdata = dev_get_platdata(&pdev->dev);
2153                 if (pdata) {
2154                         clock_freq = pdata->clock_frequency;
2155                         clk_src = pdata->clk_src;
2156                 }
2157         }
2158
2159         if (!clock_freq) {
2160                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2161                 if (IS_ERR(clk_ipg)) {
2162                         dev_err(&pdev->dev, "no ipg clock defined\n");
2163                         return PTR_ERR(clk_ipg);
2164                 }
2165
2166                 clk_per = devm_clk_get(&pdev->dev, "per");
2167                 if (IS_ERR(clk_per)) {
2168                         dev_err(&pdev->dev, "no per clock defined\n");
2169                         return PTR_ERR(clk_per);
2170                 }
2171                 clock_freq = clk_get_rate(clk_per);
2172         }
2173
2174         irq = platform_get_irq(pdev, 0);
2175         if (irq <= 0)
2176                 return -ENODEV;
2177
2178         regs = devm_platform_ioremap_resource(pdev, 0);
2179         if (IS_ERR(regs))
2180                 return PTR_ERR(regs);
2181
2182         of_id = of_match_device(flexcan_of_match, &pdev->dev);
2183         if (of_id)
2184                 devtype_data = of_id->data;
2185         else if (platform_get_device_id(pdev)->driver_data)
2186                 devtype_data = (struct flexcan_devtype_data *)
2187                         platform_get_device_id(pdev)->driver_data;
2188         else
2189                 return -ENODEV;
2190
2191         if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2192             !((devtype_data->quirks &
2193                (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2194                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2195                 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR |
2196                 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO)) ==
2197               (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2198                FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2199                FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR))) {
2200                 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2201                 return -EINVAL;
2202         }
2203
2204         if ((devtype_data->quirks &
2205              (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2206               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
2207             FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR) {
2208                 dev_err(&pdev->dev,
2209                         "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2210                         devtype_data->quirks);
2211                 return -EINVAL;
2212         }
2213
2214         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2215         if (!dev)
2216                 return -ENOMEM;
2217
2218         platform_set_drvdata(pdev, dev);
2219         SET_NETDEV_DEV(dev, &pdev->dev);
2220
2221         dev->netdev_ops = &flexcan_netdev_ops;
2222         dev->irq = irq;
2223         dev->flags |= IFF_ECHO;
2224
2225         priv = netdev_priv(dev);
2226         priv->devtype_data = *devtype_data;
2227
2228         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2229             priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2230                 priv->read = flexcan_read_be;
2231                 priv->write = flexcan_write_be;
2232         } else {
2233                 priv->read = flexcan_read_le;
2234                 priv->write = flexcan_write_le;
2235         }
2236
2237         priv->dev = &pdev->dev;
2238         priv->can.clock.freq = clock_freq;
2239         priv->can.do_set_mode = flexcan_set_mode;
2240         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2241         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2242                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2243                 CAN_CTRLMODE_BERR_REPORTING;
2244         priv->regs = regs;
2245         priv->clk_ipg = clk_ipg;
2246         priv->clk_per = clk_per;
2247         priv->clk_src = clk_src;
2248         priv->reg_xceiver = reg_xceiver;
2249
2250         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2251                 priv->irq_boff = platform_get_irq(pdev, 1);
2252                 if (priv->irq_boff <= 0) {
2253                         err = -ENODEV;
2254                         goto failed_platform_get_irq;
2255                 }
2256                 priv->irq_err = platform_get_irq(pdev, 2);
2257                 if (priv->irq_err <= 0) {
2258                         err = -ENODEV;
2259                         goto failed_platform_get_irq;
2260                 }
2261         }
2262
2263         if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2264                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2265                         CAN_CTRLMODE_FD_NON_ISO;
2266                 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2267                 priv->can.data_bittiming_const =
2268                         &flexcan_fd_data_bittiming_const;
2269         } else {
2270                 priv->can.bittiming_const = &flexcan_bittiming_const;
2271         }
2272
2273         pm_runtime_get_noresume(&pdev->dev);
2274         pm_runtime_set_active(&pdev->dev);
2275         pm_runtime_enable(&pdev->dev);
2276
2277         err = register_flexcandev(dev);
2278         if (err) {
2279                 dev_err(&pdev->dev, "registering netdev failed\n");
2280                 goto failed_register;
2281         }
2282
2283         err = flexcan_setup_stop_mode(pdev);
2284         if (err < 0) {
2285                 if (err != -EPROBE_DEFER)
2286                         dev_err(&pdev->dev, "setup stop mode failed\n");
2287                 goto failed_setup_stop_mode;
2288         }
2289
2290         of_can_transceiver(dev);
2291         devm_can_led_init(dev);
2292
2293         return 0;
2294
2295  failed_setup_stop_mode:
2296         unregister_flexcandev(dev);
2297  failed_register:
2298         pm_runtime_put_noidle(&pdev->dev);
2299         pm_runtime_disable(&pdev->dev);
2300  failed_platform_get_irq:
2301         free_candev(dev);
2302         return err;
2303 }
2304
2305 static int flexcan_remove(struct platform_device *pdev)
2306 {
2307         struct net_device *dev = platform_get_drvdata(pdev);
2308
2309         device_set_wakeup_enable(&pdev->dev, false);
2310         device_set_wakeup_capable(&pdev->dev, false);
2311         unregister_flexcandev(dev);
2312         pm_runtime_disable(&pdev->dev);
2313         free_candev(dev);
2314
2315         return 0;
2316 }
2317
2318 static int __maybe_unused flexcan_suspend(struct device *device)
2319 {
2320         struct net_device *dev = dev_get_drvdata(device);
2321         struct flexcan_priv *priv = netdev_priv(dev);
2322         int err;
2323
2324         if (netif_running(dev)) {
2325                 /* if wakeup is enabled, enter stop mode
2326                  * else enter disabled mode.
2327                  */
2328                 if (device_may_wakeup(device)) {
2329                         enable_irq_wake(dev->irq);
2330                         err = flexcan_enter_stop_mode(priv);
2331                         if (err)
2332                                 return err;
2333                 } else {
2334                         err = flexcan_chip_stop(dev);
2335                         if (err)
2336                                 return err;
2337
2338                         flexcan_chip_interrupts_disable(dev);
2339
2340                         err = pinctrl_pm_select_sleep_state(device);
2341                         if (err)
2342                                 return err;
2343                 }
2344                 netif_stop_queue(dev);
2345                 netif_device_detach(dev);
2346         }
2347         priv->can.state = CAN_STATE_SLEEPING;
2348
2349         return 0;
2350 }
2351
2352 static int __maybe_unused flexcan_resume(struct device *device)
2353 {
2354         struct net_device *dev = dev_get_drvdata(device);
2355         struct flexcan_priv *priv = netdev_priv(dev);
2356         int err;
2357
2358         priv->can.state = CAN_STATE_ERROR_ACTIVE;
2359         if (netif_running(dev)) {
2360                 netif_device_attach(dev);
2361                 netif_start_queue(dev);
2362                 if (device_may_wakeup(device)) {
2363                         disable_irq_wake(dev->irq);
2364                         err = flexcan_exit_stop_mode(priv);
2365                         if (err)
2366                                 return err;
2367                 } else {
2368                         err = pinctrl_pm_select_default_state(device);
2369                         if (err)
2370                                 return err;
2371
2372                         err = flexcan_chip_start(dev);
2373                         if (err)
2374                                 return err;
2375
2376                         flexcan_chip_interrupts_enable(dev);
2377                 }
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2384 {
2385         struct net_device *dev = dev_get_drvdata(device);
2386         struct flexcan_priv *priv = netdev_priv(dev);
2387
2388         flexcan_clks_disable(priv);
2389
2390         return 0;
2391 }
2392
2393 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2394 {
2395         struct net_device *dev = dev_get_drvdata(device);
2396         struct flexcan_priv *priv = netdev_priv(dev);
2397
2398         return flexcan_clks_enable(priv);
2399 }
2400
2401 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2402 {
2403         struct net_device *dev = dev_get_drvdata(device);
2404         struct flexcan_priv *priv = netdev_priv(dev);
2405
2406         if (netif_running(dev)) {
2407                 int err;
2408
2409                 if (device_may_wakeup(device))
2410                         flexcan_enable_wakeup_irq(priv, true);
2411
2412                 err = pm_runtime_force_suspend(device);
2413                 if (err)
2414                         return err;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2421 {
2422         struct net_device *dev = dev_get_drvdata(device);
2423         struct flexcan_priv *priv = netdev_priv(dev);
2424
2425         if (netif_running(dev)) {
2426                 int err;
2427
2428                 err = pm_runtime_force_resume(device);
2429                 if (err)
2430                         return err;
2431
2432                 if (device_may_wakeup(device))
2433                         flexcan_enable_wakeup_irq(priv, false);
2434         }
2435
2436         return 0;
2437 }
2438
2439 static const struct dev_pm_ops flexcan_pm_ops = {
2440         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2441         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2442         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2443 };
2444
2445 static struct platform_driver flexcan_driver = {
2446         .driver = {
2447                 .name = DRV_NAME,
2448                 .pm = &flexcan_pm_ops,
2449                 .of_match_table = flexcan_of_match,
2450         },
2451         .probe = flexcan_probe,
2452         .remove = flexcan_remove,
2453         .id_table = flexcan_id_table,
2454 };
2455
2456 module_platform_driver(flexcan_driver);
2457
2458 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2459               "Marc Kleine-Budde <kernel@pengutronix.de>");
2460 MODULE_LICENSE("GPL v2");
2461 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");