2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/pinctrl/consumer.h>
40 #include <linux/can.h>
41 #include <linux/can/dev.h>
42 #include <linux/can/error.h>
43 #include <linux/can/led.h>
47 /* Number of interface registers */
48 #define IF_ENUM_REG_LEN 11
49 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
51 /* control extension register D_CAN specific */
52 #define CONTROL_EX_PDR BIT(8)
54 /* control register */
55 #define CONTROL_SWR BIT(15)
56 #define CONTROL_TEST BIT(7)
57 #define CONTROL_CCE BIT(6)
58 #define CONTROL_DISABLE_AR BIT(5)
59 #define CONTROL_ENABLE_AR (0 << 5)
60 #define CONTROL_EIE BIT(3)
61 #define CONTROL_SIE BIT(2)
62 #define CONTROL_IE BIT(1)
63 #define CONTROL_INIT BIT(0)
65 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
68 #define TEST_RX BIT(7)
69 #define TEST_TX1 BIT(6)
70 #define TEST_TX2 BIT(5)
71 #define TEST_LBACK BIT(4)
72 #define TEST_SILENT BIT(3)
73 #define TEST_BASIC BIT(2)
76 #define STATUS_PDA BIT(10)
77 #define STATUS_BOFF BIT(7)
78 #define STATUS_EWARN BIT(6)
79 #define STATUS_EPASS BIT(5)
80 #define STATUS_RXOK BIT(4)
81 #define STATUS_TXOK BIT(3)
83 /* error counter register */
84 #define ERR_CNT_TEC_MASK 0xff
85 #define ERR_CNT_TEC_SHIFT 0
86 #define ERR_CNT_REC_SHIFT 8
87 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
88 #define ERR_CNT_RP_SHIFT 15
89 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
91 /* bit-timing register */
92 #define BTR_BRP_MASK 0x3f
93 #define BTR_BRP_SHIFT 0
94 #define BTR_SJW_SHIFT 6
95 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
96 #define BTR_TSEG1_SHIFT 8
97 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
98 #define BTR_TSEG2_SHIFT 12
99 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
101 /* interrupt register */
102 #define INT_STS_PENDING 0x8000
104 /* brp extension register */
105 #define BRP_EXT_BRPE_MASK 0x0f
106 #define BRP_EXT_BRPE_SHIFT 0
108 /* IFx command request */
109 #define IF_COMR_BUSY BIT(15)
111 /* IFx command mask */
112 #define IF_COMM_WR BIT(7)
113 #define IF_COMM_MASK BIT(6)
114 #define IF_COMM_ARB BIT(5)
115 #define IF_COMM_CONTROL BIT(4)
116 #define IF_COMM_CLR_INT_PND BIT(3)
117 #define IF_COMM_TXRQST BIT(2)
118 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
119 #define IF_COMM_DATAA BIT(1)
120 #define IF_COMM_DATAB BIT(0)
122 /* TX buffer setup */
123 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
125 IF_COMM_DATAA | IF_COMM_DATAB)
127 /* For the low buffers we clear the interrupt bit, but keep newdat */
128 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
130 IF_COMM_DATAA | IF_COMM_DATAB)
132 /* For the high buffers we clear the interrupt bit and newdat */
133 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
136 /* Receive setup of message objects */
137 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
139 /* Invalidation of message objects */
140 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
142 /* IFx arbitration */
143 #define IF_ARB_MSGVAL BIT(31)
144 #define IF_ARB_MSGXTD BIT(30)
145 #define IF_ARB_TRANSMIT BIT(29)
147 /* IFx message control */
148 #define IF_MCONT_NEWDAT BIT(15)
149 #define IF_MCONT_MSGLST BIT(14)
150 #define IF_MCONT_INTPND BIT(13)
151 #define IF_MCONT_UMASK BIT(12)
152 #define IF_MCONT_TXIE BIT(11)
153 #define IF_MCONT_RXIE BIT(10)
154 #define IF_MCONT_RMTEN BIT(9)
155 #define IF_MCONT_TXRQST BIT(8)
156 #define IF_MCONT_EOB BIT(7)
157 #define IF_MCONT_DLC_MASK 0xf
159 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
160 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
162 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
165 * Use IF1 for RX and IF2 for TX
170 /* minimum timeout for checking BUSY status */
171 #define MIN_TIMEOUT_VALUE 6
173 /* Wait for ~1 sec for INIT bit */
174 #define INIT_WAIT_MS 1000
177 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
179 /* c_can lec values */
180 enum c_can_lec_type {
189 LEC_MASK = LEC_UNUSED,
194 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
196 enum c_can_bus_error_types {
203 static const struct can_bittiming_const c_can_bittiming_const = {
204 .name = KBUILD_MODNAME,
205 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
207 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
211 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
215 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
218 pm_runtime_get_sync(priv->device);
221 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
224 pm_runtime_put_sync(priv->device);
227 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
230 priv->raminit(priv, enable);
233 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
235 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
238 ctrl |= CONTROL_IRQMSK;
240 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
243 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
245 struct c_can_priv *priv = netdev_priv(dev);
246 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
248 priv->write_reg32(priv, reg, (cmd << 16) | obj);
250 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
251 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
255 netdev_err(dev, "Updating object timed out\n");
259 static inline void c_can_object_get(struct net_device *dev, int iface,
262 c_can_obj_update(dev, iface, cmd, obj);
265 static inline void c_can_object_put(struct net_device *dev, int iface,
268 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
272 * Note: According to documentation clearing TXIE while MSGVAL is set
273 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
274 * load significantly.
276 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
278 struct c_can_priv *priv = netdev_priv(dev);
280 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
281 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
284 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
286 struct c_can_priv *priv = netdev_priv(dev);
288 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
289 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
290 c_can_inval_tx_object(dev, iface, obj);
293 static void c_can_setup_tx_object(struct net_device *dev, int iface,
294 struct can_frame *frame, int idx)
296 struct c_can_priv *priv = netdev_priv(dev);
297 u16 ctrl = IF_MCONT_TX | frame->can_dlc;
298 bool rtr = frame->can_id & CAN_RTR_FLAG;
299 u32 arb = IF_ARB_MSGVAL;
302 if (frame->can_id & CAN_EFF_FLAG) {
303 arb |= frame->can_id & CAN_EFF_MASK;
304 arb |= IF_ARB_MSGXTD;
306 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
310 arb |= IF_ARB_TRANSMIT;
313 * If we change the DIR bit, we need to invalidate the buffer
314 * first, i.e. clear the MSGVAL flag in the arbiter.
316 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
317 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
319 c_can_inval_msg_object(dev, iface, obj);
320 change_bit(idx, &priv->tx_dir);
323 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
325 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
327 if (priv->type == BOSCH_D_CAN) {
328 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
330 for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) {
331 data = (u32)frame->data[i];
332 data |= (u32)frame->data[i + 1] << 8;
333 data |= (u32)frame->data[i + 2] << 16;
334 data |= (u32)frame->data[i + 3] << 24;
335 priv->write_reg32(priv, dreg, data);
338 for (i = 0; i < frame->can_dlc; i += 2) {
339 priv->write_reg(priv,
340 C_CAN_IFACE(DATA1_REG, iface) + i / 2,
342 (frame->data[i + 1] << 8));
347 static int c_can_handle_lost_msg_obj(struct net_device *dev,
348 int iface, int objno, u32 ctrl)
350 struct net_device_stats *stats = &dev->stats;
351 struct c_can_priv *priv = netdev_priv(dev);
352 struct can_frame *frame;
355 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
356 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
357 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
360 stats->rx_over_errors++;
362 /* create an error msg */
363 skb = alloc_can_err_skb(dev, &frame);
367 frame->can_id |= CAN_ERR_CRTL;
368 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
370 netif_receive_skb(skb);
374 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
376 struct net_device_stats *stats = &dev->stats;
377 struct c_can_priv *priv = netdev_priv(dev);
378 struct can_frame *frame;
382 skb = alloc_can_skb(dev, &frame);
388 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
390 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
392 if (arb & IF_ARB_MSGXTD)
393 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
395 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
397 if (arb & IF_ARB_TRANSMIT) {
398 frame->can_id |= CAN_RTR_FLAG;
400 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
402 if (priv->type == BOSCH_D_CAN) {
403 for (i = 0; i < frame->can_dlc; i += 4, dreg += 2) {
404 data = priv->read_reg32(priv, dreg);
405 frame->data[i] = data;
406 frame->data[i + 1] = data >> 8;
407 frame->data[i + 2] = data >> 16;
408 frame->data[i + 3] = data >> 24;
411 for (i = 0; i < frame->can_dlc; i += 2, dreg++) {
412 data = priv->read_reg(priv, dreg);
413 frame->data[i] = data;
414 frame->data[i + 1] = data >> 8;
420 stats->rx_bytes += frame->can_dlc;
422 netif_receive_skb(skb);
426 static void c_can_setup_receive_object(struct net_device *dev, int iface,
427 u32 obj, u32 mask, u32 id, u32 mcont)
429 struct c_can_priv *priv = netdev_priv(dev);
432 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
435 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
437 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
438 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
441 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
442 struct net_device *dev)
444 struct can_frame *frame = (struct can_frame *)skb->data;
445 struct c_can_priv *priv = netdev_priv(dev);
448 if (can_dropped_invalid_skb(dev, skb))
451 * This is not a FIFO. C/D_CAN sends out the buffers
452 * prioritized. The lowest buffer number wins.
454 idx = fls(atomic_read(&priv->tx_active));
455 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
457 /* If this is the last buffer, stop the xmit queue */
458 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1)
459 netif_stop_queue(dev);
461 * Store the message in the interface so we can call
462 * can_put_echo_skb(). We must do this before we enable
463 * transmit as we might race against do_tx().
465 c_can_setup_tx_object(dev, IF_TX, frame, idx);
466 priv->dlc[idx] = frame->can_dlc;
467 can_put_echo_skb(skb, dev, idx);
469 /* Update the active bits */
470 atomic_add((1 << idx), &priv->tx_active);
471 /* Start transmission */
472 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
477 static int c_can_wait_for_ctrl_init(struct net_device *dev,
478 struct c_can_priv *priv, u32 init)
482 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
484 if (retry++ > 1000) {
485 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
492 static int c_can_set_bittiming(struct net_device *dev)
494 unsigned int reg_btr, reg_brpe, ctrl_save;
495 u8 brp, brpe, sjw, tseg1, tseg2;
497 struct c_can_priv *priv = netdev_priv(dev);
498 const struct can_bittiming *bt = &priv->can.bittiming;
501 /* c_can provides a 6-bit brp and 4-bit brpe fields */
502 ten_bit_brp = bt->brp - 1;
503 brp = ten_bit_brp & BTR_BRP_MASK;
504 brpe = ten_bit_brp >> 6;
507 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
508 tseg2 = bt->phase_seg2 - 1;
509 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
510 (tseg2 << BTR_TSEG2_SHIFT);
511 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
514 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
516 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
517 ctrl_save &= ~CONTROL_INIT;
518 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
519 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
523 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
524 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
525 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
527 return c_can_wait_for_ctrl_init(dev, priv, 0);
531 * Configure C_CAN message objects for Tx and Rx purposes:
532 * C_CAN provides a total of 32 message objects that can be configured
533 * either for Tx or Rx purposes. Here the first 16 message objects are used as
534 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
535 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
536 * See user guide document for further details on configuring message
539 static void c_can_configure_msg_objects(struct net_device *dev)
543 /* first invalidate all message objects */
544 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
545 c_can_inval_msg_object(dev, IF_RX, i);
547 /* setup receive message objects */
548 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
549 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
551 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
555 static int c_can_software_reset(struct net_device *dev)
557 struct c_can_priv *priv = netdev_priv(dev);
560 if (priv->type != BOSCH_D_CAN)
563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
564 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
567 netdev_err(dev, "CCTRL: software reset failed\n");
576 * Configure C_CAN chip:
577 * - enable/disable auto-retransmission
578 * - set operating mode
579 * - configure message objects
581 static int c_can_chip_config(struct net_device *dev)
583 struct c_can_priv *priv = netdev_priv(dev);
586 err = c_can_software_reset(dev);
590 /* enable automatic retransmission */
591 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
593 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
594 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
595 /* loopback + silent mode : useful for hot self-test */
596 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
597 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
598 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
599 /* loopback mode : useful for self-test function */
600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
601 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
602 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
603 /* silent mode : bus-monitoring mode */
604 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
605 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
608 /* configure message objects */
609 c_can_configure_msg_objects(dev);
611 /* set a `lec` value so that we can check for updates later */
612 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
614 /* Clear all internal status */
615 atomic_set(&priv->tx_active, 0);
619 /* set bittiming params */
620 return c_can_set_bittiming(dev);
623 static int c_can_start(struct net_device *dev)
625 struct c_can_priv *priv = netdev_priv(dev);
629 /* basic c_can configuration */
630 err = c_can_chip_config(dev);
634 /* Setup the command for new messages */
635 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
636 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
638 priv->can.state = CAN_STATE_ERROR_ACTIVE;
640 /* Attempt to use "active" if available else use "default" */
641 p = pinctrl_get_select(priv->device, "active");
645 pinctrl_pm_select_default_state(priv->device);
650 static void c_can_stop(struct net_device *dev)
652 struct c_can_priv *priv = netdev_priv(dev);
654 c_can_irq_control(priv, false);
656 /* put ctrl to init on stop to end ongoing transmission */
657 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
659 /* deactivate pins */
660 pinctrl_pm_select_sleep_state(dev->dev.parent);
661 priv->can.state = CAN_STATE_STOPPED;
664 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
666 struct c_can_priv *priv = netdev_priv(dev);
671 err = c_can_start(dev);
674 netif_wake_queue(dev);
675 c_can_irq_control(priv, true);
684 static int __c_can_get_berr_counter(const struct net_device *dev,
685 struct can_berr_counter *bec)
687 unsigned int reg_err_counter;
688 struct c_can_priv *priv = netdev_priv(dev);
690 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
691 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
693 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
698 static int c_can_get_berr_counter(const struct net_device *dev,
699 struct can_berr_counter *bec)
701 struct c_can_priv *priv = netdev_priv(dev);
704 c_can_pm_runtime_get_sync(priv);
705 err = __c_can_get_berr_counter(dev, bec);
706 c_can_pm_runtime_put_sync(priv);
711 static void c_can_do_tx(struct net_device *dev)
713 struct c_can_priv *priv = netdev_priv(dev);
714 struct net_device_stats *stats = &dev->stats;
715 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
717 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
719 while ((idx = ffs(pend))) {
722 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
723 c_can_inval_tx_object(dev, IF_RX, obj);
724 can_get_echo_skb(dev, idx);
725 bytes += priv->dlc[idx];
729 /* Clear the bits in the tx_active mask */
730 atomic_sub(clr, &priv->tx_active);
732 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1)))
733 netif_wake_queue(dev);
736 stats->tx_bytes += bytes;
737 stats->tx_packets += pkts;
738 can_led_event(dev, CAN_LED_EVENT_TX);
743 * If we have a gap in the pending bits, that means we either
744 * raced with the hardware or failed to readout all upper
745 * objects in the last run due to quota limit.
747 static u32 c_can_adjust_pending(u32 pend)
751 if (pend == RECEIVE_OBJECT_BITS)
755 * If the last set bit is larger than the number of pending
756 * bits we have a gap.
758 weight = hweight32(pend);
761 /* If the bits are linear, nothing to do */
766 * Find the first set bit after the gap. We walk backwards
767 * from the last set bit.
769 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
771 return pend & ~((1 << lasts) - 1);
774 static inline void c_can_rx_object_get(struct net_device *dev,
775 struct c_can_priv *priv, u32 obj)
777 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
780 static inline void c_can_rx_finalize(struct net_device *dev,
781 struct c_can_priv *priv, u32 obj)
783 if (priv->type != BOSCH_D_CAN)
784 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
787 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
790 u32 pkts = 0, ctrl, obj;
792 while ((obj = ffs(pend)) && quota > 0) {
793 pend &= ~BIT(obj - 1);
795 c_can_rx_object_get(dev, priv, obj);
796 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
798 if (ctrl & IF_MCONT_MSGLST) {
799 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
807 * This really should not happen, but this covers some
808 * odd HW behaviour. Do not remove that unless you
809 * want to brick your machine.
811 if (!(ctrl & IF_MCONT_NEWDAT))
814 /* read the data from the message object */
815 c_can_read_msg_object(dev, IF_RX, ctrl);
817 c_can_rx_finalize(dev, priv, obj);
826 static inline u32 c_can_get_pending(struct c_can_priv *priv)
828 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
834 * theory of operation:
836 * c_can core saves a received CAN message into the first free message
837 * object it finds free (starting with the lowest). Bits NEWDAT and
838 * INTPND are set for this message object indicating that a new message
839 * has arrived. To work-around this issue, we keep two groups of message
840 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
842 * We clear the newdat bit right away.
844 * This can result in packet reordering when the readout is slow.
846 static int c_can_do_rx_poll(struct net_device *dev, int quota)
848 struct c_can_priv *priv = netdev_priv(dev);
849 u32 pkts = 0, pend = 0, toread, n;
852 * It is faster to read only one 16bit register. This is only possible
853 * for a maximum number of 16 objects.
855 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
856 "Implementation does not support more message objects than 16");
860 pend = c_can_get_pending(priv);
864 * If the pending field has a gap, handle the
865 * bits above the gap first.
867 toread = c_can_adjust_pending(pend);
871 /* Remove the bits from pend */
873 /* Read the objects */
874 n = c_can_read_objects(dev, priv, toread, quota);
880 can_led_event(dev, CAN_LED_EVENT_RX);
885 static int c_can_handle_state_change(struct net_device *dev,
886 enum c_can_bus_error_types error_type)
888 unsigned int reg_err_counter;
889 unsigned int rx_err_passive;
890 struct c_can_priv *priv = netdev_priv(dev);
891 struct net_device_stats *stats = &dev->stats;
892 struct can_frame *cf;
894 struct can_berr_counter bec;
896 switch (error_type) {
898 priv->can.state = CAN_STATE_ERROR_ACTIVE;
900 case C_CAN_ERROR_WARNING:
901 /* error warning state */
902 priv->can.can_stats.error_warning++;
903 priv->can.state = CAN_STATE_ERROR_WARNING;
905 case C_CAN_ERROR_PASSIVE:
906 /* error passive state */
907 priv->can.can_stats.error_passive++;
908 priv->can.state = CAN_STATE_ERROR_PASSIVE;
912 priv->can.state = CAN_STATE_BUS_OFF;
913 priv->can.can_stats.bus_off++;
919 /* propagate the error condition to the CAN stack */
920 skb = alloc_can_err_skb(dev, &cf);
924 __c_can_get_berr_counter(dev, &bec);
925 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
926 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
929 switch (error_type) {
931 /* error warning state */
932 cf->can_id |= CAN_ERR_CRTL;
933 cf->data[1] = CAN_ERR_CRTL_ACTIVE;
934 cf->data[6] = bec.txerr;
935 cf->data[7] = bec.rxerr;
937 case C_CAN_ERROR_WARNING:
938 /* error warning state */
939 cf->can_id |= CAN_ERR_CRTL;
940 cf->data[1] = (bec.txerr > bec.rxerr) ?
941 CAN_ERR_CRTL_TX_WARNING :
942 CAN_ERR_CRTL_RX_WARNING;
943 cf->data[6] = bec.txerr;
944 cf->data[7] = bec.rxerr;
947 case C_CAN_ERROR_PASSIVE:
948 /* error passive state */
949 cf->can_id |= CAN_ERR_CRTL;
951 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
953 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
955 cf->data[6] = bec.txerr;
956 cf->data[7] = bec.rxerr;
960 cf->can_id |= CAN_ERR_BUSOFF;
968 stats->rx_bytes += cf->can_dlc;
969 netif_receive_skb(skb);
974 static int c_can_handle_bus_err(struct net_device *dev,
975 enum c_can_lec_type lec_type)
977 struct c_can_priv *priv = netdev_priv(dev);
978 struct net_device_stats *stats = &dev->stats;
979 struct can_frame *cf;
983 * early exit if no lec update or no error.
984 * no lec update means that no CAN bus event has been detected
985 * since CPU wrote 0x7 value to status reg.
987 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
990 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
993 /* common for all type of bus errors */
994 priv->can.can_stats.bus_error++;
997 /* propagate the error condition to the CAN stack */
998 skb = alloc_can_err_skb(dev, &cf);
1003 * check for 'last error code' which tells us the
1004 * type of the last error to occur on the CAN bus
1006 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1009 case LEC_STUFF_ERROR:
1010 netdev_dbg(dev, "stuff error\n");
1011 cf->data[2] |= CAN_ERR_PROT_STUFF;
1013 case LEC_FORM_ERROR:
1014 netdev_dbg(dev, "form error\n");
1015 cf->data[2] |= CAN_ERR_PROT_FORM;
1018 netdev_dbg(dev, "ack error\n");
1019 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1021 case LEC_BIT1_ERROR:
1022 netdev_dbg(dev, "bit1 error\n");
1023 cf->data[2] |= CAN_ERR_PROT_BIT1;
1025 case LEC_BIT0_ERROR:
1026 netdev_dbg(dev, "bit0 error\n");
1027 cf->data[2] |= CAN_ERR_PROT_BIT0;
1030 netdev_dbg(dev, "CRC error\n");
1031 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1037 stats->rx_packets++;
1038 stats->rx_bytes += cf->can_dlc;
1039 netif_receive_skb(skb);
1043 static int c_can_poll(struct napi_struct *napi, int quota)
1045 struct net_device *dev = napi->dev;
1046 struct c_can_priv *priv = netdev_priv(dev);
1047 u16 curr, last = priv->last_status;
1050 /* Only read the status register if a status interrupt was pending */
1051 if (atomic_xchg(&priv->sie_pending, 0)) {
1052 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
1053 /* Ack status on C_CAN. D_CAN is self clearing */
1054 if (priv->type != BOSCH_D_CAN)
1055 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1057 /* no change detected ... */
1061 /* handle state changes */
1062 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1063 netdev_dbg(dev, "entered error warning state\n");
1064 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1067 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1068 netdev_dbg(dev, "entered error passive state\n");
1069 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1072 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1073 netdev_dbg(dev, "entered bus off state\n");
1074 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1078 /* handle bus recovery events */
1079 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1080 netdev_dbg(dev, "left bus off state\n");
1081 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1084 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1085 netdev_dbg(dev, "left error passive state\n");
1086 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1089 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1090 netdev_dbg(dev, "left error warning state\n");
1091 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1094 /* handle lec errors on the bus */
1095 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1097 /* Handle Tx/Rx events. We do this unconditionally */
1098 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1102 if (work_done < quota) {
1103 napi_complete_done(napi, work_done);
1104 /* enable all IRQs if we are not in bus off state */
1105 if (priv->can.state != CAN_STATE_BUS_OFF)
1106 c_can_irq_control(priv, true);
1112 static irqreturn_t c_can_isr(int irq, void *dev_id)
1114 struct net_device *dev = (struct net_device *)dev_id;
1115 struct c_can_priv *priv = netdev_priv(dev);
1118 reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1122 /* save for later use */
1123 if (reg_int & INT_STS_PENDING)
1124 atomic_set(&priv->sie_pending, 1);
1126 /* disable all interrupts and schedule the NAPI */
1127 c_can_irq_control(priv, false);
1128 napi_schedule(&priv->napi);
1133 static int c_can_open(struct net_device *dev)
1136 struct c_can_priv *priv = netdev_priv(dev);
1138 c_can_pm_runtime_get_sync(priv);
1139 c_can_reset_ram(priv, true);
1141 /* open the can device */
1142 err = open_candev(dev);
1144 netdev_err(dev, "failed to open can device\n");
1145 goto exit_open_fail;
1148 /* register interrupt handler */
1149 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1152 netdev_err(dev, "failed to request interrupt\n");
1156 /* start the c_can controller */
1157 err = c_can_start(dev);
1159 goto exit_start_fail;
1161 can_led_event(dev, CAN_LED_EVENT_OPEN);
1163 napi_enable(&priv->napi);
1164 /* enable status change, error and module interrupts */
1165 c_can_irq_control(priv, true);
1166 netif_start_queue(dev);
1171 free_irq(dev->irq, dev);
1175 c_can_reset_ram(priv, false);
1176 c_can_pm_runtime_put_sync(priv);
1180 static int c_can_close(struct net_device *dev)
1182 struct c_can_priv *priv = netdev_priv(dev);
1184 netif_stop_queue(dev);
1185 napi_disable(&priv->napi);
1187 free_irq(dev->irq, dev);
1190 c_can_reset_ram(priv, false);
1191 c_can_pm_runtime_put_sync(priv);
1193 can_led_event(dev, CAN_LED_EVENT_STOP);
1198 struct net_device *alloc_c_can_dev(void)
1200 struct net_device *dev;
1201 struct c_can_priv *priv;
1203 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1207 priv = netdev_priv(dev);
1208 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1211 priv->can.bittiming_const = &c_can_bittiming_const;
1212 priv->can.do_set_mode = c_can_set_mode;
1213 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1214 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1215 CAN_CTRLMODE_LISTENONLY |
1216 CAN_CTRLMODE_BERR_REPORTING;
1220 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1223 int c_can_power_down(struct net_device *dev)
1226 unsigned long time_out;
1227 struct c_can_priv *priv = netdev_priv(dev);
1229 if (!(dev->flags & IFF_UP))
1232 WARN_ON(priv->type != BOSCH_D_CAN);
1234 /* set PDR value so the device goes to power down mode */
1235 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1236 val |= CONTROL_EX_PDR;
1237 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1239 /* Wait for the PDA bit to get set */
1240 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1241 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1242 time_after(time_out, jiffies))
1245 if (time_after(jiffies, time_out))
1250 c_can_reset_ram(priv, false);
1251 c_can_pm_runtime_put_sync(priv);
1255 EXPORT_SYMBOL_GPL(c_can_power_down);
1257 int c_can_power_up(struct net_device *dev)
1260 unsigned long time_out;
1261 struct c_can_priv *priv = netdev_priv(dev);
1264 if (!(dev->flags & IFF_UP))
1267 WARN_ON(priv->type != BOSCH_D_CAN);
1269 c_can_pm_runtime_get_sync(priv);
1270 c_can_reset_ram(priv, true);
1272 /* Clear PDR and INIT bits */
1273 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1274 val &= ~CONTROL_EX_PDR;
1275 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1276 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1277 val &= ~CONTROL_INIT;
1278 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1280 /* Wait for the PDA bit to get clear */
1281 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1282 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1283 time_after(time_out, jiffies))
1286 if (time_after(jiffies, time_out)) {
1291 ret = c_can_start(dev);
1295 c_can_irq_control(priv, true);
1300 c_can_reset_ram(priv, false);
1301 c_can_pm_runtime_put_sync(priv);
1305 EXPORT_SYMBOL_GPL(c_can_power_up);
1308 void free_c_can_dev(struct net_device *dev)
1310 struct c_can_priv *priv = netdev_priv(dev);
1312 netif_napi_del(&priv->napi);
1315 EXPORT_SYMBOL_GPL(free_c_can_dev);
1317 static const struct net_device_ops c_can_netdev_ops = {
1318 .ndo_open = c_can_open,
1319 .ndo_stop = c_can_close,
1320 .ndo_start_xmit = c_can_start_xmit,
1321 .ndo_change_mtu = can_change_mtu,
1324 int register_c_can_dev(struct net_device *dev)
1328 /* Deactivate pins to prevent DRA7 DCAN IP from being
1329 * stuck in transition when module is disabled.
1330 * Pins are activated in c_can_start() and deactivated
1333 pinctrl_pm_select_sleep_state(dev->dev.parent);
1335 dev->flags |= IFF_ECHO; /* we support local echo */
1336 dev->netdev_ops = &c_can_netdev_ops;
1338 err = register_candev(dev);
1340 devm_can_led_init(dev);
1343 EXPORT_SYMBOL_GPL(register_c_can_dev);
1345 void unregister_c_can_dev(struct net_device *dev)
1347 unregister_candev(dev);
1349 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1351 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1352 MODULE_LICENSE("GPL v2");
1353 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");