1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 #include <linux/mtd/spi-nor.h>
11 #define XILINX_OP_SE 0x50 /* Sector erase */
12 #define XILINX_OP_PP 0x82 /* Page program */
13 #define XILINX_OP_RDSR 0xd7 /* Read status register */
15 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
16 #define XSR_RDY BIT(7) /* Ready */
18 #define XILINX_RDSR_OP(buf) \
19 SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \
21 SPI_MEM_OP_NO_DUMMY, \
22 SPI_MEM_OP_DATA_IN(1, buf, 0))
24 #define S3AN_FLASH(_id, _name, _n_sectors, _page_size) \
27 .size = 8 * (_page_size) * (_n_sectors), \
28 .sector_size = (8 * (_page_size)), \
29 .page_size = (_page_size), \
30 .flags = SPI_NOR_NO_FR
32 /* Xilinx S3AN share MFR with Atmel SPI NOR */
33 static const struct flash_info xilinx_nor_parts[] = {
34 /* Xilinx S3AN Internal Flash */
35 { S3AN_FLASH(SNOR_ID(0x1f, 0x22, 0x00), "3S50AN", 64, 264) },
36 { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S200AN", 256, 264) },
37 { S3AN_FLASH(SNOR_ID(0x1f, 0x24, 0x00), "3S400AN", 256, 264) },
38 { S3AN_FLASH(SNOR_ID(0x1f, 0x25, 0x00), "3S700AN", 512, 264) },
39 { S3AN_FLASH(SNOR_ID(0x1f, 0x26, 0x00), "3S1400AN", 512, 528) },
43 * This code converts an address to the Default Address Mode, that has non
44 * power of two page sizes. We must support this mode because it is the default
45 * mode supported by Xilinx tools, it can access the whole flash area and
46 * changing over to the Power-of-two mode is irreversible and corrupts the
48 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
51 static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
53 u32 page_size = nor->params->page_size;
56 offset = addr % page_size;
57 page = addr / page_size;
58 page <<= (page_size > 512) ? 10 : 9;
64 * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
65 * @nor: pointer to 'struct spi_nor'.
66 * @sr: pointer to a DMA-able buffer where the value of the
67 * Status Register will be written.
69 * Return: 0 on success, -errno otherwise.
71 static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
76 struct spi_mem_op op = XILINX_RDSR_OP(sr);
78 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
80 ret = spi_mem_exec_op(nor->spimem, &op);
82 ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr,
87 dev_dbg(nor->dev, "error %d reading SR\n", ret);
93 * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see
94 * if the flash is ready for new commands.
95 * @nor: pointer to 'struct spi_nor'.
97 * Return: 1 if ready, 0 if not ready, -errno on errors.
99 static int xilinx_nor_sr_ready(struct spi_nor *nor)
103 ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
107 return !!(nor->bouncebuf[0] & XSR_RDY);
110 static int xilinx_nor_setup(struct spi_nor *nor,
111 const struct spi_nor_hwcaps *hwcaps)
116 ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
120 nor->erase_opcode = XILINX_OP_SE;
121 nor->program_opcode = XILINX_OP_PP;
122 nor->read_opcode = SPINOR_OP_READ;
123 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
126 * This flashes have a page size of 264 or 528 bytes (known as
127 * Default addressing mode). It can be changed to a more standard
128 * Power of two mode where the page size is 256/512. This comes
129 * with a price: there is 3% less of space, the data is corrupted
130 * and the page size cannot be changed back to default addressing
133 * The current addressing mode can be read from the XRDSR register
134 * and should not be changed, because is a destructive operation.
136 if (nor->bouncebuf[0] & XSR_PAGESIZE) {
137 /* Flash in Power of 2 mode */
138 page_size = (nor->params->page_size == 264) ? 256 : 512;
139 nor->params->page_size = page_size;
140 nor->mtd.writebufsize = page_size;
141 nor->params->size = nor->info->size;
142 nor->mtd.erasesize = 8 * page_size;
144 /* Flash in Default addressing mode */
145 nor->params->convert_addr = s3an_nor_convert_addr;
146 nor->mtd.erasesize = nor->info->sector_size;
152 static int xilinx_nor_late_init(struct spi_nor *nor)
154 nor->params->setup = xilinx_nor_setup;
155 nor->params->ready = xilinx_nor_sr_ready;
160 static const struct spi_nor_fixups xilinx_nor_fixups = {
161 .late_init = xilinx_nor_late_init,
164 const struct spi_nor_manufacturer spi_nor_xilinx = {
166 .parts = xilinx_nor_parts,
167 .nparts = ARRAY_SIZE(xilinx_nor_parts),
168 .fixups = &xilinx_nor_fixups,