drivers/mtd/spi-nor/winbond.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static int
  12 w25q256_post_bfpt_fixups(struct spi_nor *nor,
  13                          const struct sfdp_parameter_header *bfpt_header,
  14                          const struct sfdp_bfpt *bfpt)
  15 {
  16         /*
  17          * W25Q256JV supports 4B opcodes but W25Q256FV does not.
  18          * Unfortunately, Winbond has re-used the same JEDEC ID for both
  19          * variants which prevents us from defining a new entry in the parts
  20          * table.
  21          * To differentiate between W25Q256JV and W25Q256FV check SFDP header
  22          * version: only JV has JESD216A compliant structure (version 5).
  23          */
  24         if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  25             bfpt_header->minor == SFDP_JESD216A_MINOR)
  26                 nor->flags |= SNOR_F_4B_OPCODES;
  27
  28         return 0;
  29 }
  30
  31 static struct spi_nor_fixups w25q256_fixups = {
  32         .post_bfpt = w25q256_post_bfpt_fixups,
  33 };
  34
  35 static const struct flash_info winbond_parts[] = {
  36         /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  37         { "w25x05", INFO(0xef3010, 0, 64 * 1024,  1,  SECT_4K) },
  38         { "w25x10", INFO(0xef3011, 0, 64 * 1024,  2,  SECT_4K) },
  39         { "w25x20", INFO(0xef3012, 0, 64 * 1024,  4,  SECT_4K) },
  40         { "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
  41         { "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
  42         { "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
  43         { "w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
  44                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  45                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  46         { "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
  47         { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024,  32,
  48                                  SECT_4K | SPI_NOR_DUAL_READ |
  49                                  SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
  50                                  SPI_NOR_HAS_TB) },
  51         { "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
  52         { "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
  53         { "w25q20ew", INFO(0xef6012, 0, 64 * 1024,  4, SECT_4K) },
  54         { "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
  55         { "w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
  56                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  57                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  58                            OTP_INFO(256, 3, 0x1000, 0x1000)
  59         },
  60
  61         { "w25q32jv", INFO(0xef7016, 0, 64 * 1024,  64,
  62                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  63                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  64         },
  65         { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024,  64,
  66                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  67                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  68                             OTP_INFO(256, 3, 0x1000, 0x1000) },
  69         { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128,
  70                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  71                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  72         { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256,
  73                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  74                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  75         { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512,
  76                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  77                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  78         { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
  79         { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128,
  80                          SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  81         { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
  82                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  83                            SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  84         { "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128, SECT_4K) },
  85         { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
  86                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  87                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  88         { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
  89                             SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  90                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
  91         { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
  92         { "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
  93         { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
  94         { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
  95                           SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  96           .fixups = &w25q256_fixups },
  97         { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
  98                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  99         { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
 100                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 101         { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
 102                             SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
 103         { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024,
 104                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 105 };
 106
 107 /**
 108  * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
 109  * @nor:        pointer to 'struct spi_nor'.
 110  * @enable:     true to enter the 4-byte address mode, false to exit the 4-byte
 111  *              address mode.
 112  *
 113  * Return: 0 on success, -errno otherwise.
 114  */
 115 static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 116 {
 117         int ret;
 118
 119         ret = spi_nor_set_4byte_addr_mode(nor, enable);
 120         if (ret || enable)
 121                 return ret;
 122
 123         /*
 124          * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
 125          * Register to be set to 1, so all 3-byte-address reads come from the
 126          * second 16M. We must clear the register to enable normal behavior.
 127          */
 128         ret = spi_nor_write_enable(nor);
 129         if (ret)
 130                 return ret;
 131
 132         ret = spi_nor_write_ear(nor, 0);
 133         if (ret)
 134                 return ret;
 135
 136         return spi_nor_write_disable(nor);
 137 }
 138
 139 static const struct spi_nor_otp_ops winbond_otp_ops = {
 140         .read = spi_nor_otp_read_secr,
 141         .write = spi_nor_otp_write_secr,
 142         .erase = spi_nor_otp_erase_secr,
 143         .lock = spi_nor_otp_lock_sr2,
 144         .is_locked = spi_nor_otp_is_locked_sr2,
 145 };
 146
 147 static void winbond_default_init(struct spi_nor *nor)
 148 {
 149         nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
 150         if (nor->params->otp.org->n_regions)
 151                 nor->params->otp.ops = &winbond_otp_ops;
 152 }
 153
 154 static const struct spi_nor_fixups winbond_fixups = {
 155         .default_init = winbond_default_init,
 156 };
 157
 158 const struct spi_nor_manufacturer spi_nor_winbond = {
 159         .name = "winbond",
 160         .parts = winbond_parts,
 161         .nparts = ARRAY_SIZE(winbond_parts),
 162         .fixups = &winbond_fixups,
 163 };