drivers/mtd/spi-nor/spansion.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 #define SPINOR_OP_RD_ANY_REG                    0x65    /* Read any register */
  12 #define SPINOR_OP_WR_ANY_REG                    0x71    /* Write any register */
  13 #define SPINOR_REG_CYPRESS_CFR2V                0x00800003
  14 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24   0xb
  15 #define SPINOR_REG_CYPRESS_CFR3V                0x00800004
  16 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ           BIT(4) /* Page size. */
  17 #define SPINOR_REG_CYPRESS_CFR5V                0x00800006
  18 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN     0x3
  19 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS     0
  20 #define SPINOR_OP_CYPRESS_RD_FAST               0xee
  21
  22 /**
  23  * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  24  * @nor:                pointer to a 'struct spi_nor'
  25  * @enable:              whether to enable or disable Octal DTR
  26  *
  27  * This also sets the memory access latency cycles to 24 to allow the flash to
  28  * run at up to 200MHz.
  29  *
  30  * Return: 0 on success, -errno otherwise.
  31  */
  32 static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
  33 {
  34         struct spi_mem_op op;
  35         u8 *buf = nor->bouncebuf;
  36         int ret;
  37
  38         if (enable) {
  39                 /* Use 24 dummy cycles for memory array reads. */
  40                 ret = spi_nor_write_enable(nor);
  41                 if (ret)
  42                         return ret;
  43
  44                 *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
  45                 op = (struct spi_mem_op)
  46                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  47                                    SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V,
  48                                                    1),
  49                                    SPI_MEM_OP_NO_DUMMY,
  50                                    SPI_MEM_OP_DATA_OUT(1, buf, 1));
  51
  52                 ret = spi_mem_exec_op(nor->spimem, &op);
  53                 if (ret)
  54                         return ret;
  55
  56                 ret = spi_nor_wait_till_ready(nor);
  57                 if (ret)
  58                         return ret;
  59
  60                 nor->read_dummy = 24;
  61         }
  62
  63         /* Set/unset the octal and DTR enable bits. */
  64         ret = spi_nor_write_enable(nor);
  65         if (ret)
  66                 return ret;
  67
  68         if (enable)
  69                 *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
  70         else
  71                 *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
  72
  73         op = (struct spi_mem_op)
  74                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  75                            SPI_MEM_OP_ADDR(enable ? 3 : 4,
  76                                            SPINOR_REG_CYPRESS_CFR5V,
  77                                            1),
  78                            SPI_MEM_OP_NO_DUMMY,
  79                            SPI_MEM_OP_DATA_OUT(1, buf, 1));
  80
  81         if (!enable)
  82                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  83
  84         ret = spi_mem_exec_op(nor->spimem, &op);
  85         if (ret)
  86                 return ret;
  87
  88         /* Read flash ID to make sure the switch was successful. */
  89         op = (struct spi_mem_op)
  90                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
  91                            SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1),
  92                            SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1),
  93                            SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2),
  94                                               buf, 1));
  95
  96         if (enable)
  97                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  98
  99         ret = spi_mem_exec_op(nor->spimem, &op);
 100         if (ret)
 101                 return ret;
 102
 103         if (memcmp(buf, nor->info->id, nor->info->id_len))
 104                 return -EINVAL;
 105
 106         return 0;
 107 }
 108
 109 static void s28hs512t_default_init(struct spi_nor *nor)
 110 {
 111         nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
 112         nor->params->writesize = 16;
 113 }
 114
 115 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
 116 {
 117         /*
 118          * On older versions of the flash the xSPI Profile 1.0 table has the
 119          * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
 120          */
 121         if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
 122                 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
 123                         SPINOR_OP_CYPRESS_RD_FAST;
 124
 125         /* This flash is also missing the 4-byte Page Program opcode bit. */
 126         spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
 127                                 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
 128         /*
 129          * Since xSPI Page Program opcode is backward compatible with
 130          * Legacy SPI, use Legacy SPI opcode there as well.
 131          */
 132         spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
 133                                 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
 134
 135         /*
 136          * The xSPI Profile 1.0 table advertises the number of additional
 137          * address bytes needed for Read Status Register command as 0 but the
 138          * actual value for that is 4.
 139          */
 140         nor->params->rdsr_addr_nbytes = 4;
 141 }
 142
 143 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
 144                                      const struct sfdp_parameter_header *bfpt_header,
 145                                      const struct sfdp_bfpt *bfpt)
 146 {
 147         /*
 148          * The BFPT table advertises a 512B page size but the page size is
 149          * actually configurable (with the default being 256B). Read from
 150          * CFR3V[4] and set the correct size.
 151          */
 152         struct spi_mem_op op =
 153                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
 154                            SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1),
 155                            SPI_MEM_OP_NO_DUMMY,
 156                            SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
 157         int ret;
 158
 159         ret = spi_mem_exec_op(nor->spimem, &op);
 160         if (ret)
 161                 return ret;
 162
 163         if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
 164                 nor->params->page_size = 512;
 165         else
 166                 nor->params->page_size = 256;
 167
 168         return 0;
 169 }
 170
 171 static struct spi_nor_fixups s28hs512t_fixups = {
 172         .default_init = s28hs512t_default_init,
 173         .post_sfdp = s28hs512t_post_sfdp_fixup,
 174         .post_bfpt = s28hs512t_post_bfpt_fixup,
 175 };
 176
 177 static int
 178 s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
 179                          const struct sfdp_parameter_header *bfpt_header,
 180                          const struct sfdp_bfpt *bfpt)
 181 {
 182         /*
 183          * The S25FS-S chip family reports 512-byte pages in BFPT but
 184          * in reality the write buffer still wraps at the safe default
 185          * of 256 bytes.  Overwrite the page size advertised by BFPT
 186          * to get the writes working.
 187          */
 188         nor->params->page_size = 256;
 189
 190         return 0;
 191 }
 192
 193 static struct spi_nor_fixups s25fs_s_fixups = {
 194         .post_bfpt = s25fs_s_post_bfpt_fixups,
 195 };
 196
 197 static const struct flash_info spansion_parts[] = {
 198         /* Spansion/Cypress -- single (large) sector size only, at least
 199          * for the chips listed here (without boot sectors).
 200          */
 201         { "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64,
 202                              SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 203         { "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128,
 204                              SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 205         { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
 206                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 207                               USE_CLSR) },
 208         { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
 209                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 210                               USE_CLSR) },
 211         { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128,
 212                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 213                               USE_CLSR) },
 214         { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512,
 215                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 216                               USE_CLSR) },
 217         { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
 218                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 219                               SPI_NOR_HAS_LOCK | USE_CLSR) },
 220         { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256,
 221                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
 222           .fixups = &s25fs_s_fixups, },
 223         { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128,
 224                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 225                               USE_CLSR) },
 226         { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512,
 227                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 228                               USE_CLSR) },
 229         { "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
 230                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
 231           .fixups = &s25fs_s_fixups, },
 232         { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
 233         { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
 234         { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64,
 235                              SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 236                              USE_CLSR) },
 237         { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256,
 238                              SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 239                              USE_CLSR) },
 240         { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
 241         { "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
 242         { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
 243         { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
 244         { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
 245         { "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8,
 246                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 247         { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16,
 248                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 249         { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32,
 250                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 251         { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128,
 252                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 253         { "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32,
 254                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 255         { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },
 256         { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
 257         { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8,
 258                              SECT_4K | SPI_NOR_DUAL_READ) },
 259         { "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16,
 260                              SECT_4K | SPI_NOR_DUAL_READ) },
 261         { "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128,
 262                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 263                              SPI_NOR_4B_OPCODES) },
 264         { "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256,
 265                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 266                              SPI_NOR_4B_OPCODES) },
 267         { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512,
 268                              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 269                              SPI_NOR_4B_OPCODES) },
 270         { "cy15x104q",  INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1,
 271                               SPI_NOR_NO_ERASE) },
 272         { "s28hs512t",   INFO(0x345b1a,      0, 256 * 1024, 256,
 273                              SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 274                               SPI_NOR_OCTAL_DTR_PP)
 275           .fixups = &s28hs512t_fixups,
 276         },
 277 };
 278
 279 static void spansion_post_sfdp_fixups(struct spi_nor *nor)
 280 {
 281         if (nor->params->size <= SZ_16M)
 282                 return;
 283
 284         nor->flags |= SNOR_F_4B_OPCODES;
 285         /* No small sector erase for 4-byte command set */
 286         nor->erase_opcode = SPINOR_OP_SE;
 287         nor->mtd.erasesize = nor->info->sector_size;
 288 }
 289
 290 static const struct spi_nor_fixups spansion_fixups = {
 291         .post_sfdp = spansion_post_sfdp_fixups,
 292 };
 293
 294 const struct spi_nor_manufacturer spi_nor_spansion = {
 295         .name = "spansion",
 296         .parts = spansion_parts,
 297         .nparts = ARRAY_SIZE(spansion_parts),
 298         .fixups = &spansion_fixups,
 299 };