2 * Intel PCH/PCU SPI flash driver.
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/sizes.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/mtd/spi-nor.h>
21 #include <linux/platform_data/intel-spi.h>
23 #include "intel-spi.h"
25 /* Offsets are from @ispi->base */
28 #define HSFSTS_CTL 0x04
29 #define HSFSTS_CTL_FSMIE BIT(31)
30 #define HSFSTS_CTL_FDBC_SHIFT 24
31 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
33 #define HSFSTS_CTL_FCYCLE_SHIFT 17
34 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
35 /* HW sequencer opcodes */
36 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
39 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
40 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
41 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
42 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
44 #define HSFSTS_CTL_FGO BIT(16)
45 #define HSFSTS_CTL_FLOCKDN BIT(15)
46 #define HSFSTS_CTL_FDV BIT(14)
47 #define HSFSTS_CTL_SCIP BIT(5)
48 #define HSFSTS_CTL_AEL BIT(2)
49 #define HSFSTS_CTL_FCERR BIT(1)
50 #define HSFSTS_CTL_FDONE BIT(0)
54 #define FDATA(n) (0x10 + ((n) * 4))
58 #define FREG(n) (0x54 + ((n) * 4))
59 #define FREG_BASE_MASK 0x3fff
60 #define FREG_LIMIT_SHIFT 16
61 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
63 /* Offset is from @ispi->pregs */
64 #define PR(n) ((n) * 4)
65 #define PR_WPE BIT(31)
66 #define PR_LIMIT_SHIFT 16
67 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
68 #define PR_RPE BIT(15)
69 #define PR_BASE_MASK 0x3fff
71 #define PR_NUM (5 + 1)
73 /* Offsets are from @ispi->sregs */
74 #define SSFSTS_CTL 0x00
75 #define SSFSTS_CTL_FSMIE BIT(23)
76 #define SSFSTS_CTL_DS BIT(22)
77 #define SSFSTS_CTL_DBC_SHIFT 16
78 #define SSFSTS_CTL_SPOP BIT(11)
79 #define SSFSTS_CTL_ACS BIT(10)
80 #define SSFSTS_CTL_SCGO BIT(9)
81 #define SSFSTS_CTL_COP_SHIFT 12
82 #define SSFSTS_CTL_FRS BIT(7)
83 #define SSFSTS_CTL_DOFRS BIT(6)
84 #define SSFSTS_CTL_AEL BIT(4)
85 #define SSFSTS_CTL_FCERR BIT(3)
86 #define SSFSTS_CTL_FDONE BIT(2)
87 #define SSFSTS_CTL_SCIP BIT(0)
89 #define PREOP_OPTYPE 0x04
95 #define BYT_SSFSTS_CTL 0x90
97 #define BYT_BCR_WPD BIT(0)
98 #define BYT_FREG_NUM 5
101 #define LPT_SSFSTS_CTL 0x90
102 #define LPT_FREG_NUM 5
105 #define BXT_SSFSTS_CTL 0xa0
106 #define BXT_FREG_NUM 12
108 #define INTEL_SPI_TIMEOUT 5000 /* ms */
109 #define INTEL_SPI_FIFO_SZ 64
112 * struct intel_spi - Driver private data
113 * @dev: Device pointer
114 * @info: Pointer to board specific info
115 * @nor: SPI NOR layer structure
116 * @base: Beginning of MMIO space
117 * @pregs: Start of protection registers
118 * @sregs: Start of software sequencer registers
119 * @nregions: Maximum number of regions
120 * @writeable: Is the chip writeable
121 * @swseq: Use SW sequencer in register reads/writes
122 * @erase_64k: 64k erase supported
123 * @opcodes: Opcodes which are supported. This are programmed by BIOS
124 * before it locks down the controller.
125 * @preopcodes: Preopcodes which are supported.
129 const struct intel_spi_boardinfo *info;
142 static bool writeable;
143 module_param(writeable, bool, 0);
144 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
146 static void intel_spi_dump_regs(struct intel_spi *ispi)
151 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
153 value = readl(ispi->base + HSFSTS_CTL);
154 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
155 if (value & HSFSTS_CTL_FLOCKDN)
156 dev_dbg(ispi->dev, "-> Locked\n");
158 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
159 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
161 for (i = 0; i < 16; i++)
162 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
163 i, readl(ispi->base + FDATA(i)));
165 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
167 for (i = 0; i < ispi->nregions; i++)
168 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
169 readl(ispi->base + FREG(i)));
170 for (i = 0; i < PR_NUM; i++)
171 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
172 readl(ispi->pregs + PR(i)));
174 value = readl(ispi->sregs + SSFSTS_CTL);
175 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
176 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
177 readl(ispi->sregs + PREOP_OPTYPE));
178 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
179 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
181 if (ispi->info->type == INTEL_SPI_BYT)
182 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
184 dev_dbg(ispi->dev, "Protected regions:\n");
185 for (i = 0; i < PR_NUM; i++) {
188 value = readl(ispi->pregs + PR(i));
189 if (!(value & (PR_WPE | PR_RPE)))
192 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
193 base = value & PR_BASE_MASK;
195 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
196 i, base << 12, (limit << 12) | 0xfff,
197 value & PR_WPE ? 'W' : '.',
198 value & PR_RPE ? 'R' : '.');
201 dev_dbg(ispi->dev, "Flash regions:\n");
202 for (i = 0; i < ispi->nregions; i++) {
203 u32 region, base, limit;
205 region = readl(ispi->base + FREG(i));
206 base = region & FREG_BASE_MASK;
207 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
209 if (base >= limit || (i > 0 && limit == 0))
210 dev_dbg(ispi->dev, " %02d disabled\n", i);
212 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
213 i, base << 12, (limit << 12) | 0xfff);
216 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
217 ispi->swseq ? 'S' : 'H');
220 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
221 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
226 if (size > INTEL_SPI_FIFO_SZ)
230 bytes = min_t(size_t, size, 4);
231 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
240 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
241 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
247 if (size > INTEL_SPI_FIFO_SZ)
251 bytes = min_t(size_t, size, 4);
252 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
261 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
265 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
266 !(val & HSFSTS_CTL_SCIP), 0,
267 INTEL_SPI_TIMEOUT * 1000);
270 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
274 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
275 !(val & SSFSTS_CTL_SCIP), 0,
276 INTEL_SPI_TIMEOUT * 1000);
279 static int intel_spi_init(struct intel_spi *ispi)
281 u32 opmenu0, opmenu1, val;
284 switch (ispi->info->type) {
286 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
287 ispi->pregs = ispi->base + BYT_PR;
288 ispi->nregions = BYT_FREG_NUM;
291 /* Disable write protection */
292 val = readl(ispi->base + BYT_BCR);
293 if (!(val & BYT_BCR_WPD)) {
295 writel(val, ispi->base + BYT_BCR);
296 val = readl(ispi->base + BYT_BCR);
299 ispi->writeable = !!(val & BYT_BCR_WPD);
305 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
306 ispi->pregs = ispi->base + LPT_PR;
307 ispi->nregions = LPT_FREG_NUM;
311 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
312 ispi->pregs = ispi->base + BXT_PR;
313 ispi->nregions = BXT_FREG_NUM;
314 ispi->erase_64k = true;
321 /* Disable #SMI generation */
322 val = readl(ispi->base + HSFSTS_CTL);
323 val &= ~HSFSTS_CTL_FSMIE;
324 writel(val, ispi->base + HSFSTS_CTL);
327 * BIOS programs allowed opcodes and then locks down the register.
328 * So read back what opcodes it decided to support. That's the set
329 * we are going to support as well.
331 opmenu0 = readl(ispi->sregs + OPMENU0);
332 opmenu1 = readl(ispi->sregs + OPMENU1);
335 * Some controllers can only do basic operations using hardware
336 * sequencer. All other operations are supposed to be carried out
337 * using software sequencer. If we find that BIOS has programmed
338 * opcodes for the software sequencer we use that over the hardware
341 if (opmenu0 && opmenu1) {
342 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
343 ispi->opcodes[i] = opmenu0 >> i * 8;
344 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
347 val = readl(ispi->sregs + PREOP_OPTYPE);
348 ispi->preopcodes[0] = val;
349 ispi->preopcodes[1] = val >> 8;
351 /* Disable #SMI generation from SW sequencer */
352 val = readl(ispi->sregs + SSFSTS_CTL);
353 val &= ~SSFSTS_CTL_FSMIE;
354 writel(val, ispi->sregs + SSFSTS_CTL);
359 intel_spi_dump_regs(ispi);
364 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode)
368 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
369 if (ispi->opcodes[i] == opcode)
374 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
380 val = readl(ispi->base + HSFSTS_CTL);
381 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
385 val |= HSFSTS_CTL_FCYCLE_RDID;
388 val |= HSFSTS_CTL_FCYCLE_WRSR;
391 val |= HSFSTS_CTL_FCYCLE_RDSR;
397 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
398 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
399 val |= HSFSTS_CTL_FGO;
400 writel(val, ispi->base + HSFSTS_CTL);
402 ret = intel_spi_wait_hw_busy(ispi);
406 status = readl(ispi->base + HSFSTS_CTL);
407 if (status & HSFSTS_CTL_FCERR)
409 else if (status & HSFSTS_CTL_AEL)
415 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf,
421 ret = intel_spi_opcode_index(ispi, opcode);
425 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
426 val |= ret << SSFSTS_CTL_COP_SHIFT;
427 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
428 val |= SSFSTS_CTL_SCGO;
429 writel(val, ispi->sregs + SSFSTS_CTL);
431 ret = intel_spi_wait_sw_busy(ispi);
435 status = readl(ispi->sregs + SSFSTS_CTL);
436 if (status & SSFSTS_CTL_FCERR)
438 else if (status & SSFSTS_CTL_AEL)
444 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
446 struct intel_spi *ispi = nor->priv;
449 /* Address of the first chip */
450 writel(0, ispi->base + FADDR);
453 ret = intel_spi_sw_cycle(ispi, opcode, buf, len);
455 ret = intel_spi_hw_cycle(ispi, opcode, buf, len);
460 return intel_spi_read_block(ispi, buf, len);
463 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
465 struct intel_spi *ispi = nor->priv;
469 * This is handled with atomic operation and preop code in Intel
470 * controller so skip it here now.
472 if (opcode == SPINOR_OP_WREN)
475 writel(0, ispi->base + FADDR);
477 /* Write the value beforehand */
478 ret = intel_spi_write_block(ispi, buf, len);
483 return intel_spi_sw_cycle(ispi, opcode, buf, len);
484 return intel_spi_hw_cycle(ispi, opcode, buf, len);
487 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
490 struct intel_spi *ispi = nor->priv;
491 size_t block_size, retlen = 0;
495 switch (nor->read_opcode) {
497 case SPINOR_OP_READ_FAST:
504 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
506 /* Read cannot cross 4K boundary */
507 block_size = min_t(loff_t, from + block_size,
508 round_up(from + 1, SZ_4K)) - from;
510 writel(from, ispi->base + FADDR);
512 val = readl(ispi->base + HSFSTS_CTL);
513 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
514 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
515 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
516 val |= HSFSTS_CTL_FCYCLE_READ;
517 val |= HSFSTS_CTL_FGO;
518 writel(val, ispi->base + HSFSTS_CTL);
520 ret = intel_spi_wait_hw_busy(ispi);
524 status = readl(ispi->base + HSFSTS_CTL);
525 if (status & HSFSTS_CTL_FCERR)
527 else if (status & HSFSTS_CTL_AEL)
531 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
536 ret = intel_spi_read_block(ispi, read_buf, block_size);
542 retlen += block_size;
543 read_buf += block_size;
549 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
550 const u_char *write_buf)
552 struct intel_spi *ispi = nor->priv;
553 size_t block_size, retlen = 0;
558 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
560 /* Write cannot cross 4K boundary */
561 block_size = min_t(loff_t, to + block_size,
562 round_up(to + 1, SZ_4K)) - to;
564 writel(to, ispi->base + FADDR);
566 val = readl(ispi->base + HSFSTS_CTL);
567 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
568 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
569 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
570 val |= HSFSTS_CTL_FCYCLE_WRITE;
573 if (ispi->preopcodes[1] == SPINOR_OP_WREN)
574 val |= SSFSTS_CTL_SPOP;
575 val |= SSFSTS_CTL_ACS;
576 writel(val, ispi->base + HSFSTS_CTL);
578 ret = intel_spi_write_block(ispi, write_buf, block_size);
580 dev_err(ispi->dev, "failed to write block\n");
584 /* Start the write now */
585 val = readl(ispi->base + HSFSTS_CTL);
586 writel(val | HSFSTS_CTL_FGO, ispi->base + HSFSTS_CTL);
588 ret = intel_spi_wait_hw_busy(ispi);
590 dev_err(ispi->dev, "timeout\n");
594 status = readl(ispi->base + HSFSTS_CTL);
595 if (status & HSFSTS_CTL_FCERR)
597 else if (status & HSFSTS_CTL_AEL)
601 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
608 retlen += block_size;
609 write_buf += block_size;
615 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
617 size_t erase_size, len = nor->mtd.erasesize;
618 struct intel_spi *ispi = nor->priv;
619 u32 val, status, cmd;
622 /* If the hardware can do 64k erase use that when possible */
623 if (len >= SZ_64K && ispi->erase_64k) {
624 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
627 cmd = HSFSTS_CTL_FCYCLE_ERASE;
632 writel(offs, ispi->base + FADDR);
634 val = readl(ispi->base + HSFSTS_CTL);
635 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
636 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
638 val |= HSFSTS_CTL_FGO;
639 writel(val, ispi->base + HSFSTS_CTL);
641 ret = intel_spi_wait_hw_busy(ispi);
645 status = readl(ispi->base + HSFSTS_CTL);
646 if (status & HSFSTS_CTL_FCERR)
648 else if (status & HSFSTS_CTL_AEL)
658 static bool intel_spi_is_protected(const struct intel_spi *ispi,
659 unsigned int base, unsigned int limit)
663 for (i = 0; i < PR_NUM; i++) {
664 u32 pr_base, pr_limit, pr_value;
666 pr_value = readl(ispi->pregs + PR(i));
667 if (!(pr_value & (PR_WPE | PR_RPE)))
670 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
671 pr_base = pr_value & PR_BASE_MASK;
673 if (pr_base >= base && pr_limit <= limit)
681 * There will be a single partition holding all enabled flash regions. We
684 static void intel_spi_fill_partition(struct intel_spi *ispi,
685 struct mtd_partition *part)
690 memset(part, 0, sizeof(*part));
692 /* Start from the mandatory descriptor region */
697 * Now try to find where this partition ends based on the flash
700 for (i = 1; i < ispi->nregions; i++) {
701 u32 region, base, limit;
703 region = readl(ispi->base + FREG(i));
704 base = region & FREG_BASE_MASK;
705 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
707 if (base >= limit || limit == 0)
711 * If any of the regions have protection bits set, make the
712 * whole partition read-only to be on the safe side.
714 if (intel_spi_is_protected(ispi, base, limit))
715 ispi->writeable = false;
717 end = (limit << 12) + 4096;
718 if (end > part->size)
723 struct intel_spi *intel_spi_probe(struct device *dev,
724 struct resource *mem, const struct intel_spi_boardinfo *info)
726 const struct spi_nor_hwcaps hwcaps = {
727 .mask = SNOR_HWCAPS_READ |
728 SNOR_HWCAPS_READ_FAST |
731 struct mtd_partition part;
732 struct intel_spi *ispi;
736 return ERR_PTR(-EINVAL);
738 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
740 return ERR_PTR(-ENOMEM);
742 ispi->base = devm_ioremap_resource(dev, mem);
743 if (IS_ERR(ispi->base))
744 return ERR_CAST(ispi->base);
748 ispi->writeable = info->writeable;
750 ret = intel_spi_init(ispi);
754 ispi->nor.dev = ispi->dev;
755 ispi->nor.priv = ispi;
756 ispi->nor.read_reg = intel_spi_read_reg;
757 ispi->nor.write_reg = intel_spi_write_reg;
758 ispi->nor.read = intel_spi_read;
759 ispi->nor.write = intel_spi_write;
760 ispi->nor.erase = intel_spi_erase;
762 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
764 dev_info(dev, "failed to locate the chip\n");
768 intel_spi_fill_partition(ispi, &part);
770 /* Prevent writes if not explicitly enabled */
771 if (!ispi->writeable || !writeable)
772 ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
774 ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, &part, 1);
780 EXPORT_SYMBOL_GPL(intel_spi_probe);
782 int intel_spi_remove(struct intel_spi *ispi)
784 return mtd_device_unregister(&ispi->nor.mtd);
786 EXPORT_SYMBOL_GPL(intel_spi_remove);
788 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
789 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
790 MODULE_LICENSE("GPL v2");