1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/of_platform.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
27 /* Define max times to check status register before we give up. */
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
44 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
46 * @nor: pointer to 'struct spi_nor'
47 * @op: pointer to 'struct spi_mem_op' template for transfer
49 * If we have to use the bounce buffer, the data field in @op will be updated.
51 * Return: true if the bounce buffer is needed, false if not
53 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
55 /* op->data.buf.in occupies the same memory as op->data.buf.out */
56 if (object_is_on_stack(op->data.buf.in) ||
57 !virt_addr_valid(op->data.buf.in)) {
58 if (op->data.nbytes > nor->bouncebuf_size)
59 op->data.nbytes = nor->bouncebuf_size;
60 op->data.buf.in = nor->bouncebuf;
68 * spi_nor_spimem_exec_op() - execute a memory operation
69 * @nor: pointer to 'struct spi_nor'
70 * @op: pointer to 'struct spi_mem_op' template for transfer
72 * Return: 0 on success, -error otherwise.
74 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
78 error = spi_mem_adjust_op_size(nor->spimem, op);
82 return spi_mem_exec_op(nor->spimem, op);
86 * spi_nor_spimem_read_data() - read data from flash's memory region via
88 * @nor: pointer to 'struct spi_nor'
89 * @from: offset to read from
90 * @len: number of bytes to read
91 * @buf: pointer to dst buffer
93 * Return: number of bytes read successfully, -errno otherwise
95 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
98 struct spi_mem_op op =
99 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
100 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
101 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
102 SPI_MEM_OP_DATA_IN(len, buf, 1));
107 /* get transfer protocols. */
108 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
109 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
110 op.dummy.buswidth = op.addr.buswidth;
111 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
113 /* convert the dummy cycles to the number of bytes */
114 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
116 usebouncebuf = spi_nor_spimem_bounce(nor, &op);
118 if (nor->dirmap.rdesc) {
119 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
120 op.data.nbytes, op.data.buf.in);
122 error = spi_nor_spimem_exec_op(nor, &op);
125 nbytes = op.data.nbytes;
128 if (usebouncebuf && nbytes > 0)
129 memcpy(buf, op.data.buf.in, nbytes);
135 * spi_nor_read_data() - read data from flash memory
136 * @nor: pointer to 'struct spi_nor'
137 * @from: offset to read from
138 * @len: number of bytes to read
139 * @buf: pointer to dst buffer
141 * Return: number of bytes read successfully, -errno otherwise
143 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
146 return spi_nor_spimem_read_data(nor, from, len, buf);
148 return nor->controller_ops->read(nor, from, len, buf);
152 * spi_nor_spimem_write_data() - write data to flash memory via
154 * @nor: pointer to 'struct spi_nor'
155 * @to: offset to write to
156 * @len: number of bytes to write
157 * @buf: pointer to src buffer
159 * Return: number of bytes written successfully, -errno otherwise
161 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
162 size_t len, const u8 *buf)
164 struct spi_mem_op op =
165 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
166 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
168 SPI_MEM_OP_DATA_OUT(len, buf, 1));
172 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
173 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
174 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
176 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
179 if (spi_nor_spimem_bounce(nor, &op))
180 memcpy(nor->bouncebuf, buf, op.data.nbytes);
182 if (nor->dirmap.wdesc) {
183 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
184 op.data.nbytes, op.data.buf.out);
186 error = spi_nor_spimem_exec_op(nor, &op);
189 nbytes = op.data.nbytes;
196 * spi_nor_write_data() - write data to flash memory
197 * @nor: pointer to 'struct spi_nor'
198 * @to: offset to write to
199 * @len: number of bytes to write
200 * @buf: pointer to src buffer
202 * Return: number of bytes written successfully, -errno otherwise
204 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
208 return spi_nor_spimem_write_data(nor, to, len, buf);
210 return nor->controller_ops->write(nor, to, len, buf);
214 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
215 * @nor: pointer to 'struct spi_nor'.
217 * Return: 0 on success, -errno otherwise.
219 int spi_nor_write_enable(struct spi_nor *nor)
224 struct spi_mem_op op =
225 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
230 ret = spi_mem_exec_op(nor->spimem, &op);
232 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
237 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
243 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
244 * @nor: pointer to 'struct spi_nor'.
246 * Return: 0 on success, -errno otherwise.
248 int spi_nor_write_disable(struct spi_nor *nor)
253 struct spi_mem_op op =
254 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
259 ret = spi_mem_exec_op(nor->spimem, &op);
261 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
266 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
272 * spi_nor_read_sr() - Read the Status Register.
273 * @nor: pointer to 'struct spi_nor'.
274 * @sr: pointer to a DMA-able buffer where the value of the
275 * Status Register will be written.
277 * Return: 0 on success, -errno otherwise.
279 static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
284 struct spi_mem_op op =
285 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
288 SPI_MEM_OP_DATA_IN(1, sr, 1));
290 ret = spi_mem_exec_op(nor->spimem, &op);
292 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
297 dev_dbg(nor->dev, "error %d reading SR\n", ret);
303 * spi_nor_read_fsr() - Read the Flag Status Register.
304 * @nor: pointer to 'struct spi_nor'
305 * @fsr: pointer to a DMA-able buffer where the value of the
306 * Flag Status Register will be written.
308 * Return: 0 on success, -errno otherwise.
310 static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
315 struct spi_mem_op op =
316 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
319 SPI_MEM_OP_DATA_IN(1, fsr, 1));
321 ret = spi_mem_exec_op(nor->spimem, &op);
323 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
328 dev_dbg(nor->dev, "error %d reading FSR\n", ret);
334 * spi_nor_read_cr() - Read the Configuration Register using the
335 * SPINOR_OP_RDCR (35h) command.
336 * @nor: pointer to 'struct spi_nor'
337 * @cr: pointer to a DMA-able buffer where the value of the
338 * Configuration Register will be written.
340 * Return: 0 on success, -errno otherwise.
342 static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
347 struct spi_mem_op op =
348 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
351 SPI_MEM_OP_DATA_IN(1, cr, 1));
353 ret = spi_mem_exec_op(nor->spimem, &op);
355 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
359 dev_dbg(nor->dev, "error %d reading CR\n", ret);
365 * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode.
366 * @nor: pointer to 'struct spi_nor'.
367 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
370 * Return: 0 on success, -errno otherwise.
372 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
377 struct spi_mem_op op =
378 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
386 ret = spi_mem_exec_op(nor->spimem, &op);
388 ret = nor->controller_ops->write_reg(nor,
389 enable ? SPINOR_OP_EN4B :
395 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
401 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
403 * @nor: pointer to 'struct spi_nor'.
404 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
407 * Return: 0 on success, -errno otherwise.
409 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
413 nor->bouncebuf[0] = enable << 7;
416 struct spi_mem_op op =
417 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1),
420 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
422 ret = spi_mem_exec_op(nor->spimem, &op);
424 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
429 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
435 * spi_nor_write_ear() - Write Extended Address Register.
436 * @nor: pointer to 'struct spi_nor'.
437 * @ear: value to write to the Extended Address Register.
439 * Return: 0 on success, -errno otherwise.
441 int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
445 nor->bouncebuf[0] = ear;
448 struct spi_mem_op op =
449 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1),
452 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
454 ret = spi_mem_exec_op(nor->spimem, &op);
456 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
461 dev_dbg(nor->dev, "error %d writing EAR\n", ret);
467 * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
468 * @nor: pointer to 'struct spi_nor'.
469 * @sr: pointer to a DMA-able buffer where the value of the
470 * Status Register will be written.
472 * Return: 0 on success, -errno otherwise.
474 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
479 struct spi_mem_op op =
480 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
483 SPI_MEM_OP_DATA_IN(1, sr, 1));
485 ret = spi_mem_exec_op(nor->spimem, &op);
487 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
492 dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
498 * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
499 * the flash is ready for new commands.
500 * @nor: pointer to 'struct spi_nor'.
502 * Return: 1 if ready, 0 if not ready, -errno on errors.
504 static int spi_nor_xsr_ready(struct spi_nor *nor)
508 ret = spi_nor_xread_sr(nor, nor->bouncebuf);
512 return !!(nor->bouncebuf[0] & XSR_RDY);
516 * spi_nor_clear_sr() - Clear the Status Register.
517 * @nor: pointer to 'struct spi_nor'.
519 static void spi_nor_clear_sr(struct spi_nor *nor)
524 struct spi_mem_op op =
525 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
530 ret = spi_mem_exec_op(nor->spimem, &op);
532 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
537 dev_dbg(nor->dev, "error %d clearing SR\n", ret);
541 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
543 * @nor: pointer to 'struct spi_nor'.
545 * Return: 1 if ready, 0 if not ready, -errno on errors.
547 static int spi_nor_sr_ready(struct spi_nor *nor)
549 int ret = spi_nor_read_sr(nor, nor->bouncebuf);
554 if (nor->flags & SNOR_F_USE_CLSR &&
555 nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
556 if (nor->bouncebuf[0] & SR_E_ERR)
557 dev_err(nor->dev, "Erase Error occurred\n");
559 dev_err(nor->dev, "Programming Error occurred\n");
561 spi_nor_clear_sr(nor);
564 * WEL bit remains set to one when an erase or page program
565 * error occurs. Issue a Write Disable command to protect
566 * against inadvertent writes that can possibly corrupt the
567 * contents of the memory.
569 ret = spi_nor_write_disable(nor);
576 return !(nor->bouncebuf[0] & SR_WIP);
580 * spi_nor_clear_fsr() - Clear the Flag Status Register.
581 * @nor: pointer to 'struct spi_nor'.
583 static void spi_nor_clear_fsr(struct spi_nor *nor)
588 struct spi_mem_op op =
589 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
594 ret = spi_mem_exec_op(nor->spimem, &op);
596 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
601 dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
605 * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
606 * ready for new commands.
607 * @nor: pointer to 'struct spi_nor'.
609 * Return: 1 if ready, 0 if not ready, -errno on errors.
611 static int spi_nor_fsr_ready(struct spi_nor *nor)
613 int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
618 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
619 if (nor->bouncebuf[0] & FSR_E_ERR)
620 dev_err(nor->dev, "Erase operation failed.\n");
622 dev_err(nor->dev, "Program operation failed.\n");
624 if (nor->bouncebuf[0] & FSR_PT_ERR)
626 "Attempted to modify a protected sector.\n");
628 spi_nor_clear_fsr(nor);
631 * WEL bit remains set to one when an erase or page program
632 * error occurs. Issue a Write Disable command to protect
633 * against inadvertent writes that can possibly corrupt the
634 * contents of the memory.
636 ret = spi_nor_write_disable(nor);
643 return !!(nor->bouncebuf[0] & FSR_READY);
647 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
648 * @nor: pointer to 'struct spi_nor'.
650 * Return: 1 if ready, 0 if not ready, -errno on errors.
652 static int spi_nor_ready(struct spi_nor *nor)
656 if (nor->flags & SNOR_F_READY_XSR_RDY)
657 sr = spi_nor_xsr_ready(nor);
659 sr = spi_nor_sr_ready(nor);
662 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
669 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
670 * Status Register until ready, or timeout occurs.
671 * @nor: pointer to "struct spi_nor".
672 * @timeout_jiffies: jiffies to wait until timeout.
674 * Return: 0 on success, -errno otherwise.
676 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
677 unsigned long timeout_jiffies)
679 unsigned long deadline;
680 int timeout = 0, ret;
682 deadline = jiffies + timeout_jiffies;
685 if (time_after_eq(jiffies, deadline))
688 ret = spi_nor_ready(nor);
697 dev_dbg(nor->dev, "flash operation timed out\n");
703 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
704 * flash to be ready, or timeout occurs.
705 * @nor: pointer to "struct spi_nor".
707 * Return: 0 on success, -errno otherwise.
709 int spi_nor_wait_till_ready(struct spi_nor *nor)
711 return spi_nor_wait_till_ready_with_timeout(nor,
712 DEFAULT_READY_WAIT_JIFFIES);
716 * spi_nor_write_sr() - Write the Status Register.
717 * @nor: pointer to 'struct spi_nor'.
718 * @sr: pointer to DMA-able buffer to write to the Status Register.
719 * @len: number of bytes to write to the Status Register.
721 * Return: 0 on success, -errno otherwise.
723 static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
727 ret = spi_nor_write_enable(nor);
732 struct spi_mem_op op =
733 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
736 SPI_MEM_OP_DATA_OUT(len, sr, 1));
738 ret = spi_mem_exec_op(nor->spimem, &op);
740 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
745 dev_dbg(nor->dev, "error %d writing SR\n", ret);
749 return spi_nor_wait_till_ready(nor);
753 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
754 * ensure that the byte written match the received value.
755 * @nor: pointer to a 'struct spi_nor'.
756 * @sr1: byte value to be written to the Status Register.
758 * Return: 0 on success, -errno otherwise.
760 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
764 nor->bouncebuf[0] = sr1;
766 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
770 ret = spi_nor_read_sr(nor, nor->bouncebuf);
774 if (nor->bouncebuf[0] != sr1) {
775 dev_dbg(nor->dev, "SR1: read back test failed\n");
783 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
784 * Status Register 2 in one shot. Ensure that the byte written in the Status
785 * Register 1 match the received value, and that the 16-bit Write did not
786 * affect what was already in the Status Register 2.
787 * @nor: pointer to a 'struct spi_nor'.
788 * @sr1: byte value to be written to the Status Register 1.
790 * Return: 0 on success, -errno otherwise.
792 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
795 u8 *sr_cr = nor->bouncebuf;
798 /* Make sure we don't overwrite the contents of Status Register 2. */
799 if (!(nor->flags & SNOR_F_NO_READ_CR)) {
800 ret = spi_nor_read_cr(nor, &sr_cr[1]);
803 } else if (nor->params->quad_enable) {
805 * If the Status Register 2 Read command (35h) is not
806 * supported, we should at least be sure we don't
807 * change the value of the SR2 Quad Enable bit.
809 * We can safely assume that when the Quad Enable method is
810 * set, the value of the QE bit is one, as a consequence of the
811 * nor->params->quad_enable() call.
813 * We can safely assume that the Quad Enable bit is present in
814 * the Status Register 2 at BIT(1). According to the JESD216
815 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
816 * Write Status (01h) command is available just for the cases
817 * in which the QE bit is described in SR2 at BIT(1).
819 sr_cr[1] = SR2_QUAD_EN_BIT1;
826 ret = spi_nor_write_sr(nor, sr_cr, 2);
830 ret = spi_nor_read_sr(nor, sr_cr);
834 if (sr1 != sr_cr[0]) {
835 dev_dbg(nor->dev, "SR: Read back test failed\n");
839 if (nor->flags & SNOR_F_NO_READ_CR)
842 cr_written = sr_cr[1];
844 ret = spi_nor_read_cr(nor, &sr_cr[1]);
848 if (cr_written != sr_cr[1]) {
849 dev_dbg(nor->dev, "CR: read back test failed\n");
857 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
858 * Configuration Register in one shot. Ensure that the byte written in the
859 * Configuration Register match the received value, and that the 16-bit Write
860 * did not affect what was already in the Status Register 1.
861 * @nor: pointer to a 'struct spi_nor'.
862 * @cr: byte value to be written to the Configuration Register.
864 * Return: 0 on success, -errno otherwise.
866 static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
869 u8 *sr_cr = nor->bouncebuf;
872 /* Keep the current value of the Status Register 1. */
873 ret = spi_nor_read_sr(nor, sr_cr);
879 ret = spi_nor_write_sr(nor, sr_cr, 2);
883 sr_written = sr_cr[0];
885 ret = spi_nor_read_sr(nor, sr_cr);
889 if (sr_written != sr_cr[0]) {
890 dev_dbg(nor->dev, "SR: Read back test failed\n");
894 if (nor->flags & SNOR_F_NO_READ_CR)
897 ret = spi_nor_read_cr(nor, &sr_cr[1]);
901 if (cr != sr_cr[1]) {
902 dev_dbg(nor->dev, "CR: read back test failed\n");
910 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
911 * the byte written match the received value without affecting other bits in the
912 * Status Register 1 and 2.
913 * @nor: pointer to a 'struct spi_nor'.
914 * @sr1: byte value to be written to the Status Register.
916 * Return: 0 on success, -errno otherwise.
918 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
920 if (nor->flags & SNOR_F_HAS_16BIT_SR)
921 return spi_nor_write_16bit_sr_and_check(nor, sr1);
923 return spi_nor_write_sr1_and_check(nor, sr1);
927 * spi_nor_write_sr2() - Write the Status Register 2 using the
928 * SPINOR_OP_WRSR2 (3eh) command.
929 * @nor: pointer to 'struct spi_nor'.
930 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
932 * Return: 0 on success, -errno otherwise.
934 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
938 ret = spi_nor_write_enable(nor);
943 struct spi_mem_op op =
944 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
947 SPI_MEM_OP_DATA_OUT(1, sr2, 1));
949 ret = spi_mem_exec_op(nor->spimem, &op);
951 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
956 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
960 return spi_nor_wait_till_ready(nor);
964 * spi_nor_read_sr2() - Read the Status Register 2 using the
965 * SPINOR_OP_RDSR2 (3fh) command.
966 * @nor: pointer to 'struct spi_nor'.
967 * @sr2: pointer to DMA-able buffer where the value of the
968 * Status Register 2 will be written.
970 * Return: 0 on success, -errno otherwise.
972 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
977 struct spi_mem_op op =
978 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
981 SPI_MEM_OP_DATA_IN(1, sr2, 1));
983 ret = spi_mem_exec_op(nor->spimem, &op);
985 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
990 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
996 * spi_nor_erase_chip() - Erase the entire flash memory.
997 * @nor: pointer to 'struct spi_nor'.
999 * Return: 0 on success, -errno otherwise.
1001 static int spi_nor_erase_chip(struct spi_nor *nor)
1005 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
1008 struct spi_mem_op op =
1009 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1),
1011 SPI_MEM_OP_NO_DUMMY,
1012 SPI_MEM_OP_NO_DATA);
1014 ret = spi_mem_exec_op(nor->spimem, &op);
1016 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
1021 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1026 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1030 for (i = 0; i < size; i++)
1031 if (table[i][0] == opcode)
1034 /* No conversion found, keep input op code. */
1038 u8 spi_nor_convert_3to4_read(u8 opcode)
1040 static const u8 spi_nor_3to4_read[][2] = {
1041 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1042 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1043 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1044 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1045 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1046 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1047 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1048 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1050 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1051 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1052 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1055 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1056 ARRAY_SIZE(spi_nor_3to4_read));
1059 static u8 spi_nor_convert_3to4_program(u8 opcode)
1061 static const u8 spi_nor_3to4_program[][2] = {
1062 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1063 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1064 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1065 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1066 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1069 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1070 ARRAY_SIZE(spi_nor_3to4_program));
1073 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1075 static const u8 spi_nor_3to4_erase[][2] = {
1076 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1077 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1078 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1081 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1082 ARRAY_SIZE(spi_nor_3to4_erase));
1085 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1087 return !!nor->params->erase_map.uniform_erase_type;
1090 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1092 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1093 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1094 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1096 if (!spi_nor_has_uniform_erase(nor)) {
1097 struct spi_nor_erase_map *map = &nor->params->erase_map;
1098 struct spi_nor_erase_type *erase;
1101 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1102 erase = &map->erase_type[i];
1104 spi_nor_convert_3to4_erase(erase->opcode);
1109 int spi_nor_lock_and_prep(struct spi_nor *nor)
1113 mutex_lock(&nor->lock);
1115 if (nor->controller_ops && nor->controller_ops->prepare) {
1116 ret = nor->controller_ops->prepare(nor);
1118 mutex_unlock(&nor->lock);
1125 void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1127 if (nor->controller_ops && nor->controller_ops->unprepare)
1128 nor->controller_ops->unprepare(nor);
1129 mutex_unlock(&nor->lock);
1132 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1134 if (!nor->params->convert_addr)
1137 return nor->params->convert_addr(nor, addr);
1141 * Initiate the erasure of a single sector
1143 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1147 addr = spi_nor_convert_addr(nor, addr);
1150 struct spi_mem_op op =
1151 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
1152 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
1153 SPI_MEM_OP_NO_DUMMY,
1154 SPI_MEM_OP_NO_DATA);
1156 return spi_mem_exec_op(nor->spimem, &op);
1157 } else if (nor->controller_ops->erase) {
1158 return nor->controller_ops->erase(nor, addr);
1162 * Default implementation, if driver doesn't have a specialized HW
1165 for (i = nor->addr_width - 1; i >= 0; i--) {
1166 nor->bouncebuf[i] = addr & 0xff;
1170 return nor->controller_ops->write_reg(nor, nor->erase_opcode,
1171 nor->bouncebuf, nor->addr_width);
1175 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1176 * @erase: pointer to a structure that describes a SPI NOR erase type
1177 * @dividend: dividend value
1178 * @remainder: pointer to u32 remainder (will be updated)
1180 * Return: the result of the division
1182 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1183 u64 dividend, u32 *remainder)
1185 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1186 *remainder = (u32)dividend & erase->size_mask;
1187 return dividend >> erase->size_shift;
1191 * spi_nor_find_best_erase_type() - find the best erase type for the given
1192 * offset in the serial flash memory and the
1193 * number of bytes to erase. The region in
1194 * which the address fits is expected to be
1196 * @map: the erase map of the SPI NOR
1197 * @region: pointer to a structure that describes a SPI NOR erase region
1198 * @addr: offset in the serial flash memory
1199 * @len: number of bytes to erase
1201 * Return: a pointer to the best fitted erase type, NULL otherwise.
1203 static const struct spi_nor_erase_type *
1204 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1205 const struct spi_nor_erase_region *region,
1208 const struct spi_nor_erase_type *erase;
1211 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1214 * Erase types are ordered by size, with the smallest erase type at
1217 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1218 /* Does the erase region support the tested erase type? */
1219 if (!(erase_mask & BIT(i)))
1222 erase = &map->erase_type[i];
1224 /* Alignment is not mandatory for overlaid regions */
1225 if (region->offset & SNOR_OVERLAID_REGION &&
1226 region->size <= len)
1229 /* Don't erase more than what the user has asked for. */
1230 if (erase->size > len)
1233 spi_nor_div_by_erase_size(erase, addr, &rem);
1243 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1245 return region->offset & SNOR_LAST_REGION;
1248 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1250 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1254 * spi_nor_region_next() - get the next spi nor region
1255 * @region: pointer to a structure that describes a SPI NOR erase region
1257 * Return: the next spi nor region or NULL if last region.
1259 struct spi_nor_erase_region *
1260 spi_nor_region_next(struct spi_nor_erase_region *region)
1262 if (spi_nor_region_is_last(region))
1269 * spi_nor_find_erase_region() - find the region of the serial flash memory in
1270 * which the offset fits
1271 * @map: the erase map of the SPI NOR
1272 * @addr: offset in the serial flash memory
1274 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1277 static struct spi_nor_erase_region *
1278 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1280 struct spi_nor_erase_region *region = map->regions;
1281 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1282 u64 region_end = region_start + region->size;
1284 while (addr < region_start || addr >= region_end) {
1285 region = spi_nor_region_next(region);
1287 return ERR_PTR(-EINVAL);
1289 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1290 region_end = region_start + region->size;
1297 * spi_nor_init_erase_cmd() - initialize an erase command
1298 * @region: pointer to a structure that describes a SPI NOR erase region
1299 * @erase: pointer to a structure that describes a SPI NOR erase type
1301 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1304 static struct spi_nor_erase_command *
1305 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1306 const struct spi_nor_erase_type *erase)
1308 struct spi_nor_erase_command *cmd;
1310 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1312 return ERR_PTR(-ENOMEM);
1314 INIT_LIST_HEAD(&cmd->list);
1315 cmd->opcode = erase->opcode;
1318 if (region->offset & SNOR_OVERLAID_REGION)
1319 cmd->size = region->size;
1321 cmd->size = erase->size;
1327 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1328 * @erase_list: list of erase commands
1330 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1332 struct spi_nor_erase_command *cmd, *next;
1334 list_for_each_entry_safe(cmd, next, erase_list, list) {
1335 list_del(&cmd->list);
1341 * spi_nor_init_erase_cmd_list() - initialize erase command list
1342 * @nor: pointer to a 'struct spi_nor'
1343 * @erase_list: list of erase commands to be executed once we validate that the
1344 * erase can be performed
1345 * @addr: offset in the serial flash memory
1346 * @len: number of bytes to erase
1348 * Builds the list of best fitted erase commands and verifies if the erase can
1351 * Return: 0 on success, -errno otherwise.
1353 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1354 struct list_head *erase_list,
1357 const struct spi_nor_erase_map *map = &nor->params->erase_map;
1358 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1359 struct spi_nor_erase_region *region;
1360 struct spi_nor_erase_command *cmd = NULL;
1364 region = spi_nor_find_erase_region(map, addr);
1366 return PTR_ERR(region);
1368 region_end = spi_nor_region_end(region);
1371 erase = spi_nor_find_best_erase_type(map, region, addr, len);
1373 goto destroy_erase_cmd_list;
1375 if (prev_erase != erase ||
1376 erase->size != cmd->size ||
1377 region->offset & SNOR_OVERLAID_REGION) {
1378 cmd = spi_nor_init_erase_cmd(region, erase);
1381 goto destroy_erase_cmd_list;
1384 list_add_tail(&cmd->list, erase_list);
1392 if (len && addr >= region_end) {
1393 region = spi_nor_region_next(region);
1395 goto destroy_erase_cmd_list;
1396 region_end = spi_nor_region_end(region);
1404 destroy_erase_cmd_list:
1405 spi_nor_destroy_erase_cmd_list(erase_list);
1410 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1411 * @nor: pointer to a 'struct spi_nor'
1412 * @addr: offset in the serial flash memory
1413 * @len: number of bytes to erase
1415 * Build a list of best fitted erase commands and execute it once we validate
1416 * that the erase can be performed.
1418 * Return: 0 on success, -errno otherwise.
1420 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1422 LIST_HEAD(erase_list);
1423 struct spi_nor_erase_command *cmd, *next;
1426 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1430 list_for_each_entry_safe(cmd, next, &erase_list, list) {
1431 nor->erase_opcode = cmd->opcode;
1432 while (cmd->count) {
1433 ret = spi_nor_write_enable(nor);
1435 goto destroy_erase_cmd_list;
1437 ret = spi_nor_erase_sector(nor, addr);
1439 goto destroy_erase_cmd_list;
1444 ret = spi_nor_wait_till_ready(nor);
1446 goto destroy_erase_cmd_list;
1448 list_del(&cmd->list);
1454 destroy_erase_cmd_list:
1455 spi_nor_destroy_erase_cmd_list(&erase_list);
1460 * Erase an address range on the nor chip. The address range may extend
1461 * one or more erase sectors. Return an error is there is a problem erasing.
1463 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1465 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1470 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1471 (long long)instr->len);
1473 if (spi_nor_has_uniform_erase(nor)) {
1474 div_u64_rem(instr->len, mtd->erasesize, &rem);
1482 ret = spi_nor_lock_and_prep(nor);
1486 /* whole-chip erase? */
1487 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1488 unsigned long timeout;
1490 ret = spi_nor_write_enable(nor);
1494 ret = spi_nor_erase_chip(nor);
1499 * Scale the timeout linearly with the size of the flash, with
1500 * a minimum calibrated to an old 2MB flash. We could try to
1501 * pull these from CFI/SFDP, but these values should be good
1504 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1505 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1506 (unsigned long)(mtd->size / SZ_2M));
1507 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1511 /* REVISIT in some cases we could speed up erasing large regions
1512 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1513 * to use "small sector erase", but that's not always optimal.
1516 /* "sector"-at-a-time erase */
1517 } else if (spi_nor_has_uniform_erase(nor)) {
1519 ret = spi_nor_write_enable(nor);
1523 ret = spi_nor_erase_sector(nor, addr);
1527 addr += mtd->erasesize;
1528 len -= mtd->erasesize;
1530 ret = spi_nor_wait_till_ready(nor);
1535 /* erase multiple sectors */
1537 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1542 ret = spi_nor_write_disable(nor);
1545 spi_nor_unlock_and_unprep(nor);
1550 static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor)
1552 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1554 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6)
1555 return mask | SR_BP3_BIT6;
1557 if (nor->flags & SNOR_F_HAS_4BIT_BP)
1558 return mask | SR_BP3;
1563 static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
1565 if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
1571 static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)
1573 unsigned int bp_slots, bp_slots_needed;
1574 u8 mask = spi_nor_get_sr_bp_mask(nor);
1576 /* Reserved one for "protect none" and one for "protect all". */
1577 bp_slots = (1 << hweight8(mask)) - 2;
1578 bp_slots_needed = ilog2(nor->info->n_sectors);
1580 if (bp_slots_needed > bp_slots)
1581 return nor->info->sector_size <<
1582 (bp_slots_needed - bp_slots);
1584 return nor->info->sector_size;
1587 static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs,
1590 struct mtd_info *mtd = &nor->mtd;
1592 u8 mask = spi_nor_get_sr_bp_mask(nor);
1593 u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1594 u8 bp, val = sr & mask;
1596 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6)
1597 val = (val & ~SR_BP3_BIT6) | SR_BP3;
1599 bp = val >> SR_BP_SHIFT;
1608 min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1609 *len = min_prot_len << (bp - 1);
1611 if (*len > mtd->size)
1614 if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
1617 *ofs = mtd->size - *len;
1621 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1622 * @locked is false); 0 otherwise
1624 static int spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs,
1625 uint64_t len, u8 sr, bool locked)
1633 spi_nor_get_locked_range_sr(nor, sr, &lock_offs, &lock_len);
1636 /* Requested range is a sub-range of locked range */
1637 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1639 /* Requested range does not overlap with locked range */
1640 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1643 static int spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1646 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true);
1649 static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1652 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false);
1656 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1657 * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status
1659 * (SR). Does not support these features found in newer SR bitfields:
1660 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1661 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1663 * Support for the following is provided conditionally for some flash:
1664 * - TB: top/bottom protect
1666 * Sample table portion for 8MB flash (Winbond w25q64fw):
1668 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1669 * --------------------------------------------------------------------------
1670 * X | X | 0 | 0 | 0 | NONE | NONE
1671 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1672 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1673 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1674 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1675 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1676 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1677 * X | X | 1 | 1 | 1 | 8 MB | ALL
1678 * ------|-------|-------|-------|-------|---------------|-------------------
1679 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1680 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1681 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1682 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1683 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1684 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1686 * Returns negative on errors, 0 on success.
1688 static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1690 struct mtd_info *mtd = &nor->mtd;
1692 int ret, status_old, status_new;
1693 u8 mask = spi_nor_get_sr_bp_mask(nor);
1694 u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1697 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1700 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1704 status_old = nor->bouncebuf[0];
1706 /* If nothing in our range is unlocked, we don't need to do anything */
1707 if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
1710 /* If anything below us is unlocked, we can't use 'bottom' protection */
1711 if (!spi_nor_is_locked_sr(nor, 0, ofs, status_old))
1712 can_be_bottom = false;
1714 /* If anything above us is unlocked, we can't use 'top' protection */
1715 if (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1719 if (!can_be_bottom && !can_be_top)
1722 /* Prefer top, if both are valid */
1723 use_top = can_be_top;
1725 /* lock_len: length of region that should end up locked */
1727 lock_len = mtd->size - ofs;
1729 lock_len = ofs + len;
1731 if (lock_len == mtd->size) {
1734 min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1735 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
1736 val = pow << SR_BP_SHIFT;
1738 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
1739 val = (val & ~SR_BP3) | SR_BP3_BIT6;
1744 /* Don't "lock" with no region! */
1749 status_new = (status_old & ~mask & ~tb_mask) | val;
1751 /* Disallow further writes if WP pin is asserted */
1752 status_new |= SR_SRWD;
1755 status_new |= tb_mask;
1757 /* Don't bother if they're the same */
1758 if (status_new == status_old)
1761 /* Only modify protection if it will not unlock other areas */
1762 if ((status_new & mask) < (status_old & mask))
1765 return spi_nor_write_sr_and_check(nor, status_new);
1769 * Unlock a region of the flash. See spi_nor_sr_lock() for more info
1771 * Returns negative on errors, 0 on success.
1773 static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1775 struct mtd_info *mtd = &nor->mtd;
1777 int ret, status_old, status_new;
1778 u8 mask = spi_nor_get_sr_bp_mask(nor);
1779 u8 tb_mask = spi_nor_get_sr_tb_mask(nor);
1782 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1785 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1789 status_old = nor->bouncebuf[0];
1791 /* If nothing in our range is locked, we don't need to do anything */
1792 if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
1795 /* If anything below us is locked, we can't use 'top' protection */
1796 if (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old))
1799 /* If anything above us is locked, we can't use 'bottom' protection */
1800 if (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1802 can_be_bottom = false;
1804 if (!can_be_bottom && !can_be_top)
1807 /* Prefer top, if both are valid */
1808 use_top = can_be_top;
1810 /* lock_len: length of region that should remain locked */
1812 lock_len = mtd->size - (ofs + len);
1816 if (lock_len == 0) {
1817 val = 0; /* fully unlocked */
1819 min_prot_len = spi_nor_get_min_prot_length_sr(nor);
1820 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
1821 val = pow << SR_BP_SHIFT;
1823 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
1824 val = (val & ~SR_BP3) | SR_BP3_BIT6;
1826 /* Some power-of-two sizes are not supported */
1831 status_new = (status_old & ~mask & ~tb_mask) | val;
1833 /* Don't protect status register if we're fully unlocked */
1835 status_new &= ~SR_SRWD;
1838 status_new |= tb_mask;
1840 /* Don't bother if they're the same */
1841 if (status_new == status_old)
1844 /* Only modify protection if it will not lock other areas */
1845 if ((status_new & mask) > (status_old & mask))
1848 return spi_nor_write_sr_and_check(nor, status_new);
1852 * Check if a region of the flash is (completely) locked. See spi_nor_sr_lock()
1855 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1856 * negative on errors.
1858 static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1862 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1866 return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
1869 static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = {
1870 .lock = spi_nor_sr_lock,
1871 .unlock = spi_nor_sr_unlock,
1872 .is_locked = spi_nor_sr_is_locked,
1875 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1877 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1880 ret = spi_nor_lock_and_prep(nor);
1884 ret = nor->params->locking_ops->lock(nor, ofs, len);
1886 spi_nor_unlock_and_unprep(nor);
1890 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1892 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1895 ret = spi_nor_lock_and_prep(nor);
1899 ret = nor->params->locking_ops->unlock(nor, ofs, len);
1901 spi_nor_unlock_and_unprep(nor);
1905 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1907 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1910 ret = spi_nor_lock_and_prep(nor);
1914 ret = nor->params->locking_ops->is_locked(nor, ofs, len);
1916 spi_nor_unlock_and_unprep(nor);
1921 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1923 * @nor: pointer to a 'struct spi_nor'
1925 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1927 * Return: 0 on success, -errno otherwise.
1929 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1933 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1937 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1940 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1942 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1946 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1948 * @nor: pointer to a 'struct spi_nor'.
1950 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1952 * Return: 0 on success, -errno otherwise.
1954 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1958 if (nor->flags & SNOR_F_NO_READ_CR)
1959 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1961 ret = spi_nor_read_cr(nor, nor->bouncebuf);
1965 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1968 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1970 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1974 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1975 * @nor: pointer to a 'struct spi_nor'
1977 * Set the Quad Enable (QE) bit in the Status Register 2.
1979 * This is one of the procedures to set the QE bit described in the SFDP
1980 * (JESD216 rev B) specification but no manufacturer using this procedure has
1981 * been identified yet, hence the name of the function.
1983 * Return: 0 on success, -errno otherwise.
1985 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1987 u8 *sr2 = nor->bouncebuf;
1991 /* Check current Quad Enable bit value. */
1992 ret = spi_nor_read_sr2(nor, sr2);
1995 if (*sr2 & SR2_QUAD_EN_BIT7)
1998 /* Update the Quad Enable bit. */
1999 *sr2 |= SR2_QUAD_EN_BIT7;
2001 ret = spi_nor_write_sr2(nor, sr2);
2007 /* Read back and check it. */
2008 ret = spi_nor_read_sr2(nor, sr2);
2012 if (*sr2 != sr2_written) {
2013 dev_dbg(nor->dev, "SR2: Read back test failed\n");
2020 static const struct spi_nor_manufacturer *manufacturers[] = {
2027 &spi_nor_gigadevice,
2040 static const struct flash_info *
2041 spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts,
2046 for (i = 0; i < nparts; i++) {
2047 if (parts[i].id_len &&
2048 !memcmp(parts[i].id, id, parts[i].id_len))
2055 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2057 const struct flash_info *info;
2058 u8 *id = nor->bouncebuf;
2063 struct spi_mem_op op =
2064 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
2066 SPI_MEM_OP_NO_DUMMY,
2067 SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1));
2069 ret = spi_mem_exec_op(nor->spimem, &op);
2071 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
2072 SPI_NOR_MAX_ID_LEN);
2075 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
2076 return ERR_PTR(ret);
2079 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2080 info = spi_nor_search_part_by_id(manufacturers[i]->parts,
2081 manufacturers[i]->nparts,
2084 nor->manufacturer = manufacturers[i];
2089 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2090 SPI_NOR_MAX_ID_LEN, id);
2091 return ERR_PTR(-ENODEV);
2094 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2095 size_t *retlen, u_char *buf)
2097 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2100 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2102 ret = spi_nor_lock_and_prep(nor);
2109 addr = spi_nor_convert_addr(nor, addr);
2111 ret = spi_nor_read_data(nor, addr, len, buf);
2113 /* We shouldn't see 0-length reads */
2129 spi_nor_unlock_and_unprep(nor);
2134 * Write an address range to the nor chip. Data must be written in
2135 * FLASH_PAGESIZE chunks. The address range may be any size provided
2136 * it is within the physical boundaries.
2138 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2139 size_t *retlen, const u_char *buf)
2141 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2142 size_t page_offset, page_remain, i;
2145 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2147 ret = spi_nor_lock_and_prep(nor);
2151 for (i = 0; i < len; ) {
2153 loff_t addr = to + i;
2156 * If page_size is a power of two, the offset can be quickly
2157 * calculated with an AND operation. On the other cases we
2158 * need to do a modulus operation (more expensive).
2159 * Power of two numbers have only one bit set and we can use
2160 * the instruction hweight32 to detect if we need to do a
2161 * modulus (do_div()) or not.
2163 if (hweight32(nor->page_size) == 1) {
2164 page_offset = addr & (nor->page_size - 1);
2166 uint64_t aux = addr;
2168 page_offset = do_div(aux, nor->page_size);
2170 /* the size of data remaining on the first page */
2171 page_remain = min_t(size_t,
2172 nor->page_size - page_offset, len - i);
2174 addr = spi_nor_convert_addr(nor, addr);
2176 ret = spi_nor_write_enable(nor);
2180 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2185 ret = spi_nor_wait_till_ready(nor);
2193 spi_nor_unlock_and_unprep(nor);
2197 static int spi_nor_check(struct spi_nor *nor)
2200 (!nor->spimem && !nor->controller_ops) ||
2201 (!nor->spimem && nor->controller_ops &&
2202 (!nor->controller_ops->read ||
2203 !nor->controller_ops->write ||
2204 !nor->controller_ops->read_reg ||
2205 !nor->controller_ops->write_reg))) {
2206 pr_err("spi-nor: please fill all the necessary fields!\n");
2210 if (nor->spimem && nor->controller_ops) {
2211 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2219 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2223 enum spi_nor_protocol proto)
2225 read->num_mode_clocks = num_mode_clocks;
2226 read->num_wait_states = num_wait_states;
2227 read->opcode = opcode;
2228 read->proto = proto;
2231 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2232 enum spi_nor_protocol proto)
2234 pp->opcode = opcode;
2238 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2242 for (i = 0; i < size; i++)
2243 if (table[i][0] == (int)hwcaps)
2249 int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2251 static const int hwcaps_read2cmd[][2] = {
2252 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2253 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2254 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2255 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2256 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2257 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2258 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2259 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2260 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2261 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2262 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2263 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2264 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2265 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2266 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2269 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2270 ARRAY_SIZE(hwcaps_read2cmd));
2273 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2275 static const int hwcaps_pp2cmd[][2] = {
2276 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2277 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2278 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2279 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2280 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2281 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2282 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2285 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2286 ARRAY_SIZE(hwcaps_pp2cmd));
2290 * spi_nor_spimem_check_op - check if the operation is supported
2292 *@nor: pointer to a 'struct spi_nor'
2293 *@op: pointer to op template to be checked
2295 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2297 static int spi_nor_spimem_check_op(struct spi_nor *nor,
2298 struct spi_mem_op *op)
2301 * First test with 4 address bytes. The opcode itself might
2302 * be a 3B addressing opcode but we don't care, because
2303 * SPI controller implementation should not check the opcode,
2304 * but just the sequence.
2306 op->addr.nbytes = 4;
2307 if (!spi_mem_supports_op(nor->spimem, op)) {
2308 if (nor->mtd.size > SZ_16M)
2311 /* If flash size <= 16MB, 3 address bytes are sufficient */
2312 op->addr.nbytes = 3;
2313 if (!spi_mem_supports_op(nor->spimem, op))
2321 * spi_nor_spimem_check_readop - check if the read op is supported
2323 *@nor: pointer to a 'struct spi_nor'
2324 *@read: pointer to op template to be checked
2326 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2328 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2329 const struct spi_nor_read_command *read)
2331 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1),
2332 SPI_MEM_OP_ADDR(3, 0, 1),
2333 SPI_MEM_OP_DUMMY(0, 1),
2334 SPI_MEM_OP_DATA_IN(0, NULL, 1));
2336 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto);
2337 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto);
2338 op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto);
2339 op.dummy.buswidth = op.addr.buswidth;
2340 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2341 op.dummy.buswidth / 8;
2343 return spi_nor_spimem_check_op(nor, &op);
2347 * spi_nor_spimem_check_pp - check if the page program op is supported
2349 *@nor: pointer to a 'struct spi_nor'
2350 *@pp: pointer to op template to be checked
2352 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
2354 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2355 const struct spi_nor_pp_command *pp)
2357 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1),
2358 SPI_MEM_OP_ADDR(3, 0, 1),
2359 SPI_MEM_OP_NO_DUMMY,
2360 SPI_MEM_OP_DATA_OUT(0, NULL, 1));
2362 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto);
2363 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
2364 op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
2366 return spi_nor_spimem_check_op(nor, &op);
2370 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2371 * based on SPI controller capabilities
2372 * @nor: pointer to a 'struct spi_nor'
2373 * @hwcaps: pointer to resulting capabilities after adjusting
2374 * according to controller and flash's capability
2377 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
2379 struct spi_nor_flash_parameter *params = nor->params;
2382 /* DTR modes are not supported yet, mask them all. */
2383 *hwcaps &= ~SNOR_HWCAPS_DTR;
2385 /* X-X-X modes are not supported yet, mask them all. */
2386 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2388 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2391 if (!(*hwcaps & BIT(cap)))
2394 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2396 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
2397 *hwcaps &= ~BIT(cap);
2399 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2403 if (spi_nor_spimem_check_pp(nor,
2404 ¶ms->page_programs[ppidx]))
2405 *hwcaps &= ~BIT(cap);
2410 * spi_nor_set_erase_type() - set a SPI NOR erase type
2411 * @erase: pointer to a structure that describes a SPI NOR erase type
2412 * @size: the size of the sector/block erased by the erase type
2413 * @opcode: the SPI command op code to erase the sector/block
2415 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2419 erase->opcode = opcode;
2420 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2421 erase->size_shift = ffs(erase->size) - 1;
2422 erase->size_mask = (1 << erase->size_shift) - 1;
2426 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2427 * @map: the erase map of the SPI NOR
2428 * @erase_mask: bitmask encoding erase types that can erase the entire
2430 * @flash_size: the spi nor flash memory size
2432 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2433 u8 erase_mask, u64 flash_size)
2435 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2436 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2438 map->uniform_region.size = flash_size;
2439 map->regions = &map->uniform_region;
2440 map->uniform_erase_type = erase_mask;
2443 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2444 const struct sfdp_parameter_header *bfpt_header,
2445 const struct sfdp_bfpt *bfpt,
2446 struct spi_nor_flash_parameter *params)
2450 if (nor->manufacturer && nor->manufacturer->fixups &&
2451 nor->manufacturer->fixups->post_bfpt) {
2452 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2458 if (nor->info->fixups && nor->info->fixups->post_bfpt)
2459 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
2465 static int spi_nor_select_read(struct spi_nor *nor,
2468 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2469 const struct spi_nor_read_command *read;
2474 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2478 read = &nor->params->reads[cmd];
2479 nor->read_opcode = read->opcode;
2480 nor->read_proto = read->proto;
2483 * In the SPI NOR framework, we don't need to make the difference
2484 * between mode clock cycles and wait state clock cycles.
2485 * Indeed, the value of the mode clock cycles is used by a QSPI
2486 * flash memory to know whether it should enter or leave its 0-4-4
2487 * (Continuous Read / XIP) mode.
2488 * eXecution In Place is out of the scope of the mtd sub-system.
2489 * Hence we choose to merge both mode and wait state clock cycles
2490 * into the so called dummy clock cycles.
2492 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2496 static int spi_nor_select_pp(struct spi_nor *nor,
2499 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2500 const struct spi_nor_pp_command *pp;
2505 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2509 pp = &nor->params->page_programs[cmd];
2510 nor->program_opcode = pp->opcode;
2511 nor->write_proto = pp->proto;
2516 * spi_nor_select_uniform_erase() - select optimum uniform erase type
2517 * @map: the erase map of the SPI NOR
2518 * @wanted_size: the erase type size to search for. Contains the value of
2519 * info->sector_size or of the "small sector" size in case
2520 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
2522 * Once the optimum uniform sector erase command is found, disable all the
2525 * Return: pointer to erase type on success, NULL otherwise.
2527 static const struct spi_nor_erase_type *
2528 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2529 const u32 wanted_size)
2531 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2533 u8 uniform_erase_type = map->uniform_erase_type;
2535 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2536 if (!(uniform_erase_type & BIT(i)))
2539 tested_erase = &map->erase_type[i];
2542 * If the current erase size is the one, stop here:
2543 * we have found the right uniform Sector Erase command.
2545 if (tested_erase->size == wanted_size) {
2546 erase = tested_erase;
2551 * Otherwise, the current erase size is still a valid canditate.
2552 * Select the biggest valid candidate.
2554 if (!erase && tested_erase->size)
2555 erase = tested_erase;
2556 /* keep iterating to find the wanted_size */
2562 /* Disable all other Sector Erase commands. */
2563 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2564 map->uniform_erase_type |= BIT(erase - map->erase_type);
2568 static int spi_nor_select_erase(struct spi_nor *nor)
2570 struct spi_nor_erase_map *map = &nor->params->erase_map;
2571 const struct spi_nor_erase_type *erase = NULL;
2572 struct mtd_info *mtd = &nor->mtd;
2573 u32 wanted_size = nor->info->sector_size;
2577 * The previous implementation handling Sector Erase commands assumed
2578 * that the SPI flash memory has an uniform layout then used only one
2579 * of the supported erase sizes for all Sector Erase commands.
2580 * So to be backward compatible, the new implementation also tries to
2581 * manage the SPI flash memory as uniform with a single erase sector
2582 * size, when possible.
2584 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2585 /* prefer "small sector" erase if possible */
2586 wanted_size = 4096u;
2589 if (spi_nor_has_uniform_erase(nor)) {
2590 erase = spi_nor_select_uniform_erase(map, wanted_size);
2593 nor->erase_opcode = erase->opcode;
2594 mtd->erasesize = erase->size;
2599 * For non-uniform SPI flash memory, set mtd->erasesize to the
2600 * maximum erase sector size. No need to set nor->erase_opcode.
2602 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2603 if (map->erase_type[i].size) {
2604 erase = &map->erase_type[i];
2612 mtd->erasesize = erase->size;
2616 static int spi_nor_default_setup(struct spi_nor *nor,
2617 const struct spi_nor_hwcaps *hwcaps)
2619 struct spi_nor_flash_parameter *params = nor->params;
2620 u32 ignored_mask, shared_mask;
2624 * Keep only the hardware capabilities supported by both the SPI
2625 * controller and the SPI flash memory.
2627 shared_mask = hwcaps->mask & params->hwcaps.mask;
2631 * When called from spi_nor_probe(), all caps are set and we
2632 * need to discard some of them based on what the SPI
2633 * controller actually supports (using spi_mem_supports_op()).
2635 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2638 * SPI n-n-n protocols are not supported when the SPI
2639 * controller directly implements the spi_nor interface.
2640 * Yet another reason to switch to spi-mem.
2642 ignored_mask = SNOR_HWCAPS_X_X_X;
2643 if (shared_mask & ignored_mask) {
2645 "SPI n-n-n protocols are not supported.\n");
2646 shared_mask &= ~ignored_mask;
2650 /* Select the (Fast) Read command. */
2651 err = spi_nor_select_read(nor, shared_mask);
2654 "can't select read settings supported by both the SPI controller and memory.\n");
2658 /* Select the Page Program command. */
2659 err = spi_nor_select_pp(nor, shared_mask);
2662 "can't select write settings supported by both the SPI controller and memory.\n");
2666 /* Select the Sector Erase command. */
2667 err = spi_nor_select_erase(nor);
2670 "can't select erase settings supported by both the SPI controller and memory.\n");
2677 static int spi_nor_setup(struct spi_nor *nor,
2678 const struct spi_nor_hwcaps *hwcaps)
2680 if (!nor->params->setup)
2683 return nor->params->setup(nor, hwcaps);
2687 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2688 * settings based on MFR register and ->default_init() hook.
2689 * @nor: pointer to a 'struct spi_nor'.
2691 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2693 if (nor->manufacturer && nor->manufacturer->fixups &&
2694 nor->manufacturer->fixups->default_init)
2695 nor->manufacturer->fixups->default_init(nor);
2697 if (nor->info->fixups && nor->info->fixups->default_init)
2698 nor->info->fixups->default_init(nor);
2702 * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
2703 * based on JESD216 SFDP standard.
2704 * @nor: pointer to a 'struct spi_nor'.
2706 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2707 * legacy flash parameters and settings will be restored.
2709 static void spi_nor_sfdp_init_params(struct spi_nor *nor)
2711 struct spi_nor_flash_parameter sfdp_params;
2713 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2715 if (spi_nor_parse_sfdp(nor, nor->params)) {
2716 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2717 nor->addr_width = 0;
2718 nor->flags &= ~SNOR_F_4B_OPCODES;
2723 * spi_nor_info_init_params() - Initialize the flash's parameters and settings
2724 * based on nor->info data.
2725 * @nor: pointer to a 'struct spi_nor'.
2727 static void spi_nor_info_init_params(struct spi_nor *nor)
2729 struct spi_nor_flash_parameter *params = nor->params;
2730 struct spi_nor_erase_map *map = ¶ms->erase_map;
2731 const struct flash_info *info = nor->info;
2732 struct device_node *np = spi_nor_get_flash_node(nor);
2735 /* Initialize legacy flash parameters and settings. */
2736 params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2737 params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2738 params->setup = spi_nor_default_setup;
2739 /* Default to 16-bit Write Status (01h) Command */
2740 nor->flags |= SNOR_F_HAS_16BIT_SR;
2742 /* Set SPI NOR sizes. */
2743 params->size = (u64)info->sector_size * info->n_sectors;
2744 params->page_size = info->page_size;
2746 if (!(info->flags & SPI_NOR_NO_FR)) {
2747 /* Default to Fast Read for DT and non-DT platform devices. */
2748 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2750 /* Mask out Fast Read if not requested at DT instantiation. */
2751 if (np && !of_property_read_bool(np, "m25p,fast-read"))
2752 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2755 /* (Fast) Read settings. */
2756 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2757 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2758 0, 0, SPINOR_OP_READ,
2761 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2762 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2763 0, 8, SPINOR_OP_READ_FAST,
2766 if (info->flags & SPI_NOR_DUAL_READ) {
2767 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2768 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2769 0, 8, SPINOR_OP_READ_1_1_2,
2773 if (info->flags & SPI_NOR_QUAD_READ) {
2774 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2775 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2776 0, 8, SPINOR_OP_READ_1_1_4,
2780 if (info->flags & SPI_NOR_OCTAL_READ) {
2781 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2782 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2783 0, 8, SPINOR_OP_READ_1_1_8,
2787 /* Page Program settings. */
2788 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2789 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2790 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2793 * Sector Erase settings. Sort Erase Types in ascending order, with the
2794 * smallest erase size starting at BIT(0).
2798 if (info->flags & SECT_4K_PMC) {
2799 erase_mask |= BIT(i);
2800 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2801 SPINOR_OP_BE_4K_PMC);
2803 } else if (info->flags & SECT_4K) {
2804 erase_mask |= BIT(i);
2805 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2809 erase_mask |= BIT(i);
2810 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
2812 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2816 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2817 * after SFDP has been parsed (is also called for SPI NORs that do not
2819 * @nor: pointer to a 'struct spi_nor'
2821 * Typically used to tweak various parameters that could not be extracted by
2822 * other means (i.e. when information provided by the SFDP/flash_info tables
2823 * are incomplete or wrong).
2825 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
2827 if (nor->manufacturer && nor->manufacturer->fixups &&
2828 nor->manufacturer->fixups->post_sfdp)
2829 nor->manufacturer->fixups->post_sfdp(nor);
2831 if (nor->info->fixups && nor->info->fixups->post_sfdp)
2832 nor->info->fixups->post_sfdp(nor);
2836 * spi_nor_late_init_params() - Late initialization of default flash parameters.
2837 * @nor: pointer to a 'struct spi_nor'
2839 * Used to set default flash parameters and settings when the ->default_init()
2840 * hook or the SFDP parser let voids.
2842 static void spi_nor_late_init_params(struct spi_nor *nor)
2845 * NOR protection support. When locking_ops are not provided, we pick
2848 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2849 nor->params->locking_ops = &spi_nor_sr_locking_ops;
2853 * spi_nor_init_params() - Initialize the flash's parameters and settings.
2854 * @nor: pointer to a 'struct spi_nor'.
2856 * The flash parameters and settings are initialized based on a sequence of
2857 * calls that are ordered by priority:
2859 * 1/ Default flash parameters initialization. The initializations are done
2860 * based on nor->info data:
2861 * spi_nor_info_init_params()
2863 * which can be overwritten by:
2864 * 2/ Manufacturer flash parameters initialization. The initializations are
2865 * done based on MFR register, or when the decisions can not be done solely
2866 * based on MFR, by using specific flash_info tweeks, ->default_init():
2867 * spi_nor_manufacturer_init_params()
2869 * which can be overwritten by:
2870 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2871 * should be more accurate that the above.
2872 * spi_nor_sfdp_init_params()
2874 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
2875 * the flash parameters and settings immediately after parsing the Basic
2876 * Flash Parameter Table.
2878 * which can be overwritten by:
2879 * 4/ Post SFDP flash parameters initialization. Used to tweak various
2880 * parameters that could not be extracted by other means (i.e. when
2881 * information provided by the SFDP/flash_info tables are incomplete or
2883 * spi_nor_post_sfdp_fixups()
2885 * 5/ Late default flash parameters initialization, used when the
2886 * ->default_init() hook or the SFDP parser do not set specific params.
2887 * spi_nor_late_init_params()
2889 static int spi_nor_init_params(struct spi_nor *nor)
2891 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2895 spi_nor_info_init_params(nor);
2897 spi_nor_manufacturer_init_params(nor);
2899 if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2900 !(nor->info->flags & SPI_NOR_SKIP_SFDP))
2901 spi_nor_sfdp_init_params(nor);
2903 spi_nor_post_sfdp_fixups(nor);
2905 spi_nor_late_init_params(nor);
2911 * spi_nor_quad_enable() - enable Quad I/O if needed.
2912 * @nor: pointer to a 'struct spi_nor'
2914 * Return: 0 on success, -errno otherwise.
2916 static int spi_nor_quad_enable(struct spi_nor *nor)
2918 if (!nor->params->quad_enable)
2921 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2922 spi_nor_get_protocol_width(nor->write_proto) == 4))
2925 return nor->params->quad_enable(nor);
2929 * spi_nor_try_unlock_all() - Tries to unlock the entire flash memory array.
2930 * @nor: pointer to a 'struct spi_nor'.
2932 * Some SPI NOR flashes are write protected by default after a power-on reset
2933 * cycle, in order to avoid inadvertent writes during power-up. Backward
2934 * compatibility imposes to unlock the entire flash memory array at power-up
2937 * Unprotecting the entire flash array will fail for boards which are hardware
2938 * write-protected. Thus any errors are ignored.
2940 static void spi_nor_try_unlock_all(struct spi_nor *nor)
2944 if (!(nor->flags & SNOR_F_HAS_LOCK))
2947 ret = spi_nor_unlock(&nor->mtd, 0, nor->params->size);
2949 dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n");
2952 static int spi_nor_init(struct spi_nor *nor)
2956 err = spi_nor_quad_enable(nor);
2958 dev_dbg(nor->dev, "quad mode not supported\n");
2962 spi_nor_try_unlock_all(nor);
2964 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
2966 * If the RESET# pin isn't hooked up properly, or the system
2967 * otherwise doesn't perform a reset command in the boot
2968 * sequence, it's impossible to 100% protect against unexpected
2969 * reboots (e.g., crashes). Warn the user (or hopefully, system
2970 * designer) that this is bad.
2972 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2973 "enabling reset hack; may not recover from unexpected reboots\n");
2974 nor->params->set_4byte_addr_mode(nor, true);
2980 /* mtd resume handler */
2981 static void spi_nor_resume(struct mtd_info *mtd)
2983 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2984 struct device *dev = nor->dev;
2987 /* re-initialize the nor chip */
2988 ret = spi_nor_init(nor);
2990 dev_err(dev, "resume() failed\n");
2993 static int spi_nor_get_device(struct mtd_info *mtd)
2995 struct mtd_info *master = mtd_get_master(mtd);
2996 struct spi_nor *nor = mtd_to_spi_nor(master);
3000 dev = nor->spimem->spi->controller->dev.parent;
3004 if (!try_module_get(dev->driver->owner))
3010 static void spi_nor_put_device(struct mtd_info *mtd)
3012 struct mtd_info *master = mtd_get_master(mtd);
3013 struct spi_nor *nor = mtd_to_spi_nor(master);
3017 dev = nor->spimem->spi->controller->dev.parent;
3021 module_put(dev->driver->owner);
3024 void spi_nor_restore(struct spi_nor *nor)
3026 /* restore the addressing mode */
3027 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
3028 nor->flags & SNOR_F_BROKEN_RESET)
3029 nor->params->set_4byte_addr_mode(nor, false);
3031 EXPORT_SYMBOL_GPL(spi_nor_restore);
3033 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
3038 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
3039 for (j = 0; j < manufacturers[i]->nparts; j++) {
3040 if (!strcmp(name, manufacturers[i]->parts[j].name)) {
3041 nor->manufacturer = manufacturers[i];
3042 return &manufacturers[i]->parts[j];
3050 static int spi_nor_set_addr_width(struct spi_nor *nor)
3052 if (nor->addr_width) {
3053 /* already configured from SFDP */
3054 } else if (nor->info->addr_width) {
3055 nor->addr_width = nor->info->addr_width;
3057 nor->addr_width = 3;
3060 if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
3061 /* enable 4-byte addressing if the device exceeds 16MiB */
3062 nor->addr_width = 4;
3065 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3066 dev_dbg(nor->dev, "address width is too large: %u\n",
3071 /* Set 4byte opcodes when possible. */
3072 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
3073 !(nor->flags & SNOR_F_HAS_4BAIT))
3074 spi_nor_set_4byte_opcodes(nor);
3079 static void spi_nor_debugfs_init(struct spi_nor *nor,
3080 const struct flash_info *info)
3082 struct mtd_info *mtd = &nor->mtd;
3084 mtd->dbg.partname = info->name;
3085 mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN",
3086 info->id_len, info->id);
3089 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3092 const struct flash_info *info = NULL;
3095 info = spi_nor_match_id(nor, name);
3096 /* Try to auto-detect if chip name wasn't specified or not found */
3098 info = spi_nor_read_id(nor);
3099 if (IS_ERR_OR_NULL(info))
3100 return ERR_PTR(-ENOENT);
3103 * If caller has specified name of flash model that can normally be
3104 * detected using JEDEC, let's verify it.
3106 if (name && info->id_len) {
3107 const struct flash_info *jinfo;
3109 jinfo = spi_nor_read_id(nor);
3110 if (IS_ERR(jinfo)) {
3112 } else if (jinfo != info) {
3114 * JEDEC knows better, so overwrite platform ID. We
3115 * can't trust partitions any longer, but we'll let
3116 * mtd apply them anyway, since some partitions may be
3117 * marked read-only, and we don't want to lose that
3118 * information, even if it's not 100% accurate.
3120 dev_warn(nor->dev, "found %s, expected %s\n",
3121 jinfo->name, info->name);
3129 int spi_nor_scan(struct spi_nor *nor, const char *name,
3130 const struct spi_nor_hwcaps *hwcaps)
3132 const struct flash_info *info;
3133 struct device *dev = nor->dev;
3134 struct mtd_info *mtd = &nor->mtd;
3135 struct device_node *np = spi_nor_get_flash_node(nor);
3139 ret = spi_nor_check(nor);
3143 /* Reset SPI protocol for all commands. */
3144 nor->reg_proto = SNOR_PROTO_1_1_1;
3145 nor->read_proto = SNOR_PROTO_1_1_1;
3146 nor->write_proto = SNOR_PROTO_1_1_1;
3149 * We need the bounce buffer early to read/write registers when going
3150 * through the spi-mem layer (buffers have to be DMA-able).
3151 * For spi-mem drivers, we'll reallocate a new buffer if
3152 * nor->page_size turns out to be greater than PAGE_SIZE (which
3153 * shouldn't happen before long since NOR pages are usually less
3154 * than 1KB) after spi_nor_scan() returns.
3156 nor->bouncebuf_size = PAGE_SIZE;
3157 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3159 if (!nor->bouncebuf)
3162 info = spi_nor_get_flash_info(nor, name);
3164 return PTR_ERR(info);
3168 spi_nor_debugfs_init(nor, info);
3170 mutex_init(&nor->lock);
3173 * Make sure the XSR_RDY flag is set before calling
3174 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
3175 * with Atmel SPI NOR.
3177 if (info->flags & SPI_NOR_XSR_RDY)
3178 nor->flags |= SNOR_F_READY_XSR_RDY;
3180 if (info->flags & SPI_NOR_HAS_LOCK)
3181 nor->flags |= SNOR_F_HAS_LOCK;
3183 mtd->_write = spi_nor_write;
3185 /* Init flash parameters based on flash_info struct and SFDP */
3186 ret = spi_nor_init_params(nor);
3191 mtd->name = dev_name(dev);
3193 mtd->type = MTD_NORFLASH;
3195 mtd->flags = MTD_CAP_NORFLASH;
3196 mtd->size = nor->params->size;
3197 mtd->_erase = spi_nor_erase;
3198 mtd->_read = spi_nor_read;
3199 mtd->_resume = spi_nor_resume;
3200 mtd->_get_device = spi_nor_get_device;
3201 mtd->_put_device = spi_nor_put_device;
3203 if (nor->params->locking_ops) {
3204 mtd->_lock = spi_nor_lock;
3205 mtd->_unlock = spi_nor_unlock;
3206 mtd->_is_locked = spi_nor_is_locked;
3209 if (info->flags & USE_FSR)
3210 nor->flags |= SNOR_F_USE_FSR;
3211 if (info->flags & SPI_NOR_HAS_TB) {
3212 nor->flags |= SNOR_F_HAS_SR_TB;
3213 if (info->flags & SPI_NOR_TB_SR_BIT6)
3214 nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
3217 if (info->flags & NO_CHIP_ERASE)
3218 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3219 if (info->flags & USE_CLSR)
3220 nor->flags |= SNOR_F_USE_CLSR;
3222 if (info->flags & SPI_NOR_4BIT_BP) {
3223 nor->flags |= SNOR_F_HAS_4BIT_BP;
3224 if (info->flags & SPI_NOR_BP3_SR_BIT6)
3225 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
3228 if (info->flags & SPI_NOR_NO_ERASE)
3229 mtd->flags |= MTD_NO_ERASE;
3231 mtd->dev.parent = dev;
3232 nor->page_size = nor->params->page_size;
3233 mtd->writebufsize = nor->page_size;
3235 if (of_property_read_bool(np, "broken-flash-reset"))
3236 nor->flags |= SNOR_F_BROKEN_RESET;
3239 * Configure the SPI memory:
3240 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3241 * - set the number of dummy cycles (mode cycles + wait states).
3242 * - set the SPI protocols for register and memory accesses.
3244 ret = spi_nor_setup(nor, hwcaps);
3248 if (info->flags & SPI_NOR_4B_OPCODES)
3249 nor->flags |= SNOR_F_4B_OPCODES;
3251 ret = spi_nor_set_addr_width(nor);
3255 /* Send all the required SPI flash commands to initialize device */
3256 ret = spi_nor_init(nor);
3260 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3261 (long long)mtd->size >> 10);
3264 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
3265 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3266 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3267 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3269 if (mtd->numeraseregions)
3270 for (i = 0; i < mtd->numeraseregions; i++)
3272 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
3273 ".erasesize = 0x%.8x (%uKiB), "
3274 ".numblocks = %d }\n",
3275 i, (long long)mtd->eraseregions[i].offset,
3276 mtd->eraseregions[i].erasesize,
3277 mtd->eraseregions[i].erasesize / 1024,
3278 mtd->eraseregions[i].numblocks);
3281 EXPORT_SYMBOL_GPL(spi_nor_scan);
3283 static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3285 struct spi_mem_dirmap_info info = {
3286 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
3287 SPI_MEM_OP_ADDR(nor->addr_width, 0, 1),
3288 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
3289 SPI_MEM_OP_DATA_IN(0, NULL, 1)),
3291 .length = nor->mtd.size,
3293 struct spi_mem_op *op = &info.op_tmpl;
3295 /* get transfer protocols. */
3296 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
3297 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
3298 op->dummy.buswidth = op->addr.buswidth;
3299 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3301 /* convert the dummy cycles to the number of bytes */
3302 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3304 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3306 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3309 static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3311 struct spi_mem_dirmap_info info = {
3312 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
3313 SPI_MEM_OP_ADDR(nor->addr_width, 0, 1),
3314 SPI_MEM_OP_NO_DUMMY,
3315 SPI_MEM_OP_DATA_OUT(0, NULL, 1)),
3317 .length = nor->mtd.size,
3319 struct spi_mem_op *op = &info.op_tmpl;
3321 /* get transfer protocols. */
3322 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
3323 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
3324 op->dummy.buswidth = op->addr.buswidth;
3325 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3327 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3328 op->addr.nbytes = 0;
3330 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3332 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3335 static int spi_nor_probe(struct spi_mem *spimem)
3337 struct spi_device *spi = spimem->spi;
3338 struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3339 struct spi_nor *nor;
3341 * Enable all caps by default. The core will mask them after
3342 * checking what's really supported using spi_mem_supports_op().
3344 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3348 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3352 nor->spimem = spimem;
3353 nor->dev = &spi->dev;
3354 spi_nor_set_flash_node(nor, spi->dev.of_node);
3356 spi_mem_set_drvdata(spimem, nor);
3358 if (data && data->name)
3359 nor->mtd.name = data->name;
3362 nor->mtd.name = spi_mem_get_name(spimem);
3365 * For some (historical?) reason many platforms provide two different
3366 * names in flash_platform_data: "name" and "type". Quite often name is
3367 * set to "m25p80" and then "type" provides a real chip name.
3368 * If that's the case, respect "type" and ignore a "name".
3370 if (data && data->type)
3371 flash_name = data->type;
3372 else if (!strcmp(spi->modalias, "spi-nor"))
3373 flash_name = NULL; /* auto-detect */
3375 flash_name = spi->modalias;
3377 ret = spi_nor_scan(nor, flash_name, &hwcaps);
3382 * None of the existing parts have > 512B pages, but let's play safe
3383 * and add this logic so that if anyone ever adds support for such
3384 * a NOR we don't end up with buffer overflows.
3386 if (nor->page_size > PAGE_SIZE) {
3387 nor->bouncebuf_size = nor->page_size;
3388 devm_kfree(nor->dev, nor->bouncebuf);
3389 nor->bouncebuf = devm_kmalloc(nor->dev,
3390 nor->bouncebuf_size,
3392 if (!nor->bouncebuf)
3396 ret = spi_nor_create_read_dirmap(nor);
3400 ret = spi_nor_create_write_dirmap(nor);
3404 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3405 data ? data->nr_parts : 0);
3408 static int spi_nor_remove(struct spi_mem *spimem)
3410 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3412 spi_nor_restore(nor);
3414 /* Clean up MTD stuff. */
3415 return mtd_device_unregister(&nor->mtd);
3418 static void spi_nor_shutdown(struct spi_mem *spimem)
3420 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3422 spi_nor_restore(nor);
3426 * Do NOT add to this array without reading the following:
3428 * Historically, many flash devices are bound to this driver by their name. But
3429 * since most of these flash are compatible to some extent, and their
3430 * differences can often be differentiated by the JEDEC read-ID command, we
3431 * encourage new users to add support to the spi-nor library, and simply bind
3432 * against a generic string here (e.g., "jedec,spi-nor").
3434 * Many flash names are kept here in this list (as well as in spi-nor.c) to
3435 * keep them available as module aliases for existing platforms.
3437 static const struct spi_device_id spi_nor_dev_ids[] = {
3439 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3440 * hack around the fact that the SPI core does not provide uevent
3441 * matching for .of_match_table
3446 * Entries not used in DTs that should be safe to drop after replacing
3447 * them with "spi-nor" in platform data.
3449 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
3452 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3453 * should be kept for backward compatibility.
3455 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
3456 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3457 {"mx25l25635e"},{"mx66l51235l"},
3458 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3459 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
3461 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3462 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
3463 {"m25p64"}, {"m25p128"},
3464 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
3465 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
3467 /* Flashes that can't be detected using JEDEC */
3468 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3469 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3470 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3472 /* Everspin MRAMs (non-JEDEC) */
3473 { "mr25h128" }, /* 128 Kib, 40 MHz */
3474 { "mr25h256" }, /* 256 Kib, 40 MHz */
3475 { "mr25h10" }, /* 1 Mib, 40 MHz */
3476 { "mr25h40" }, /* 4 Mib, 40 MHz */
3480 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3482 static const struct of_device_id spi_nor_of_table[] = {
3484 * Generic compatibility for SPI NOR that can be identified by the
3485 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3487 { .compatible = "jedec,spi-nor" },
3490 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3493 * REVISIT: many of these chips have deep power-down modes, which
3494 * should clearly be entered on suspend() to minimize power use.
3495 * And also when they're otherwise idle...
3497 static struct spi_mem_driver spi_nor_driver = {
3501 .of_match_table = spi_nor_of_table,
3503 .id_table = spi_nor_dev_ids,
3505 .probe = spi_nor_probe,
3506 .remove = spi_nor_remove,
3507 .shutdown = spi_nor_shutdown,
3509 module_spi_mem_driver(spi_nor_driver);
3511 MODULE_LICENSE("GPL v2");
3512 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3513 MODULE_AUTHOR("Mike Lavender");
3514 MODULE_DESCRIPTION("framework for SPI NOR");