drivers/mtd/spi-nor/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
   4  * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
   5  *
   6  * Copyright (C) 2005, Intec Automation Inc.
   7  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/errno.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/mutex.h>
  15 #include <linux/math64.h>
  16 #include <linux/sizes.h>
  17 #include <linux/slab.h>
  18
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/spi/flash.h>
  23 #include <linux/mtd/spi-nor.h>
  24
  25 #include "core.h"
  26
  27 /* Define max times to check status register before we give up. */
  28
  29 /*
  30  * For everything but full-chip erase; probably could be much smaller, but kept
  31  * around for safety for now
  32  */
  33 #define DEFAULT_READY_WAIT_JIFFIES              (40UL * HZ)
  34
  35 /*
  36  * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
  37  * for larger flash
  38  */
  39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES       (40UL * HZ)
  40
  41 #define SPI_NOR_MAX_ADDR_WIDTH  4
  42
  43 #define SPI_NOR_SRST_SLEEP_MIN 200
  44 #define SPI_NOR_SRST_SLEEP_MAX 400
  45
  46 /**
  47  * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
  48  *                         extension type.
  49  * @nor:                pointer to a 'struct spi_nor'
  50  * @op:                 pointer to the 'struct spi_mem_op' whose properties
  51  *                      need to be initialized.
  52  *
  53  * Right now, only "repeat" and "invert" are supported.
  54  *
  55  * Return: The opcode extension.
  56  */
  57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
  58                               const struct spi_mem_op *op)
  59 {
  60         switch (nor->cmd_ext_type) {
  61         case SPI_NOR_EXT_INVERT:
  62                 return ~op->cmd.opcode;
  63
  64         case SPI_NOR_EXT_REPEAT:
  65                 return op->cmd.opcode;
  66
  67         default:
  68                 dev_err(nor->dev, "Unknown command extension type\n");
  69                 return 0;
  70         }
  71 }
  72
  73 /**
  74  * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
  75  * @nor:                pointer to a 'struct spi_nor'
  76  * @op:                 pointer to the 'struct spi_mem_op' whose properties
  77  *                      need to be initialized.
  78  * @proto:              the protocol from which the properties need to be set.
  79  */
  80 void spi_nor_spimem_setup_op(const struct spi_nor *nor,
  81                              struct spi_mem_op *op,
  82                              const enum spi_nor_protocol proto)
  83 {
  84         u8 ext;
  85
  86         op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
  87
  88         if (op->addr.nbytes)
  89                 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  90
  91         if (op->dummy.nbytes)
  92                 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  93
  94         if (op->data.nbytes)
  95                 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
  96
  97         if (spi_nor_protocol_is_dtr(proto)) {
  98                 /*
  99                  * SPIMEM supports mixed DTR modes, but right now we can only
 100                  * have all phases either DTR or STR. IOW, SPIMEM can have
 101                  * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
 102                  * phases to either DTR or STR.
 103                  */
 104                 op->cmd.dtr = true;
 105                 op->addr.dtr = true;
 106                 op->dummy.dtr = true;
 107                 op->data.dtr = true;
 108
 109                 /* 2 bytes per clock cycle in DTR mode. */
 110                 op->dummy.nbytes *= 2;
 111
 112                 ext = spi_nor_get_cmd_ext(nor, op);
 113                 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
 114                 op->cmd.nbytes = 2;
 115         }
 116 }
 117
 118 /**
 119  * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
 120  *                           transfer
 121  * @nor:        pointer to 'struct spi_nor'
 122  * @op:         pointer to 'struct spi_mem_op' template for transfer
 123  *
 124  * If we have to use the bounce buffer, the data field in @op will be updated.
 125  *
 126  * Return: true if the bounce buffer is needed, false if not
 127  */
 128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
 129 {
 130         /* op->data.buf.in occupies the same memory as op->data.buf.out */
 131         if (object_is_on_stack(op->data.buf.in) ||
 132             !virt_addr_valid(op->data.buf.in)) {
 133                 if (op->data.nbytes > nor->bouncebuf_size)
 134                         op->data.nbytes = nor->bouncebuf_size;
 135                 op->data.buf.in = nor->bouncebuf;
 136                 return true;
 137         }
 138
 139         return false;
 140 }
 141
 142 /**
 143  * spi_nor_spimem_exec_op() - execute a memory operation
 144  * @nor:        pointer to 'struct spi_nor'
 145  * @op:         pointer to 'struct spi_mem_op' template for transfer
 146  *
 147  * Return: 0 on success, -error otherwise.
 148  */
 149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
 150 {
 151         int error;
 152
 153         error = spi_mem_adjust_op_size(nor->spimem, op);
 154         if (error)
 155                 return error;
 156
 157         return spi_mem_exec_op(nor->spimem, op);
 158 }
 159
 160 static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
 161                                            u8 *buf, size_t len)
 162 {
 163         if (spi_nor_protocol_is_dtr(nor->reg_proto))
 164                 return -EOPNOTSUPP;
 165
 166         return nor->controller_ops->read_reg(nor, opcode, buf, len);
 167 }
 168
 169 static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
 170                                             const u8 *buf, size_t len)
 171 {
 172         if (spi_nor_protocol_is_dtr(nor->reg_proto))
 173                 return -EOPNOTSUPP;
 174
 175         return nor->controller_ops->write_reg(nor, opcode, buf, len);
 176 }
 177
 178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
 179 {
 180         if (spi_nor_protocol_is_dtr(nor->write_proto))
 181                 return -EOPNOTSUPP;
 182
 183         return nor->controller_ops->erase(nor, offs);
 184 }
 185
 186 /**
 187  * spi_nor_spimem_read_data() - read data from flash's memory region via
 188  *                              spi-mem
 189  * @nor:        pointer to 'struct spi_nor'
 190  * @from:       offset to read from
 191  * @len:        number of bytes to read
 192  * @buf:        pointer to dst buffer
 193  *
 194  * Return: number of bytes read successfully, -errno otherwise
 195  */
 196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
 197                                         size_t len, u8 *buf)
 198 {
 199         struct spi_mem_op op =
 200                 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
 201                            SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
 202                            SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
 203                            SPI_MEM_OP_DATA_IN(len, buf, 0));
 204         bool usebouncebuf;
 205         ssize_t nbytes;
 206         int error;
 207
 208         spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
 209
 210         /* convert the dummy cycles to the number of bytes */
 211         op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
 212         if (spi_nor_protocol_is_dtr(nor->read_proto))
 213                 op.dummy.nbytes *= 2;
 214
 215         usebouncebuf = spi_nor_spimem_bounce(nor, &op);
 216
 217         if (nor->dirmap.rdesc) {
 218                 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
 219                                              op.data.nbytes, op.data.buf.in);
 220         } else {
 221                 error = spi_nor_spimem_exec_op(nor, &op);
 222                 if (error)
 223                         return error;
 224                 nbytes = op.data.nbytes;
 225         }
 226
 227         if (usebouncebuf && nbytes > 0)
 228                 memcpy(buf, op.data.buf.in, nbytes);
 229
 230         return nbytes;
 231 }
 232
 233 /**
 234  * spi_nor_read_data() - read data from flash memory
 235  * @nor:        pointer to 'struct spi_nor'
 236  * @from:       offset to read from
 237  * @len:        number of bytes to read
 238  * @buf:        pointer to dst buffer
 239  *
 240  * Return: number of bytes read successfully, -errno otherwise
 241  */
 242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
 243 {
 244         if (nor->spimem)
 245                 return spi_nor_spimem_read_data(nor, from, len, buf);
 246
 247         return nor->controller_ops->read(nor, from, len, buf);
 248 }
 249
 250 /**
 251  * spi_nor_spimem_write_data() - write data to flash memory via
 252  *                               spi-mem
 253  * @nor:        pointer to 'struct spi_nor'
 254  * @to:         offset to write to
 255  * @len:        number of bytes to write
 256  * @buf:        pointer to src buffer
 257  *
 258  * Return: number of bytes written successfully, -errno otherwise
 259  */
 260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
 261                                          size_t len, const u8 *buf)
 262 {
 263         struct spi_mem_op op =
 264                 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
 265                            SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
 266                            SPI_MEM_OP_NO_DUMMY,
 267                            SPI_MEM_OP_DATA_OUT(len, buf, 0));
 268         ssize_t nbytes;
 269         int error;
 270
 271         if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
 272                 op.addr.nbytes = 0;
 273
 274         spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
 275
 276         if (spi_nor_spimem_bounce(nor, &op))
 277                 memcpy(nor->bouncebuf, buf, op.data.nbytes);
 278
 279         if (nor->dirmap.wdesc) {
 280                 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
 281                                               op.data.nbytes, op.data.buf.out);
 282         } else {
 283                 error = spi_nor_spimem_exec_op(nor, &op);
 284                 if (error)
 285                         return error;
 286                 nbytes = op.data.nbytes;
 287         }
 288
 289         return nbytes;
 290 }
 291
 292 /**
 293  * spi_nor_write_data() - write data to flash memory
 294  * @nor:        pointer to 'struct spi_nor'
 295  * @to:         offset to write to
 296  * @len:        number of bytes to write
 297  * @buf:        pointer to src buffer
 298  *
 299  * Return: number of bytes written successfully, -errno otherwise
 300  */
 301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
 302                            const u8 *buf)
 303 {
 304         if (nor->spimem)
 305                 return spi_nor_spimem_write_data(nor, to, len, buf);
 306
 307         return nor->controller_ops->write(nor, to, len, buf);
 308 }
 309
 310 /**
 311  * spi_nor_write_enable() - Set write enable latch with Write Enable command.
 312  * @nor:        pointer to 'struct spi_nor'.
 313  *
 314  * Return: 0 on success, -errno otherwise.
 315  */
 316 int spi_nor_write_enable(struct spi_nor *nor)
 317 {
 318         int ret;
 319
 320         if (nor->spimem) {
 321                 struct spi_mem_op op =
 322                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0),
 323                                    SPI_MEM_OP_NO_ADDR,
 324                                    SPI_MEM_OP_NO_DUMMY,
 325                                    SPI_MEM_OP_NO_DATA);
 326
 327                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 328
 329                 ret = spi_mem_exec_op(nor->spimem, &op);
 330         } else {
 331                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
 332                                                        NULL, 0);
 333         }
 334
 335         if (ret)
 336                 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
 337
 338         return ret;
 339 }
 340
 341 /**
 342  * spi_nor_write_disable() - Send Write Disable instruction to the chip.
 343  * @nor:        pointer to 'struct spi_nor'.
 344  *
 345  * Return: 0 on success, -errno otherwise.
 346  */
 347 int spi_nor_write_disable(struct spi_nor *nor)
 348 {
 349         int ret;
 350
 351         if (nor->spimem) {
 352                 struct spi_mem_op op =
 353                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0),
 354                                    SPI_MEM_OP_NO_ADDR,
 355                                    SPI_MEM_OP_NO_DUMMY,
 356                                    SPI_MEM_OP_NO_DATA);
 357
 358                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 359
 360                 ret = spi_mem_exec_op(nor->spimem, &op);
 361         } else {
 362                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
 363                                                        NULL, 0);
 364         }
 365
 366         if (ret)
 367                 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
 368
 369         return ret;
 370 }
 371
 372 /**
 373  * spi_nor_read_sr() - Read the Status Register.
 374  * @nor:        pointer to 'struct spi_nor'.
 375  * @sr:         pointer to a DMA-able buffer where the value of the
 376  *              Status Register will be written. Should be at least 2 bytes.
 377  *
 378  * Return: 0 on success, -errno otherwise.
 379  */
 380 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
 381 {
 382         int ret;
 383
 384         if (nor->spimem) {
 385                 struct spi_mem_op op =
 386                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
 387                                    SPI_MEM_OP_NO_ADDR,
 388                                    SPI_MEM_OP_NO_DUMMY,
 389                                    SPI_MEM_OP_DATA_IN(1, sr, 0));
 390
 391                 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
 392                         op.addr.nbytes = nor->params->rdsr_addr_nbytes;
 393                         op.dummy.nbytes = nor->params->rdsr_dummy;
 394                         /*
 395                          * We don't want to read only one byte in DTR mode. So,
 396                          * read 2 and then discard the second byte.
 397                          */
 398                         op.data.nbytes = 2;
 399                 }
 400
 401                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 402
 403                 ret = spi_mem_exec_op(nor->spimem, &op);
 404         } else {
 405                 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
 406                                                       1);
 407         }
 408
 409         if (ret)
 410                 dev_dbg(nor->dev, "error %d reading SR\n", ret);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * spi_nor_read_fsr() - Read the Flag Status Register.
 417  * @nor:        pointer to 'struct spi_nor'
 418  * @fsr:        pointer to a DMA-able buffer where the value of the
 419  *              Flag Status Register will be written. Should be at least 2
 420  *              bytes.
 421  *
 422  * Return: 0 on success, -errno otherwise.
 423  */
 424 static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
 425 {
 426         int ret;
 427
 428         if (nor->spimem) {
 429                 struct spi_mem_op op =
 430                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
 431                                    SPI_MEM_OP_NO_ADDR,
 432                                    SPI_MEM_OP_NO_DUMMY,
 433                                    SPI_MEM_OP_DATA_IN(1, fsr, 0));
 434
 435                 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
 436                         op.addr.nbytes = nor->params->rdsr_addr_nbytes;
 437                         op.dummy.nbytes = nor->params->rdsr_dummy;
 438                         /*
 439                          * We don't want to read only one byte in DTR mode. So,
 440                          * read 2 and then discard the second byte.
 441                          */
 442                         op.data.nbytes = 2;
 443                 }
 444
 445                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 446
 447                 ret = spi_mem_exec_op(nor->spimem, &op);
 448         } else {
 449                 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
 450                                                       1);
 451         }
 452
 453         if (ret)
 454                 dev_dbg(nor->dev, "error %d reading FSR\n", ret);
 455
 456         return ret;
 457 }
 458
 459 /**
 460  * spi_nor_read_cr() - Read the Configuration Register using the
 461  * SPINOR_OP_RDCR (35h) command.
 462  * @nor:        pointer to 'struct spi_nor'
 463  * @cr:         pointer to a DMA-able buffer where the value of the
 464  *              Configuration Register will be written.
 465  *
 466  * Return: 0 on success, -errno otherwise.
 467  */
 468 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
 469 {
 470         int ret;
 471
 472         if (nor->spimem) {
 473                 struct spi_mem_op op =
 474                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0),
 475                                    SPI_MEM_OP_NO_ADDR,
 476                                    SPI_MEM_OP_NO_DUMMY,
 477                                    SPI_MEM_OP_DATA_IN(1, cr, 0));
 478
 479                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 480
 481                 ret = spi_mem_exec_op(nor->spimem, &op);
 482         } else {
 483                 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
 484                                                       1);
 485         }
 486
 487         if (ret)
 488                 dev_dbg(nor->dev, "error %d reading CR\n", ret);
 489
 490         return ret;
 491 }
 492
 493 /**
 494  * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode.
 495  * @nor:        pointer to 'struct spi_nor'.
 496  * @enable:     true to enter the 4-byte address mode, false to exit the 4-byte
 497  *              address mode.
 498  *
 499  * Return: 0 on success, -errno otherwise.
 500  */
 501 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 502 {
 503         int ret;
 504
 505         if (nor->spimem) {
 506                 struct spi_mem_op op =
 507                         SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
 508                                                   SPINOR_OP_EN4B :
 509                                                   SPINOR_OP_EX4B,
 510                                                   0),
 511                                   SPI_MEM_OP_NO_ADDR,
 512                                   SPI_MEM_OP_NO_DUMMY,
 513                                   SPI_MEM_OP_NO_DATA);
 514
 515                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 516
 517                 ret = spi_mem_exec_op(nor->spimem, &op);
 518         } else {
 519                 ret = spi_nor_controller_ops_write_reg(nor,
 520                                                        enable ? SPINOR_OP_EN4B :
 521                                                                 SPINOR_OP_EX4B,
 522                                                        NULL, 0);
 523         }
 524
 525         if (ret)
 526                 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
 527
 528         return ret;
 529 }
 530
 531 /**
 532  * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion
 533  * flashes.
 534  * @nor:        pointer to 'struct spi_nor'.
 535  * @enable:     true to enter the 4-byte address mode, false to exit the 4-byte
 536  *              address mode.
 537  *
 538  * Return: 0 on success, -errno otherwise.
 539  */
 540 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 541 {
 542         int ret;
 543
 544         nor->bouncebuf[0] = enable << 7;
 545
 546         if (nor->spimem) {
 547                 struct spi_mem_op op =
 548                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0),
 549                                    SPI_MEM_OP_NO_ADDR,
 550                                    SPI_MEM_OP_NO_DUMMY,
 551                                    SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0));
 552
 553                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 554
 555                 ret = spi_mem_exec_op(nor->spimem, &op);
 556         } else {
 557                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
 558                                                        nor->bouncebuf, 1);
 559         }
 560
 561         if (ret)
 562                 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
 563
 564         return ret;
 565 }
 566
 567 /**
 568  * spi_nor_write_ear() - Write Extended Address Register.
 569  * @nor:        pointer to 'struct spi_nor'.
 570  * @ear:        value to write to the Extended Address Register.
 571  *
 572  * Return: 0 on success, -errno otherwise.
 573  */
 574 int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
 575 {
 576         int ret;
 577
 578         nor->bouncebuf[0] = ear;
 579
 580         if (nor->spimem) {
 581                 struct spi_mem_op op =
 582                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0),
 583                                    SPI_MEM_OP_NO_ADDR,
 584                                    SPI_MEM_OP_NO_DUMMY,
 585                                    SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0));
 586
 587                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 588
 589                 ret = spi_mem_exec_op(nor->spimem, &op);
 590         } else {
 591                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR,
 592                                                        nor->bouncebuf, 1);
 593         }
 594
 595         if (ret)
 596                 dev_dbg(nor->dev, "error %d writing EAR\n", ret);
 597
 598         return ret;
 599 }
 600
 601 /**
 602  * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
 603  * @nor:        pointer to 'struct spi_nor'.
 604  * @sr:         pointer to a DMA-able buffer where the value of the
 605  *              Status Register will be written.
 606  *
 607  * Return: 0 on success, -errno otherwise.
 608  */
 609 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
 610 {
 611         int ret;
 612
 613         if (nor->spimem) {
 614                 struct spi_mem_op op =
 615                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
 616                                    SPI_MEM_OP_NO_ADDR,
 617                                    SPI_MEM_OP_NO_DUMMY,
 618                                    SPI_MEM_OP_DATA_IN(1, sr, 0));
 619
 620                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 621
 622                 ret = spi_mem_exec_op(nor->spimem, &op);
 623         } else {
 624                 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
 625                                                       1);
 626         }
 627
 628         if (ret)
 629                 dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
 630
 631         return ret;
 632 }
 633
 634 /**
 635  * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
 636  * the flash is ready for new commands.
 637  * @nor:        pointer to 'struct spi_nor'.
 638  *
 639  * Return: 1 if ready, 0 if not ready, -errno on errors.
 640  */
 641 static int spi_nor_xsr_ready(struct spi_nor *nor)
 642 {
 643         int ret;
 644
 645         ret = spi_nor_xread_sr(nor, nor->bouncebuf);
 646         if (ret)
 647                 return ret;
 648
 649         return !!(nor->bouncebuf[0] & XSR_RDY);
 650 }
 651
 652 /**
 653  * spi_nor_clear_sr() - Clear the Status Register.
 654  * @nor:        pointer to 'struct spi_nor'.
 655  */
 656 static void spi_nor_clear_sr(struct spi_nor *nor)
 657 {
 658         int ret;
 659
 660         if (nor->spimem) {
 661                 struct spi_mem_op op =
 662                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
 663                                    SPI_MEM_OP_NO_ADDR,
 664                                    SPI_MEM_OP_NO_DUMMY,
 665                                    SPI_MEM_OP_NO_DATA);
 666
 667                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 668
 669                 ret = spi_mem_exec_op(nor->spimem, &op);
 670         } else {
 671                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
 672                                                        NULL, 0);
 673         }
 674
 675         if (ret)
 676                 dev_dbg(nor->dev, "error %d clearing SR\n", ret);
 677 }
 678
 679 /**
 680  * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
 681  * for new commands.
 682  * @nor:        pointer to 'struct spi_nor'.
 683  *
 684  * Return: 1 if ready, 0 if not ready, -errno on errors.
 685  */
 686 static int spi_nor_sr_ready(struct spi_nor *nor)
 687 {
 688         int ret = spi_nor_read_sr(nor, nor->bouncebuf);
 689
 690         if (ret)
 691                 return ret;
 692
 693         if (nor->flags & SNOR_F_USE_CLSR &&
 694             nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
 695                 if (nor->bouncebuf[0] & SR_E_ERR)
 696                         dev_err(nor->dev, "Erase Error occurred\n");
 697                 else
 698                         dev_err(nor->dev, "Programming Error occurred\n");
 699
 700                 spi_nor_clear_sr(nor);
 701
 702                 /*
 703                  * WEL bit remains set to one when an erase or page program
 704                  * error occurs. Issue a Write Disable command to protect
 705                  * against inadvertent writes that can possibly corrupt the
 706                  * contents of the memory.
 707                  */
 708                 ret = spi_nor_write_disable(nor);
 709                 if (ret)
 710                         return ret;
 711
 712                 return -EIO;
 713         }
 714
 715         return !(nor->bouncebuf[0] & SR_WIP);
 716 }
 717
 718 /**
 719  * spi_nor_clear_fsr() - Clear the Flag Status Register.
 720  * @nor:        pointer to 'struct spi_nor'.
 721  */
 722 static void spi_nor_clear_fsr(struct spi_nor *nor)
 723 {
 724         int ret;
 725
 726         if (nor->spimem) {
 727                 struct spi_mem_op op =
 728                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
 729                                    SPI_MEM_OP_NO_ADDR,
 730                                    SPI_MEM_OP_NO_DUMMY,
 731                                    SPI_MEM_OP_NO_DATA);
 732
 733                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 734
 735                 ret = spi_mem_exec_op(nor->spimem, &op);
 736         } else {
 737                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
 738                                                        NULL, 0);
 739         }
 740
 741         if (ret)
 742                 dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
 743 }
 744
 745 /**
 746  * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
 747  * ready for new commands.
 748  * @nor:        pointer to 'struct spi_nor'.
 749  *
 750  * Return: 1 if ready, 0 if not ready, -errno on errors.
 751  */
 752 static int spi_nor_fsr_ready(struct spi_nor *nor)
 753 {
 754         int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
 755
 756         if (ret)
 757                 return ret;
 758
 759         if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
 760                 if (nor->bouncebuf[0] & FSR_E_ERR)
 761                         dev_err(nor->dev, "Erase operation failed.\n");
 762                 else
 763                         dev_err(nor->dev, "Program operation failed.\n");
 764
 765                 if (nor->bouncebuf[0] & FSR_PT_ERR)
 766                         dev_err(nor->dev,
 767                         "Attempted to modify a protected sector.\n");
 768
 769                 spi_nor_clear_fsr(nor);
 770
 771                 /*
 772                  * WEL bit remains set to one when an erase or page program
 773                  * error occurs. Issue a Write Disable command to protect
 774                  * against inadvertent writes that can possibly corrupt the
 775                  * contents of the memory.
 776                  */
 777                 ret = spi_nor_write_disable(nor);
 778                 if (ret)
 779                         return ret;
 780
 781                 return -EIO;
 782         }
 783
 784         return !!(nor->bouncebuf[0] & FSR_READY);
 785 }
 786
 787 /**
 788  * spi_nor_ready() - Query the flash to see if it is ready for new commands.
 789  * @nor:        pointer to 'struct spi_nor'.
 790  *
 791  * Return: 1 if ready, 0 if not ready, -errno on errors.
 792  */
 793 static int spi_nor_ready(struct spi_nor *nor)
 794 {
 795         int sr, fsr;
 796
 797         if (nor->flags & SNOR_F_READY_XSR_RDY)
 798                 sr = spi_nor_xsr_ready(nor);
 799         else
 800                 sr = spi_nor_sr_ready(nor);
 801         if (sr < 0)
 802                 return sr;
 803         fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
 804         if (fsr < 0)
 805                 return fsr;
 806         return sr && fsr;
 807 }
 808
 809 /**
 810  * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
 811  * Status Register until ready, or timeout occurs.
 812  * @nor:                pointer to "struct spi_nor".
 813  * @timeout_jiffies:    jiffies to wait until timeout.
 814  *
 815  * Return: 0 on success, -errno otherwise.
 816  */
 817 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
 818                                                 unsigned long timeout_jiffies)
 819 {
 820         unsigned long deadline;
 821         int timeout = 0, ret;
 822
 823         deadline = jiffies + timeout_jiffies;
 824
 825         while (!timeout) {
 826                 if (time_after_eq(jiffies, deadline))
 827                         timeout = 1;
 828
 829                 ret = spi_nor_ready(nor);
 830                 if (ret < 0)
 831                         return ret;
 832                 if (ret)
 833                         return 0;
 834
 835                 cond_resched();
 836         }
 837
 838         dev_dbg(nor->dev, "flash operation timed out\n");
 839
 840         return -ETIMEDOUT;
 841 }
 842
 843 /**
 844  * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
 845  * flash to be ready, or timeout occurs.
 846  * @nor:        pointer to "struct spi_nor".
 847  *
 848  * Return: 0 on success, -errno otherwise.
 849  */
 850 int spi_nor_wait_till_ready(struct spi_nor *nor)
 851 {
 852         return spi_nor_wait_till_ready_with_timeout(nor,
 853                                                     DEFAULT_READY_WAIT_JIFFIES);
 854 }
 855
 856 /**
 857  * spi_nor_global_block_unlock() - Unlock Global Block Protection.
 858  * @nor:        pointer to 'struct spi_nor'.
 859  *
 860  * Return: 0 on success, -errno otherwise.
 861  */
 862 int spi_nor_global_block_unlock(struct spi_nor *nor)
 863 {
 864         int ret;
 865
 866         ret = spi_nor_write_enable(nor);
 867         if (ret)
 868                 return ret;
 869
 870         if (nor->spimem) {
 871                 struct spi_mem_op op =
 872                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0),
 873                                    SPI_MEM_OP_NO_ADDR,
 874                                    SPI_MEM_OP_NO_DUMMY,
 875                                    SPI_MEM_OP_NO_DATA);
 876
 877                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 878
 879                 ret = spi_mem_exec_op(nor->spimem, &op);
 880         } else {
 881                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
 882                                                        NULL, 0);
 883         }
 884
 885         if (ret) {
 886                 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
 887                 return ret;
 888         }
 889
 890         return spi_nor_wait_till_ready(nor);
 891 }
 892
 893 /**
 894  * spi_nor_write_sr() - Write the Status Register.
 895  * @nor:        pointer to 'struct spi_nor'.
 896  * @sr:         pointer to DMA-able buffer to write to the Status Register.
 897  * @len:        number of bytes to write to the Status Register.
 898  *
 899  * Return: 0 on success, -errno otherwise.
 900  */
 901 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
 902 {
 903         int ret;
 904
 905         ret = spi_nor_write_enable(nor);
 906         if (ret)
 907                 return ret;
 908
 909         if (nor->spimem) {
 910                 struct spi_mem_op op =
 911                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0),
 912                                    SPI_MEM_OP_NO_ADDR,
 913                                    SPI_MEM_OP_NO_DUMMY,
 914                                    SPI_MEM_OP_DATA_OUT(len, sr, 0));
 915
 916                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 917
 918                 ret = spi_mem_exec_op(nor->spimem, &op);
 919         } else {
 920                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
 921                                                        len);
 922         }
 923
 924         if (ret) {
 925                 dev_dbg(nor->dev, "error %d writing SR\n", ret);
 926                 return ret;
 927         }
 928
 929         return spi_nor_wait_till_ready(nor);
 930 }
 931
 932 /**
 933  * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
 934  * ensure that the byte written match the received value.
 935  * @nor:        pointer to a 'struct spi_nor'.
 936  * @sr1:        byte value to be written to the Status Register.
 937  *
 938  * Return: 0 on success, -errno otherwise.
 939  */
 940 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
 941 {
 942         int ret;
 943
 944         nor->bouncebuf[0] = sr1;
 945
 946         ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
 947         if (ret)
 948                 return ret;
 949
 950         ret = spi_nor_read_sr(nor, nor->bouncebuf);
 951         if (ret)
 952                 return ret;
 953
 954         if (nor->bouncebuf[0] != sr1) {
 955                 dev_dbg(nor->dev, "SR1: read back test failed\n");
 956                 return -EIO;
 957         }
 958
 959         return 0;
 960 }
 961
 962 /**
 963  * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
 964  * Status Register 2 in one shot. Ensure that the byte written in the Status
 965  * Register 1 match the received value, and that the 16-bit Write did not
 966  * affect what was already in the Status Register 2.
 967  * @nor:        pointer to a 'struct spi_nor'.
 968  * @sr1:        byte value to be written to the Status Register 1.
 969  *
 970  * Return: 0 on success, -errno otherwise.
 971  */
 972 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
 973 {
 974         int ret;
 975         u8 *sr_cr = nor->bouncebuf;
 976         u8 cr_written;
 977
 978         /* Make sure we don't overwrite the contents of Status Register 2. */
 979         if (!(nor->flags & SNOR_F_NO_READ_CR)) {
 980                 ret = spi_nor_read_cr(nor, &sr_cr[1]);
 981                 if (ret)
 982                         return ret;
 983         } else if (nor->params->quad_enable) {
 984                 /*
 985                  * If the Status Register 2 Read command (35h) is not
 986                  * supported, we should at least be sure we don't
 987                  * change the value of the SR2 Quad Enable bit.
 988                  *
 989                  * We can safely assume that when the Quad Enable method is
 990                  * set, the value of the QE bit is one, as a consequence of the
 991                  * nor->params->quad_enable() call.
 992                  *
 993                  * We can safely assume that the Quad Enable bit is present in
 994                  * the Status Register 2 at BIT(1). According to the JESD216
 995                  * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
 996                  * Write Status (01h) command is available just for the cases
 997                  * in which the QE bit is described in SR2 at BIT(1).
 998                  */
 999                 sr_cr[1] = SR2_QUAD_EN_BIT1;
1000         } else {
1001                 sr_cr[1] = 0;
1002         }
1003
1004         sr_cr[0] = sr1;
1005
1006         ret = spi_nor_write_sr(nor, sr_cr, 2);
1007         if (ret)
1008                 return ret;
1009
1010         ret = spi_nor_read_sr(nor, sr_cr);
1011         if (ret)
1012                 return ret;
1013
1014         if (sr1 != sr_cr[0]) {
1015                 dev_dbg(nor->dev, "SR: Read back test failed\n");
1016                 return -EIO;
1017         }
1018
1019         if (nor->flags & SNOR_F_NO_READ_CR)
1020                 return 0;
1021
1022         cr_written = sr_cr[1];
1023
1024         ret = spi_nor_read_cr(nor, &sr_cr[1]);
1025         if (ret)
1026                 return ret;
1027
1028         if (cr_written != sr_cr[1]) {
1029                 dev_dbg(nor->dev, "CR: read back test failed\n");
1030                 return -EIO;
1031         }
1032
1033         return 0;
1034 }
1035
1036 /**
1037  * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
1038  * Configuration Register in one shot. Ensure that the byte written in the
1039  * Configuration Register match the received value, and that the 16-bit Write
1040  * did not affect what was already in the Status Register 1.
1041  * @nor:        pointer to a 'struct spi_nor'.
1042  * @cr:         byte value to be written to the Configuration Register.
1043  *
1044  * Return: 0 on success, -errno otherwise.
1045  */
1046 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
1047 {
1048         int ret;
1049         u8 *sr_cr = nor->bouncebuf;
1050         u8 sr_written;
1051
1052         /* Keep the current value of the Status Register 1. */
1053         ret = spi_nor_read_sr(nor, sr_cr);
1054         if (ret)
1055                 return ret;
1056
1057         sr_cr[1] = cr;
1058
1059         ret = spi_nor_write_sr(nor, sr_cr, 2);
1060         if (ret)
1061                 return ret;
1062
1063         sr_written = sr_cr[0];
1064
1065         ret = spi_nor_read_sr(nor, sr_cr);
1066         if (ret)
1067                 return ret;
1068
1069         if (sr_written != sr_cr[0]) {
1070                 dev_dbg(nor->dev, "SR: Read back test failed\n");
1071                 return -EIO;
1072         }
1073
1074         if (nor->flags & SNOR_F_NO_READ_CR)
1075                 return 0;
1076
1077         ret = spi_nor_read_cr(nor, &sr_cr[1]);
1078         if (ret)
1079                 return ret;
1080
1081         if (cr != sr_cr[1]) {
1082                 dev_dbg(nor->dev, "CR: read back test failed\n");
1083                 return -EIO;
1084         }
1085
1086         return 0;
1087 }
1088
1089 /**
1090  * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
1091  * the byte written match the received value without affecting other bits in the
1092  * Status Register 1 and 2.
1093  * @nor:        pointer to a 'struct spi_nor'.
1094  * @sr1:        byte value to be written to the Status Register.
1095  *
1096  * Return: 0 on success, -errno otherwise.
1097  */
1098 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
1099 {
1100         if (nor->flags & SNOR_F_HAS_16BIT_SR)
1101                 return spi_nor_write_16bit_sr_and_check(nor, sr1);
1102
1103         return spi_nor_write_sr1_and_check(nor, sr1);
1104 }
1105
1106 /**
1107  * spi_nor_write_sr2() - Write the Status Register 2 using the
1108  * SPINOR_OP_WRSR2 (3eh) command.
1109  * @nor:        pointer to 'struct spi_nor'.
1110  * @sr2:        pointer to DMA-able buffer to write to the Status Register 2.
1111  *
1112  * Return: 0 on success, -errno otherwise.
1113  */
1114 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
1115 {
1116         int ret;
1117
1118         ret = spi_nor_write_enable(nor);
1119         if (ret)
1120                 return ret;
1121
1122         if (nor->spimem) {
1123                 struct spi_mem_op op =
1124                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0),
1125                                    SPI_MEM_OP_NO_ADDR,
1126                                    SPI_MEM_OP_NO_DUMMY,
1127                                    SPI_MEM_OP_DATA_OUT(1, sr2, 0));
1128
1129                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1130
1131                 ret = spi_mem_exec_op(nor->spimem, &op);
1132         } else {
1133                 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
1134                                                        sr2, 1);
1135         }
1136
1137         if (ret) {
1138                 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
1139                 return ret;
1140         }
1141
1142         return spi_nor_wait_till_ready(nor);
1143 }
1144
1145 /**
1146  * spi_nor_read_sr2() - Read the Status Register 2 using the
1147  * SPINOR_OP_RDSR2 (3fh) command.
1148  * @nor:        pointer to 'struct spi_nor'.
1149  * @sr2:        pointer to DMA-able buffer where the value of the
1150  *              Status Register 2 will be written.
1151  *
1152  * Return: 0 on success, -errno otherwise.
1153  */
1154 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1155 {
1156         int ret;
1157
1158         if (nor->spimem) {
1159                 struct spi_mem_op op =
1160                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0),
1161                                    SPI_MEM_OP_NO_ADDR,
1162                                    SPI_MEM_OP_NO_DUMMY,
1163                                    SPI_MEM_OP_DATA_IN(1, sr2, 0));
1164
1165                 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1166
1167                 ret = spi_mem_exec_op(nor->spimem, &op);
1168         } else {
1169                 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
1170                                                       1);
1171         }
1172
1173         if (ret)
1174                 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1175
1176         return ret;
1177 }
1178
1179 /**
1180  * spi_nor_erase_chip() - Erase the entire flash memory.
1181  * @nor:        pointer to 'struct spi_nor'.
1182  *
1183  * Return: 0 on success, -errno otherwise.
1184  */
1185 static int spi_nor_erase_chip(struct spi_nor *nor)
1186 {
1187         int ret;
1188
1189         dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
1190
1191         if (nor->spimem) {
1192                 struct spi_mem_op op =
1193                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0),
1194                                    SPI_MEM_OP_NO_ADDR,
1195                                    SPI_MEM_OP_NO_DUMMY,
1196                                    SPI_MEM_OP_NO_DATA);
1197
1198                 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
1199
1200                 ret = spi_mem_exec_op(nor->spimem, &op);
1201         } else {
1202                 ret = spi_nor_controller_ops_write_reg(nor,
1203                                                        SPINOR_OP_CHIP_ERASE,
1204                                                        NULL, 0);
1205         }
1206
1207         if (ret)
1208                 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1209
1210         return ret;
1211 }
1212
1213 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1214 {
1215         size_t i;
1216
1217         for (i = 0; i < size; i++)
1218                 if (table[i][0] == opcode)
1219                         return table[i][1];
1220
1221         /* No conversion found, keep input op code. */
1222         return opcode;
1223 }
1224
1225 u8 spi_nor_convert_3to4_read(u8 opcode)
1226 {
1227         static const u8 spi_nor_3to4_read[][2] = {
1228                 { SPINOR_OP_READ,       SPINOR_OP_READ_4B },
1229                 { SPINOR_OP_READ_FAST,  SPINOR_OP_READ_FAST_4B },
1230                 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1231                 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1232                 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1233                 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1234                 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1235                 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1236
1237                 { SPINOR_OP_READ_1_1_1_DTR,     SPINOR_OP_READ_1_1_1_DTR_4B },
1238                 { SPINOR_OP_READ_1_2_2_DTR,     SPINOR_OP_READ_1_2_2_DTR_4B },
1239                 { SPINOR_OP_READ_1_4_4_DTR,     SPINOR_OP_READ_1_4_4_DTR_4B },
1240         };
1241
1242         return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1243                                       ARRAY_SIZE(spi_nor_3to4_read));
1244 }
1245
1246 static u8 spi_nor_convert_3to4_program(u8 opcode)
1247 {
1248         static const u8 spi_nor_3to4_program[][2] = {
1249                 { SPINOR_OP_PP,         SPINOR_OP_PP_4B },
1250                 { SPINOR_OP_PP_1_1_4,   SPINOR_OP_PP_1_1_4_4B },
1251                 { SPINOR_OP_PP_1_4_4,   SPINOR_OP_PP_1_4_4_4B },
1252                 { SPINOR_OP_PP_1_1_8,   SPINOR_OP_PP_1_1_8_4B },
1253                 { SPINOR_OP_PP_1_8_8,   SPINOR_OP_PP_1_8_8_4B },
1254         };
1255
1256         return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1257                                       ARRAY_SIZE(spi_nor_3to4_program));
1258 }
1259
1260 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1261 {
1262         static const u8 spi_nor_3to4_erase[][2] = {
1263                 { SPINOR_OP_BE_4K,      SPINOR_OP_BE_4K_4B },
1264                 { SPINOR_OP_BE_32K,     SPINOR_OP_BE_32K_4B },
1265                 { SPINOR_OP_SE,         SPINOR_OP_SE_4B },
1266         };
1267
1268         return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1269                                       ARRAY_SIZE(spi_nor_3to4_erase));
1270 }
1271
1272 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1273 {
1274         return !!nor->params->erase_map.uniform_erase_type;
1275 }
1276
1277 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1278 {
1279         nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1280         nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1281         nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1282
1283         if (!spi_nor_has_uniform_erase(nor)) {
1284                 struct spi_nor_erase_map *map = &nor->params->erase_map;
1285                 struct spi_nor_erase_type *erase;
1286                 int i;
1287
1288                 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1289                         erase = &map->erase_type[i];
1290                         erase->opcode =
1291                                 spi_nor_convert_3to4_erase(erase->opcode);
1292                 }
1293         }
1294 }
1295
1296 int spi_nor_lock_and_prep(struct spi_nor *nor)
1297 {
1298         int ret = 0;
1299
1300         mutex_lock(&nor->lock);
1301
1302         if (nor->controller_ops &&  nor->controller_ops->prepare) {
1303                 ret = nor->controller_ops->prepare(nor);
1304                 if (ret) {
1305                         mutex_unlock(&nor->lock);
1306                         return ret;
1307                 }
1308         }
1309         return ret;
1310 }
1311
1312 void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1313 {
1314         if (nor->controller_ops && nor->controller_ops->unprepare)
1315                 nor->controller_ops->unprepare(nor);
1316         mutex_unlock(&nor->lock);
1317 }
1318
1319 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1320 {
1321         if (!nor->params->convert_addr)
1322                 return addr;
1323
1324         return nor->params->convert_addr(nor, addr);
1325 }
1326
1327 /*
1328  * Initiate the erasure of a single sector
1329  */
1330 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1331 {
1332         int i;
1333
1334         addr = spi_nor_convert_addr(nor, addr);
1335
1336         if (nor->spimem) {
1337                 struct spi_mem_op op =
1338                         SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
1339                                    SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
1340                                    SPI_MEM_OP_NO_DUMMY,
1341                                    SPI_MEM_OP_NO_DATA);
1342
1343                 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
1344
1345                 return spi_mem_exec_op(nor->spimem, &op);
1346         } else if (nor->controller_ops->erase) {
1347                 return spi_nor_controller_ops_erase(nor, addr);
1348         }
1349
1350         /*
1351          * Default implementation, if driver doesn't have a specialized HW
1352          * control
1353          */
1354         for (i = nor->addr_width - 1; i >= 0; i--) {
1355                 nor->bouncebuf[i] = addr & 0xff;
1356                 addr >>= 8;
1357         }
1358
1359         return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
1360                                                 nor->bouncebuf, nor->addr_width);
1361 }
1362
1363 /**
1364  * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1365  * @erase:      pointer to a structure that describes a SPI NOR erase type
1366  * @dividend:   dividend value
1367  * @remainder:  pointer to u32 remainder (will be updated)
1368  *
1369  * Return: the result of the division
1370  */
1371 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1372                                      u64 dividend, u32 *remainder)
1373 {
1374         /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1375         *remainder = (u32)dividend & erase->size_mask;
1376         return dividend >> erase->size_shift;
1377 }
1378
1379 /**
1380  * spi_nor_find_best_erase_type() - find the best erase type for the given
1381  *                                  offset in the serial flash memory and the
1382  *                                  number of bytes to erase. The region in
1383  *                                  which the address fits is expected to be
1384  *                                  provided.
1385  * @map:        the erase map of the SPI NOR
1386  * @region:     pointer to a structure that describes a SPI NOR erase region
1387  * @addr:       offset in the serial flash memory
1388  * @len:        number of bytes to erase
1389  *
1390  * Return: a pointer to the best fitted erase type, NULL otherwise.
1391  */
1392 static const struct spi_nor_erase_type *
1393 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1394                              const struct spi_nor_erase_region *region,
1395                              u64 addr, u32 len)
1396 {
1397         const struct spi_nor_erase_type *erase;
1398         u32 rem;
1399         int i;
1400         u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1401
1402         /*
1403          * Erase types are ordered by size, with the smallest erase type at
1404          * index 0.
1405          */
1406         for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1407                 /* Does the erase region support the tested erase type? */
1408                 if (!(erase_mask & BIT(i)))
1409                         continue;
1410
1411                 erase = &map->erase_type[i];
1412
1413                 /* Alignment is not mandatory for overlaid regions */
1414                 if (region->offset & SNOR_OVERLAID_REGION &&
1415                     region->size <= len)
1416                         return erase;
1417
1418                 /* Don't erase more than what the user has asked for. */
1419                 if (erase->size > len)
1420                         continue;
1421
1422                 spi_nor_div_by_erase_size(erase, addr, &rem);
1423                 if (!rem)
1424                         return erase;
1425         }
1426
1427         return NULL;
1428 }
1429
1430 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
1431 {
1432         return region->offset & SNOR_LAST_REGION;
1433 }
1434
1435 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region)
1436 {
1437         return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
1438 }
1439
1440 /**
1441  * spi_nor_region_next() - get the next spi nor region
1442  * @region:     pointer to a structure that describes a SPI NOR erase region
1443  *
1444  * Return: the next spi nor region or NULL if last region.
1445  */
1446 struct spi_nor_erase_region *
1447 spi_nor_region_next(struct spi_nor_erase_region *region)
1448 {
1449         if (spi_nor_region_is_last(region))
1450                 return NULL;
1451         region++;
1452         return region;
1453 }
1454
1455 /**
1456  * spi_nor_find_erase_region() - find the region of the serial flash memory in
1457  *                               which the offset fits
1458  * @map:        the erase map of the SPI NOR
1459  * @addr:       offset in the serial flash memory
1460  *
1461  * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1462  *         otherwise.
1463  */
1464 static struct spi_nor_erase_region *
1465 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1466 {
1467         struct spi_nor_erase_region *region = map->regions;
1468         u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1469         u64 region_end = region_start + region->size;
1470
1471         while (addr < region_start || addr >= region_end) {
1472                 region = spi_nor_region_next(region);
1473                 if (!region)
1474                         return ERR_PTR(-EINVAL);
1475
1476                 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1477                 region_end = region_start + region->size;
1478         }
1479
1480         return region;
1481 }
1482
1483 /**
1484  * spi_nor_init_erase_cmd() - initialize an erase command
1485  * @region:     pointer to a structure that describes a SPI NOR erase region
1486  * @erase:      pointer to a structure that describes a SPI NOR erase type
1487  *
1488  * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1489  *         otherwise.
1490  */
1491 static struct spi_nor_erase_command *
1492 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1493                        const struct spi_nor_erase_type *erase)
1494 {
1495         struct spi_nor_erase_command *cmd;
1496
1497         cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1498         if (!cmd)
1499                 return ERR_PTR(-ENOMEM);
1500
1501         INIT_LIST_HEAD(&cmd->list);
1502         cmd->opcode = erase->opcode;
1503         cmd->count = 1;
1504
1505         if (region->offset & SNOR_OVERLAID_REGION)
1506                 cmd->size = region->size;
1507         else
1508                 cmd->size = erase->size;
1509
1510         return cmd;
1511 }
1512
1513 /**
1514  * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1515  * @erase_list: list of erase commands
1516  */
1517 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1518 {
1519         struct spi_nor_erase_command *cmd, *next;
1520
1521         list_for_each_entry_safe(cmd, next, erase_list, list) {
1522                 list_del(&cmd->list);
1523                 kfree(cmd);
1524         }
1525 }
1526
1527 /**
1528  * spi_nor_init_erase_cmd_list() - initialize erase command list
1529  * @nor:        pointer to a 'struct spi_nor'
1530  * @erase_list: list of erase commands to be executed once we validate that the
1531  *              erase can be performed
1532  * @addr:       offset in the serial flash memory
1533  * @len:        number of bytes to erase
1534  *
1535  * Builds the list of best fitted erase commands and verifies if the erase can
1536  * be performed.
1537  *
1538  * Return: 0 on success, -errno otherwise.
1539  */
1540 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1541                                        struct list_head *erase_list,
1542                                        u64 addr, u32 len)
1543 {
1544         const struct spi_nor_erase_map *map = &nor->params->erase_map;
1545         const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1546         struct spi_nor_erase_region *region;
1547         struct spi_nor_erase_command *cmd = NULL;
1548         u64 region_end;
1549         int ret = -EINVAL;
1550
1551         region = spi_nor_find_erase_region(map, addr);
1552         if (IS_ERR(region))
1553                 return PTR_ERR(region);
1554
1555         region_end = spi_nor_region_end(region);
1556
1557         while (len) {
1558                 erase = spi_nor_find_best_erase_type(map, region, addr, len);
1559                 if (!erase)
1560                         goto destroy_erase_cmd_list;
1561
1562                 if (prev_erase != erase ||
1563                     erase->size != cmd->size ||
1564                     region->offset & SNOR_OVERLAID_REGION) {
1565                         cmd = spi_nor_init_erase_cmd(region, erase);
1566                         if (IS_ERR(cmd)) {
1567                                 ret = PTR_ERR(cmd);
1568                                 goto destroy_erase_cmd_list;
1569                         }
1570
1571                         list_add_tail(&cmd->list, erase_list);
1572                 } else {
1573                         cmd->count++;
1574                 }
1575
1576                 addr += cmd->size;
1577                 len -= cmd->size;
1578
1579                 if (len && addr >= region_end) {
1580                         region = spi_nor_region_next(region);
1581                         if (!region)
1582                                 goto destroy_erase_cmd_list;
1583                         region_end = spi_nor_region_end(region);
1584                 }
1585
1586                 prev_erase = erase;
1587         }
1588
1589         return 0;
1590
1591 destroy_erase_cmd_list:
1592         spi_nor_destroy_erase_cmd_list(erase_list);
1593         return ret;
1594 }
1595
1596 /**
1597  * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1598  * @nor:        pointer to a 'struct spi_nor'
1599  * @addr:       offset in the serial flash memory
1600  * @len:        number of bytes to erase
1601  *
1602  * Build a list of best fitted erase commands and execute it once we validate
1603  * that the erase can be performed.
1604  *
1605  * Return: 0 on success, -errno otherwise.
1606  */
1607 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1608 {
1609         LIST_HEAD(erase_list);
1610         struct spi_nor_erase_command *cmd, *next;
1611         int ret;
1612
1613         ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1614         if (ret)
1615                 return ret;
1616
1617         list_for_each_entry_safe(cmd, next, &erase_list, list) {
1618                 nor->erase_opcode = cmd->opcode;
1619                 while (cmd->count) {
1620                         dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1621                                  cmd->size, cmd->opcode, cmd->count);
1622
1623                         ret = spi_nor_write_enable(nor);
1624                         if (ret)
1625                                 goto destroy_erase_cmd_list;
1626
1627                         ret = spi_nor_erase_sector(nor, addr);
1628                         if (ret)
1629                                 goto destroy_erase_cmd_list;
1630
1631                         ret = spi_nor_wait_till_ready(nor);
1632                         if (ret)
1633                                 goto destroy_erase_cmd_list;
1634
1635                         addr += cmd->size;
1636                         cmd->count--;
1637                 }
1638                 list_del(&cmd->list);
1639                 kfree(cmd);
1640         }
1641
1642         return 0;
1643
1644 destroy_erase_cmd_list:
1645         spi_nor_destroy_erase_cmd_list(&erase_list);
1646         return ret;
1647 }
1648
1649 /*
1650  * Erase an address range on the nor chip.  The address range may extend
1651  * one or more erase sectors. Return an error if there is a problem erasing.
1652  */
1653 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1654 {
1655         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1656         u32 addr, len;
1657         uint32_t rem;
1658         int ret;
1659
1660         dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1661                         (long long)instr->len);
1662
1663         if (spi_nor_has_uniform_erase(nor)) {
1664                 div_u64_rem(instr->len, mtd->erasesize, &rem);
1665                 if (rem)
1666                         return -EINVAL;
1667         }
1668
1669         addr = instr->addr;
1670         len = instr->len;
1671
1672         ret = spi_nor_lock_and_prep(nor);
1673         if (ret)
1674                 return ret;
1675
1676         /* whole-chip erase? */
1677         if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1678                 unsigned long timeout;
1679
1680                 ret = spi_nor_write_enable(nor);
1681                 if (ret)
1682                         goto erase_err;
1683
1684                 ret = spi_nor_erase_chip(nor);
1685                 if (ret)
1686                         goto erase_err;
1687
1688                 /*
1689                  * Scale the timeout linearly with the size of the flash, with
1690                  * a minimum calibrated to an old 2MB flash. We could try to
1691                  * pull these from CFI/SFDP, but these values should be good
1692                  * enough for now.
1693                  */
1694                 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1695                               CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1696                               (unsigned long)(mtd->size / SZ_2M));
1697                 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1698                 if (ret)
1699                         goto erase_err;
1700
1701         /* REVISIT in some cases we could speed up erasing large regions
1702          * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K.  We may have set up
1703          * to use "small sector erase", but that's not always optimal.
1704          */
1705
1706         /* "sector"-at-a-time erase */
1707         } else if (spi_nor_has_uniform_erase(nor)) {
1708                 while (len) {
1709                         ret = spi_nor_write_enable(nor);
1710                         if (ret)
1711                                 goto erase_err;
1712
1713                         ret = spi_nor_erase_sector(nor, addr);
1714                         if (ret)
1715                                 goto erase_err;
1716
1717                         ret = spi_nor_wait_till_ready(nor);
1718                         if (ret)
1719                                 goto erase_err;
1720
1721                         addr += mtd->erasesize;
1722                         len -= mtd->erasesize;
1723                 }
1724
1725         /* erase multiple sectors */
1726         } else {
1727                 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1728                 if (ret)
1729                         goto erase_err;
1730         }
1731
1732         ret = spi_nor_write_disable(nor);
1733
1734 erase_err:
1735         spi_nor_unlock_and_unprep(nor);
1736
1737         return ret;
1738 }
1739
1740 /**
1741  * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1742  * Register 1.
1743  * @nor:        pointer to a 'struct spi_nor'
1744  *
1745  * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1746  *
1747  * Return: 0 on success, -errno otherwise.
1748  */
1749 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1750 {
1751         int ret;
1752
1753         ret = spi_nor_read_sr(nor, nor->bouncebuf);
1754         if (ret)
1755                 return ret;
1756
1757         if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1758                 return 0;
1759
1760         nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1761
1762         return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1763 }
1764
1765 /**
1766  * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1767  * Register 2.
1768  * @nor:       pointer to a 'struct spi_nor'.
1769  *
1770  * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1771  *
1772  * Return: 0 on success, -errno otherwise.
1773  */
1774 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1775 {
1776         int ret;
1777
1778         if (nor->flags & SNOR_F_NO_READ_CR)
1779                 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1780
1781         ret = spi_nor_read_cr(nor, nor->bouncebuf);
1782         if (ret)
1783                 return ret;
1784
1785         if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1786                 return 0;
1787
1788         nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1789
1790         return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1791 }
1792
1793 /**
1794  * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1795  * @nor:        pointer to a 'struct spi_nor'
1796  *
1797  * Set the Quad Enable (QE) bit in the Status Register 2.
1798  *
1799  * This is one of the procedures to set the QE bit described in the SFDP
1800  * (JESD216 rev B) specification but no manufacturer using this procedure has
1801  * been identified yet, hence the name of the function.
1802  *
1803  * Return: 0 on success, -errno otherwise.
1804  */
1805 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1806 {
1807         u8 *sr2 = nor->bouncebuf;
1808         int ret;
1809         u8 sr2_written;
1810
1811         /* Check current Quad Enable bit value. */
1812         ret = spi_nor_read_sr2(nor, sr2);
1813         if (ret)
1814                 return ret;
1815         if (*sr2 & SR2_QUAD_EN_BIT7)
1816                 return 0;
1817
1818         /* Update the Quad Enable bit. */
1819         *sr2 |= SR2_QUAD_EN_BIT7;
1820
1821         ret = spi_nor_write_sr2(nor, sr2);
1822         if (ret)
1823                 return ret;
1824
1825         sr2_written = *sr2;
1826
1827         /* Read back and check it. */
1828         ret = spi_nor_read_sr2(nor, sr2);
1829         if (ret)
1830                 return ret;
1831
1832         if (*sr2 != sr2_written) {
1833                 dev_dbg(nor->dev, "SR2: Read back test failed\n");
1834                 return -EIO;
1835         }
1836
1837         return 0;
1838 }
1839
1840 static const struct spi_nor_manufacturer *manufacturers[] = {
1841         &spi_nor_atmel,
1842         &spi_nor_catalyst,
1843         &spi_nor_eon,
1844         &spi_nor_esmt,
1845         &spi_nor_everspin,
1846         &spi_nor_fujitsu,
1847         &spi_nor_gigadevice,
1848         &spi_nor_intel,
1849         &spi_nor_issi,
1850         &spi_nor_macronix,
1851         &spi_nor_micron,
1852         &spi_nor_st,
1853         &spi_nor_spansion,
1854         &spi_nor_sst,
1855         &spi_nor_winbond,
1856         &spi_nor_xilinx,
1857         &spi_nor_xmc,
1858 };
1859
1860 static const struct flash_info *
1861 spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts,
1862                           const u8 *id)
1863 {
1864         unsigned int i;
1865
1866         for (i = 0; i < nparts; i++) {
1867                 if (parts[i].id_len &&
1868                     !memcmp(parts[i].id, id, parts[i].id_len))
1869                         return &parts[i];
1870         }
1871
1872         return NULL;
1873 }
1874
1875 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1876 {
1877         const struct flash_info *info;
1878         u8 *id = nor->bouncebuf;
1879         unsigned int i;
1880         int ret;
1881
1882         if (nor->spimem) {
1883                 struct spi_mem_op op =
1884                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
1885                                    SPI_MEM_OP_NO_ADDR,
1886                                    SPI_MEM_OP_NO_DUMMY,
1887                                    SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1));
1888
1889                 ret = spi_mem_exec_op(nor->spimem, &op);
1890         } else {
1891                 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
1892                                                     SPI_NOR_MAX_ID_LEN);
1893         }
1894         if (ret) {
1895                 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
1896                 return ERR_PTR(ret);
1897         }
1898
1899         for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
1900                 info = spi_nor_search_part_by_id(manufacturers[i]->parts,
1901                                                  manufacturers[i]->nparts,
1902                                                  id);
1903                 if (info) {
1904                         nor->manufacturer = manufacturers[i];
1905                         return info;
1906                 }
1907         }
1908
1909         dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
1910                 SPI_NOR_MAX_ID_LEN, id);
1911         return ERR_PTR(-ENODEV);
1912 }
1913
1914 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1915                         size_t *retlen, u_char *buf)
1916 {
1917         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1918         ssize_t ret;
1919
1920         dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1921
1922         ret = spi_nor_lock_and_prep(nor);
1923         if (ret)
1924                 return ret;
1925
1926         while (len) {
1927                 loff_t addr = from;
1928
1929                 addr = spi_nor_convert_addr(nor, addr);
1930
1931                 ret = spi_nor_read_data(nor, addr, len, buf);
1932                 if (ret == 0) {
1933                         /* We shouldn't see 0-length reads */
1934                         ret = -EIO;
1935                         goto read_err;
1936                 }
1937                 if (ret < 0)
1938                         goto read_err;
1939
1940                 WARN_ON(ret > len);
1941                 *retlen += ret;
1942                 buf += ret;
1943                 from += ret;
1944                 len -= ret;
1945         }
1946         ret = 0;
1947
1948 read_err:
1949         spi_nor_unlock_and_unprep(nor);
1950         return ret;
1951 }
1952
1953 /*
1954  * Write an address range to the nor chip.  Data must be written in
1955  * FLASH_PAGESIZE chunks.  The address range may be any size provided
1956  * it is within the physical boundaries.
1957  */
1958 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1959         size_t *retlen, const u_char *buf)
1960 {
1961         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1962         size_t page_offset, page_remain, i;
1963         ssize_t ret;
1964
1965         dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1966
1967         ret = spi_nor_lock_and_prep(nor);
1968         if (ret)
1969                 return ret;
1970
1971         for (i = 0; i < len; ) {
1972                 ssize_t written;
1973                 loff_t addr = to + i;
1974
1975                 /*
1976                  * If page_size is a power of two, the offset can be quickly
1977                  * calculated with an AND operation. On the other cases we
1978                  * need to do a modulus operation (more expensive).
1979                  */
1980                 if (is_power_of_2(nor->page_size)) {
1981                         page_offset = addr & (nor->page_size - 1);
1982                 } else {
1983                         uint64_t aux = addr;
1984
1985                         page_offset = do_div(aux, nor->page_size);
1986                 }
1987                 /* the size of data remaining on the first page */
1988                 page_remain = min_t(size_t,
1989                                     nor->page_size - page_offset, len - i);
1990
1991                 addr = spi_nor_convert_addr(nor, addr);
1992
1993                 ret = spi_nor_write_enable(nor);
1994                 if (ret)
1995                         goto write_err;
1996
1997                 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
1998                 if (ret < 0)
1999                         goto write_err;
2000                 written = ret;
2001
2002                 ret = spi_nor_wait_till_ready(nor);
2003                 if (ret)
2004                         goto write_err;
2005                 *retlen += written;
2006                 i += written;
2007         }
2008
2009 write_err:
2010         spi_nor_unlock_and_unprep(nor);
2011         return ret;
2012 }
2013
2014 static int spi_nor_check(struct spi_nor *nor)
2015 {
2016         if (!nor->dev ||
2017             (!nor->spimem && !nor->controller_ops) ||
2018             (!nor->spimem && nor->controller_ops &&
2019             (!nor->controller_ops->read ||
2020              !nor->controller_ops->write ||
2021              !nor->controller_ops->read_reg ||
2022              !nor->controller_ops->write_reg))) {
2023                 pr_err("spi-nor: please fill all the necessary fields!\n");
2024                 return -EINVAL;
2025         }
2026
2027         if (nor->spimem && nor->controller_ops) {
2028                 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2029                 return -EINVAL;
2030         }
2031
2032         return 0;
2033 }
2034
2035 void
2036 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2037                           u8 num_mode_clocks,
2038                           u8 num_wait_states,
2039                           u8 opcode,
2040                           enum spi_nor_protocol proto)
2041 {
2042         read->num_mode_clocks = num_mode_clocks;
2043         read->num_wait_states = num_wait_states;
2044         read->opcode = opcode;
2045         read->proto = proto;
2046 }
2047
2048 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2049                              enum spi_nor_protocol proto)
2050 {
2051         pp->opcode = opcode;
2052         pp->proto = proto;
2053 }
2054
2055 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2056 {
2057         size_t i;
2058
2059         for (i = 0; i < size; i++)
2060                 if (table[i][0] == (int)hwcaps)
2061                         return table[i][1];
2062
2063         return -EINVAL;
2064 }
2065
2066 int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2067 {
2068         static const int hwcaps_read2cmd[][2] = {
2069                 { SNOR_HWCAPS_READ,             SNOR_CMD_READ },
2070                 { SNOR_HWCAPS_READ_FAST,        SNOR_CMD_READ_FAST },
2071                 { SNOR_HWCAPS_READ_1_1_1_DTR,   SNOR_CMD_READ_1_1_1_DTR },
2072                 { SNOR_HWCAPS_READ_1_1_2,       SNOR_CMD_READ_1_1_2 },
2073                 { SNOR_HWCAPS_READ_1_2_2,       SNOR_CMD_READ_1_2_2 },
2074                 { SNOR_HWCAPS_READ_2_2_2,       SNOR_CMD_READ_2_2_2 },
2075                 { SNOR_HWCAPS_READ_1_2_2_DTR,   SNOR_CMD_READ_1_2_2_DTR },
2076                 { SNOR_HWCAPS_READ_1_1_4,       SNOR_CMD_READ_1_1_4 },
2077                 { SNOR_HWCAPS_READ_1_4_4,       SNOR_CMD_READ_1_4_4 },
2078                 { SNOR_HWCAPS_READ_4_4_4,       SNOR_CMD_READ_4_4_4 },
2079                 { SNOR_HWCAPS_READ_1_4_4_DTR,   SNOR_CMD_READ_1_4_4_DTR },
2080                 { SNOR_HWCAPS_READ_1_1_8,       SNOR_CMD_READ_1_1_8 },
2081                 { SNOR_HWCAPS_READ_1_8_8,       SNOR_CMD_READ_1_8_8 },
2082                 { SNOR_HWCAPS_READ_8_8_8,       SNOR_CMD_READ_8_8_8 },
2083                 { SNOR_HWCAPS_READ_1_8_8_DTR,   SNOR_CMD_READ_1_8_8_DTR },
2084                 { SNOR_HWCAPS_READ_8_8_8_DTR,   SNOR_CMD_READ_8_8_8_DTR },
2085         };
2086
2087         return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2088                                   ARRAY_SIZE(hwcaps_read2cmd));
2089 }
2090
2091 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2092 {
2093         static const int hwcaps_pp2cmd[][2] = {
2094                 { SNOR_HWCAPS_PP,               SNOR_CMD_PP },
2095                 { SNOR_HWCAPS_PP_1_1_4,         SNOR_CMD_PP_1_1_4 },
2096                 { SNOR_HWCAPS_PP_1_4_4,         SNOR_CMD_PP_1_4_4 },
2097                 { SNOR_HWCAPS_PP_4_4_4,         SNOR_CMD_PP_4_4_4 },
2098                 { SNOR_HWCAPS_PP_1_1_8,         SNOR_CMD_PP_1_1_8 },
2099                 { SNOR_HWCAPS_PP_1_8_8,         SNOR_CMD_PP_1_8_8 },
2100                 { SNOR_HWCAPS_PP_8_8_8,         SNOR_CMD_PP_8_8_8 },
2101                 { SNOR_HWCAPS_PP_8_8_8_DTR,     SNOR_CMD_PP_8_8_8_DTR },
2102         };
2103
2104         return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2105                                   ARRAY_SIZE(hwcaps_pp2cmd));
2106 }
2107
2108 /**
2109  * spi_nor_spimem_check_op - check if the operation is supported
2110  *                           by controller
2111  *@nor:        pointer to a 'struct spi_nor'
2112  *@op:         pointer to op template to be checked
2113  *
2114  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2115  */
2116 static int spi_nor_spimem_check_op(struct spi_nor *nor,
2117                                    struct spi_mem_op *op)
2118 {
2119         /*
2120          * First test with 4 address bytes. The opcode itself might
2121          * be a 3B addressing opcode but we don't care, because
2122          * SPI controller implementation should not check the opcode,
2123          * but just the sequence.
2124          */
2125         op->addr.nbytes = 4;
2126         if (!spi_mem_supports_op(nor->spimem, op)) {
2127                 if (nor->mtd.size > SZ_16M)
2128                         return -EOPNOTSUPP;
2129
2130                 /* If flash size <= 16MB, 3 address bytes are sufficient */
2131                 op->addr.nbytes = 3;
2132                 if (!spi_mem_supports_op(nor->spimem, op))
2133                         return -EOPNOTSUPP;
2134         }
2135
2136         return 0;
2137 }
2138
2139 /**
2140  * spi_nor_spimem_check_readop - check if the read op is supported
2141  *                               by controller
2142  *@nor:         pointer to a 'struct spi_nor'
2143  *@read:        pointer to op template to be checked
2144  *
2145  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2146  */
2147 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2148                                        const struct spi_nor_read_command *read)
2149 {
2150         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
2151                                           SPI_MEM_OP_ADDR(3, 0, 0),
2152                                           SPI_MEM_OP_DUMMY(1, 0),
2153                                           SPI_MEM_OP_DATA_IN(1, NULL, 0));
2154
2155         spi_nor_spimem_setup_op(nor, &op, read->proto);
2156
2157         /* convert the dummy cycles to the number of bytes */
2158         op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
2159         if (spi_nor_protocol_is_dtr(nor->read_proto))
2160                 op.dummy.nbytes *= 2;
2161
2162         return spi_nor_spimem_check_op(nor, &op);
2163 }
2164
2165 /**
2166  * spi_nor_spimem_check_pp - check if the page program op is supported
2167  *                           by controller
2168  *@nor:         pointer to a 'struct spi_nor'
2169  *@pp:          pointer to op template to be checked
2170  *
2171  * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2172  */
2173 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2174                                    const struct spi_nor_pp_command *pp)
2175 {
2176         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
2177                                           SPI_MEM_OP_ADDR(3, 0, 0),
2178                                           SPI_MEM_OP_NO_DUMMY,
2179                                           SPI_MEM_OP_DATA_OUT(1, NULL, 0));
2180
2181         spi_nor_spimem_setup_op(nor, &op, pp->proto);
2182
2183         return spi_nor_spimem_check_op(nor, &op);
2184 }
2185
2186 /**
2187  * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2188  *                                based on SPI controller capabilities
2189  * @nor:        pointer to a 'struct spi_nor'
2190  * @hwcaps:     pointer to resulting capabilities after adjusting
2191  *              according to controller and flash's capability
2192  */
2193 static void
2194 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
2195 {
2196         struct spi_nor_flash_parameter *params = nor->params;
2197         unsigned int cap;
2198
2199         /* X-X-X modes are not supported yet, mask them all. */
2200         *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2201
2202         /*
2203          * If the reset line is broken, we do not want to enter a stateful
2204          * mode.
2205          */
2206         if (nor->flags & SNOR_F_BROKEN_RESET)
2207                 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2208
2209         for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2210                 int rdidx, ppidx;
2211
2212                 if (!(*hwcaps & BIT(cap)))
2213                         continue;
2214
2215                 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2216                 if (rdidx >= 0 &&
2217                     spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
2218                         *hwcaps &= ~BIT(cap);
2219
2220                 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2221                 if (ppidx < 0)
2222                         continue;
2223
2224                 if (spi_nor_spimem_check_pp(nor,
2225                                             &params->page_programs[ppidx]))
2226                         *hwcaps &= ~BIT(cap);
2227         }
2228 }
2229
2230 /**
2231  * spi_nor_set_erase_type() - set a SPI NOR erase type
2232  * @erase:      pointer to a structure that describes a SPI NOR erase type
2233  * @size:       the size of the sector/block erased by the erase type
2234  * @opcode:     the SPI command op code to erase the sector/block
2235  */
2236 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2237                             u8 opcode)
2238 {
2239         erase->size = size;
2240         erase->opcode = opcode;
2241         /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2242         erase->size_shift = ffs(erase->size) - 1;
2243         erase->size_mask = (1 << erase->size_shift) - 1;
2244 }
2245
2246 /**
2247  * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2248  * @map:                the erase map of the SPI NOR
2249  * @erase_mask:         bitmask encoding erase types that can erase the entire
2250  *                      flash memory
2251  * @flash_size:         the spi nor flash memory size
2252  */
2253 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2254                                     u8 erase_mask, u64 flash_size)
2255 {
2256         /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
2257         map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
2258                                      SNOR_LAST_REGION;
2259         map->uniform_region.size = flash_size;
2260         map->regions = &map->uniform_region;
2261         map->uniform_erase_type = erase_mask;
2262 }
2263
2264 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2265                              const struct sfdp_parameter_header *bfpt_header,
2266                              const struct sfdp_bfpt *bfpt)
2267 {
2268         int ret;
2269
2270         if (nor->manufacturer && nor->manufacturer->fixups &&
2271             nor->manufacturer->fixups->post_bfpt) {
2272                 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2273                                                            bfpt);
2274                 if (ret)
2275                         return ret;
2276         }
2277
2278         if (nor->info->fixups && nor->info->fixups->post_bfpt)
2279                 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2280
2281         return 0;
2282 }
2283
2284 static int spi_nor_select_read(struct spi_nor *nor,
2285                                u32 shared_hwcaps)
2286 {
2287         int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2288         const struct spi_nor_read_command *read;
2289
2290         if (best_match < 0)
2291                 return -EINVAL;
2292
2293         cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2294         if (cmd < 0)
2295                 return -EINVAL;
2296
2297         read = &nor->params->reads[cmd];
2298         nor->read_opcode = read->opcode;
2299         nor->read_proto = read->proto;
2300
2301         /*
2302          * In the SPI NOR framework, we don't need to make the difference
2303          * between mode clock cycles and wait state clock cycles.
2304          * Indeed, the value of the mode clock cycles is used by a QSPI
2305          * flash memory to know whether it should enter or leave its 0-4-4
2306          * (Continuous Read / XIP) mode.
2307          * eXecution In Place is out of the scope of the mtd sub-system.
2308          * Hence we choose to merge both mode and wait state clock cycles
2309          * into the so called dummy clock cycles.
2310          */
2311         nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2312         return 0;
2313 }
2314
2315 static int spi_nor_select_pp(struct spi_nor *nor,
2316                              u32 shared_hwcaps)
2317 {
2318         int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2319         const struct spi_nor_pp_command *pp;
2320
2321         if (best_match < 0)
2322                 return -EINVAL;
2323
2324         cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2325         if (cmd < 0)
2326                 return -EINVAL;
2327
2328         pp = &nor->params->page_programs[cmd];
2329         nor->program_opcode = pp->opcode;
2330         nor->write_proto = pp->proto;
2331         return 0;
2332 }
2333
2334 /**
2335  * spi_nor_select_uniform_erase() - select optimum uniform erase type
2336  * @map:                the erase map of the SPI NOR
2337  * @wanted_size:        the erase type size to search for. Contains the value of
2338  *                      info->sector_size or of the "small sector" size in case
2339  *                      CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
2340  *
2341  * Once the optimum uniform sector erase command is found, disable all the
2342  * other.
2343  *
2344  * Return: pointer to erase type on success, NULL otherwise.
2345  */
2346 static const struct spi_nor_erase_type *
2347 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
2348                              const u32 wanted_size)
2349 {
2350         const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2351         int i;
2352         u8 uniform_erase_type = map->uniform_erase_type;
2353
2354         for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2355                 if (!(uniform_erase_type & BIT(i)))
2356                         continue;
2357
2358                 tested_erase = &map->erase_type[i];
2359
2360                 /*
2361                  * If the current erase size is the one, stop here:
2362                  * we have found the right uniform Sector Erase command.
2363                  */
2364                 if (tested_erase->size == wanted_size) {
2365                         erase = tested_erase;
2366                         break;
2367                 }
2368
2369                 /*
2370                  * Otherwise, the current erase size is still a valid candidate.
2371                  * Select the biggest valid candidate.
2372                  */
2373                 if (!erase && tested_erase->size)
2374                         erase = tested_erase;
2375                         /* keep iterating to find the wanted_size */
2376         }
2377
2378         if (!erase)
2379                 return NULL;
2380
2381         /* Disable all other Sector Erase commands. */
2382         map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
2383         map->uniform_erase_type |= BIT(erase - map->erase_type);
2384         return erase;
2385 }
2386
2387 static int spi_nor_select_erase(struct spi_nor *nor)
2388 {
2389         struct spi_nor_erase_map *map = &nor->params->erase_map;
2390         const struct spi_nor_erase_type *erase = NULL;
2391         struct mtd_info *mtd = &nor->mtd;
2392         u32 wanted_size = nor->info->sector_size;
2393         int i;
2394
2395         /*
2396          * The previous implementation handling Sector Erase commands assumed
2397          * that the SPI flash memory has an uniform layout then used only one
2398          * of the supported erase sizes for all Sector Erase commands.
2399          * So to be backward compatible, the new implementation also tries to
2400          * manage the SPI flash memory as uniform with a single erase sector
2401          * size, when possible.
2402          */
2403 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2404         /* prefer "small sector" erase if possible */
2405         wanted_size = 4096u;
2406 #endif
2407
2408         if (spi_nor_has_uniform_erase(nor)) {
2409                 erase = spi_nor_select_uniform_erase(map, wanted_size);
2410                 if (!erase)
2411                         return -EINVAL;
2412                 nor->erase_opcode = erase->opcode;
2413                 mtd->erasesize = erase->size;
2414                 return 0;
2415         }
2416
2417         /*
2418          * For non-uniform SPI flash memory, set mtd->erasesize to the
2419          * maximum erase sector size. No need to set nor->erase_opcode.
2420          */
2421         for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2422                 if (map->erase_type[i].size) {
2423                         erase = &map->erase_type[i];
2424                         break;
2425                 }
2426         }
2427
2428         if (!erase)
2429                 return -EINVAL;
2430
2431         mtd->erasesize = erase->size;
2432         return 0;
2433 }
2434
2435 static int spi_nor_default_setup(struct spi_nor *nor,
2436                                  const struct spi_nor_hwcaps *hwcaps)
2437 {
2438         struct spi_nor_flash_parameter *params = nor->params;
2439         u32 ignored_mask, shared_mask;
2440         int err;
2441
2442         /*
2443          * Keep only the hardware capabilities supported by both the SPI
2444          * controller and the SPI flash memory.
2445          */
2446         shared_mask = hwcaps->mask & params->hwcaps.mask;
2447
2448         if (nor->spimem) {
2449                 /*
2450                  * When called from spi_nor_probe(), all caps are set and we
2451                  * need to discard some of them based on what the SPI
2452                  * controller actually supports (using spi_mem_supports_op()).
2453                  */
2454                 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2455         } else {
2456                 /*
2457                  * SPI n-n-n protocols are not supported when the SPI
2458                  * controller directly implements the spi_nor interface.
2459                  * Yet another reason to switch to spi-mem.
2460                  */
2461                 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2462                 if (shared_mask & ignored_mask) {
2463                         dev_dbg(nor->dev,
2464                                 "SPI n-n-n protocols are not supported.\n");
2465                         shared_mask &= ~ignored_mask;
2466                 }
2467         }
2468
2469         /* Select the (Fast) Read command. */
2470         err = spi_nor_select_read(nor, shared_mask);
2471         if (err) {
2472                 dev_dbg(nor->dev,
2473                         "can't select read settings supported by both the SPI controller and memory.\n");
2474                 return err;
2475         }
2476
2477         /* Select the Page Program command. */
2478         err = spi_nor_select_pp(nor, shared_mask);
2479         if (err) {
2480                 dev_dbg(nor->dev,
2481                         "can't select write settings supported by both the SPI controller and memory.\n");
2482                 return err;
2483         }
2484
2485         /* Select the Sector Erase command. */
2486         err = spi_nor_select_erase(nor);
2487         if (err) {
2488                 dev_dbg(nor->dev,
2489                         "can't select erase settings supported by both the SPI controller and memory.\n");
2490                 return err;
2491         }
2492
2493         return 0;
2494 }
2495
2496 static int spi_nor_setup(struct spi_nor *nor,
2497                          const struct spi_nor_hwcaps *hwcaps)
2498 {
2499         if (!nor->params->setup)
2500                 return 0;
2501
2502         return nor->params->setup(nor, hwcaps);
2503 }
2504
2505 /**
2506  * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2507  * settings based on MFR register and ->default_init() hook.
2508  * @nor:        pointer to a 'struct spi_nor'.
2509  */
2510 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2511 {
2512         if (nor->manufacturer && nor->manufacturer->fixups &&
2513             nor->manufacturer->fixups->default_init)
2514                 nor->manufacturer->fixups->default_init(nor);
2515
2516         if (nor->info->fixups && nor->info->fixups->default_init)
2517                 nor->info->fixups->default_init(nor);
2518 }
2519
2520 /**
2521  * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
2522  * based on JESD216 SFDP standard.
2523  * @nor:        pointer to a 'struct spi_nor'.
2524  *
2525  * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2526  * legacy flash parameters and settings will be restored.
2527  */
2528 static void spi_nor_sfdp_init_params(struct spi_nor *nor)
2529 {
2530         struct spi_nor_flash_parameter sfdp_params;
2531
2532         memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2533
2534         if (spi_nor_parse_sfdp(nor)) {
2535                 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2536                 nor->addr_width = 0;
2537                 nor->flags &= ~SNOR_F_4B_OPCODES;
2538         }
2539 }
2540
2541 /**
2542  * spi_nor_info_init_params() - Initialize the flash's parameters and settings
2543  * based on nor->info data.
2544  * @nor:        pointer to a 'struct spi_nor'.
2545  */
2546 static void spi_nor_info_init_params(struct spi_nor *nor)
2547 {
2548         struct spi_nor_flash_parameter *params = nor->params;
2549         struct spi_nor_erase_map *map = &params->erase_map;
2550         const struct flash_info *info = nor->info;
2551         struct device_node *np = spi_nor_get_flash_node(nor);
2552         u8 i, erase_mask;
2553
2554         /* Initialize default flash parameters and settings. */
2555         params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2556         params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2557         params->setup = spi_nor_default_setup;
2558         params->otp.org = &info->otp_org;
2559
2560         /* Default to 16-bit Write Status (01h) Command */
2561         nor->flags |= SNOR_F_HAS_16BIT_SR;
2562
2563         /* Set SPI NOR sizes. */
2564         params->writesize = 1;
2565         params->size = (u64)info->sector_size * info->n_sectors;
2566         params->page_size = info->page_size;
2567
2568         if (!(info->flags & SPI_NOR_NO_FR)) {
2569                 /* Default to Fast Read for DT and non-DT platform devices. */
2570                 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2571
2572                 /* Mask out Fast Read if not requested at DT instantiation. */
2573                 if (np && !of_property_read_bool(np, "m25p,fast-read"))
2574                         params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2575         }
2576
2577         /* (Fast) Read settings. */
2578         params->hwcaps.mask |= SNOR_HWCAPS_READ;
2579         spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2580                                   0, 0, SPINOR_OP_READ,
2581                                   SNOR_PROTO_1_1_1);
2582
2583         if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2584                 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2585                                           0, 8, SPINOR_OP_READ_FAST,
2586                                           SNOR_PROTO_1_1_1);
2587
2588         if (info->flags & SPI_NOR_DUAL_READ) {
2589                 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2590                 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2591                                           0, 8, SPINOR_OP_READ_1_1_2,
2592                                           SNOR_PROTO_1_1_2);
2593         }
2594
2595         if (info->flags & SPI_NOR_QUAD_READ) {
2596                 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2597                 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2598                                           0, 8, SPINOR_OP_READ_1_1_4,
2599                                           SNOR_PROTO_1_1_4);
2600         }
2601
2602         if (info->flags & SPI_NOR_OCTAL_READ) {
2603                 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2604                 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
2605                                           0, 8, SPINOR_OP_READ_1_1_8,
2606                                           SNOR_PROTO_1_1_8);
2607         }
2608
2609         if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
2610                 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2611                 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
2612                                           0, 20, SPINOR_OP_READ_FAST,
2613                                           SNOR_PROTO_8_8_8_DTR);
2614         }
2615
2616         /* Page Program settings. */
2617         params->hwcaps.mask |= SNOR_HWCAPS_PP;
2618         spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2619                                 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2620
2621         if (info->flags & SPI_NOR_OCTAL_DTR_PP) {
2622                 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2623                 /*
2624                  * Since xSPI Page Program opcode is backward compatible with
2625                  * Legacy SPI, use Legacy SPI opcode there as well.
2626                  */
2627                 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2628                                         SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2629         }
2630
2631         /*
2632          * Sector Erase settings. Sort Erase Types in ascending order, with the
2633          * smallest erase size starting at BIT(0).
2634          */
2635         erase_mask = 0;
2636         i = 0;
2637         if (info->flags & SECT_4K_PMC) {
2638                 erase_mask |= BIT(i);
2639                 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2640                                        SPINOR_OP_BE_4K_PMC);
2641                 i++;
2642         } else if (info->flags & SECT_4K) {
2643                 erase_mask |= BIT(i);
2644                 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2645                                        SPINOR_OP_BE_4K);
2646                 i++;
2647         }
2648         erase_mask |= BIT(i);
2649         spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
2650                                SPINOR_OP_SE);
2651         spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2652 }
2653
2654 /**
2655  * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
2656  * after SFDP has been parsed (is also called for SPI NORs that do not
2657  * support RDSFDP).
2658  * @nor:        pointer to a 'struct spi_nor'
2659  *
2660  * Typically used to tweak various parameters that could not be extracted by
2661  * other means (i.e. when information provided by the SFDP/flash_info tables
2662  * are incomplete or wrong).
2663  */
2664 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
2665 {
2666         if (nor->manufacturer && nor->manufacturer->fixups &&
2667             nor->manufacturer->fixups->post_sfdp)
2668                 nor->manufacturer->fixups->post_sfdp(nor);
2669
2670         if (nor->info->fixups && nor->info->fixups->post_sfdp)
2671                 nor->info->fixups->post_sfdp(nor);
2672 }
2673
2674 /**
2675  * spi_nor_late_init_params() - Late initialization of default flash parameters.
2676  * @nor:        pointer to a 'struct spi_nor'
2677  *
2678  * Used to set default flash parameters and settings when the ->default_init()
2679  * hook or the SFDP parser let voids.
2680  */
2681 static void spi_nor_late_init_params(struct spi_nor *nor)
2682 {
2683         /*
2684          * NOR protection support. When locking_ops are not provided, we pick
2685          * the default ones.
2686          */
2687         if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2688                 spi_nor_init_default_locking_ops(nor);
2689 }
2690
2691 /**
2692  * spi_nor_init_params() - Initialize the flash's parameters and settings.
2693  * @nor:        pointer to a 'struct spi_nor'.
2694  *
2695  * The flash parameters and settings are initialized based on a sequence of
2696  * calls that are ordered by priority:
2697  *
2698  * 1/ Default flash parameters initialization. The initializations are done
2699  *    based on nor->info data:
2700  *              spi_nor_info_init_params()
2701  *
2702  * which can be overwritten by:
2703  * 2/ Manufacturer flash parameters initialization. The initializations are
2704  *    done based on MFR register, or when the decisions can not be done solely
2705  *    based on MFR, by using specific flash_info tweeks, ->default_init():
2706  *              spi_nor_manufacturer_init_params()
2707  *
2708  * which can be overwritten by:
2709  * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2710  *    should be more accurate that the above.
2711  *              spi_nor_sfdp_init_params()
2712  *
2713  *    Please note that there is a ->post_bfpt() fixup hook that can overwrite
2714  *    the flash parameters and settings immediately after parsing the Basic
2715  *    Flash Parameter Table.
2716  *
2717  * which can be overwritten by:
2718  * 4/ Post SFDP flash parameters initialization. Used to tweak various
2719  *    parameters that could not be extracted by other means (i.e. when
2720  *    information provided by the SFDP/flash_info tables are incomplete or
2721  *    wrong).
2722  *              spi_nor_post_sfdp_fixups()
2723  *
2724  * 5/ Late default flash parameters initialization, used when the
2725  * ->default_init() hook or the SFDP parser do not set specific params.
2726  *              spi_nor_late_init_params()
2727  */
2728 static int spi_nor_init_params(struct spi_nor *nor)
2729 {
2730         nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2731         if (!nor->params)
2732                 return -ENOMEM;
2733
2734         spi_nor_info_init_params(nor);
2735
2736         spi_nor_manufacturer_init_params(nor);
2737
2738         if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2739                                  SPI_NOR_OCTAL_READ | SPI_NOR_OCTAL_DTR_READ)) &&
2740             !(nor->info->flags & SPI_NOR_SKIP_SFDP))
2741                 spi_nor_sfdp_init_params(nor);
2742
2743         spi_nor_post_sfdp_fixups(nor);
2744
2745         spi_nor_late_init_params(nor);
2746
2747         return 0;
2748 }
2749
2750 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
2751  * @nor:                 pointer to a 'struct spi_nor'
2752  * @enable:              whether to enable or disable Octal DTR
2753  *
2754  * Return: 0 on success, -errno otherwise.
2755  */
2756 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
2757 {
2758         int ret;
2759
2760         if (!nor->params->octal_dtr_enable)
2761                 return 0;
2762
2763         if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
2764               nor->write_proto == SNOR_PROTO_8_8_8_DTR))
2765                 return 0;
2766
2767         if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
2768                 return 0;
2769
2770         ret = nor->params->octal_dtr_enable(nor, enable);
2771         if (ret)
2772                 return ret;
2773
2774         if (enable)
2775                 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
2776         else
2777                 nor->reg_proto = SNOR_PROTO_1_1_1;
2778
2779         return 0;
2780 }
2781
2782 /**
2783  * spi_nor_quad_enable() - enable Quad I/O if needed.
2784  * @nor:                pointer to a 'struct spi_nor'
2785  *
2786  * Return: 0 on success, -errno otherwise.
2787  */
2788 static int spi_nor_quad_enable(struct spi_nor *nor)
2789 {
2790         if (!nor->params->quad_enable)
2791                 return 0;
2792
2793         if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2794               spi_nor_get_protocol_width(nor->write_proto) == 4))
2795                 return 0;
2796
2797         return nor->params->quad_enable(nor);
2798 }
2799
2800 static int spi_nor_init(struct spi_nor *nor)
2801 {
2802         int err;
2803
2804         err = spi_nor_octal_dtr_enable(nor, true);
2805         if (err) {
2806                 dev_dbg(nor->dev, "octal mode not supported\n");
2807                 return err;
2808         }
2809
2810         err = spi_nor_quad_enable(nor);
2811         if (err) {
2812                 dev_dbg(nor->dev, "quad mode not supported\n");
2813                 return err;
2814         }
2815
2816         /*
2817          * Some SPI NOR flashes are write protected by default after a power-on
2818          * reset cycle, in order to avoid inadvertent writes during power-up.
2819          * Backward compatibility imposes to unlock the entire flash memory
2820          * array at power-up by default. Depending on the kernel configuration
2821          * (1) do nothing, (2) always unlock the entire flash array or (3)
2822          * unlock the entire flash array only when the software write
2823          * protection bits are volatile. The latter is indicated by
2824          * SNOR_F_SWP_IS_VOLATILE.
2825          */
2826         if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
2827             (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
2828              nor->flags & SNOR_F_SWP_IS_VOLATILE))
2829                 spi_nor_try_unlock_all(nor);
2830
2831         if (nor->addr_width == 4 &&
2832             nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
2833             !(nor->flags & SNOR_F_4B_OPCODES)) {
2834                 /*
2835                  * If the RESET# pin isn't hooked up properly, or the system
2836                  * otherwise doesn't perform a reset command in the boot
2837                  * sequence, it's impossible to 100% protect against unexpected
2838                  * reboots (e.g., crashes). Warn the user (or hopefully, system
2839                  * designer) that this is bad.
2840                  */
2841                 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
2842                           "enabling reset hack; may not recover from unexpected reboots\n");
2843                 nor->params->set_4byte_addr_mode(nor, true);
2844         }
2845
2846         return 0;
2847 }
2848
2849 /**
2850  * spi_nor_soft_reset() - Perform a software reset
2851  * @nor:        pointer to 'struct spi_nor'
2852  *
2853  * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
2854  * the device to its power-on-reset state. This is useful when the software has
2855  * made some changes to device (volatile) registers and needs to reset it before
2856  * shutting down, for example.
2857  *
2858  * Not every flash supports this sequence. The same set of opcodes might be used
2859  * for some other operation on a flash that does not support this. Support for
2860  * this sequence can be discovered via SFDP in the BFPT table.
2861  *
2862  * Return: 0 on success, -errno otherwise.
2863  */
2864 static void spi_nor_soft_reset(struct spi_nor *nor)
2865 {
2866         struct spi_mem_op op;
2867         int ret;
2868
2869         op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
2870                         SPI_MEM_OP_NO_DUMMY,
2871                         SPI_MEM_OP_NO_ADDR,
2872                         SPI_MEM_OP_NO_DATA);
2873
2874         spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2875
2876         ret = spi_mem_exec_op(nor->spimem, &op);
2877         if (ret) {
2878                 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2879                 return;
2880         }
2881
2882         op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
2883                         SPI_MEM_OP_NO_DUMMY,
2884                         SPI_MEM_OP_NO_ADDR,
2885                         SPI_MEM_OP_NO_DATA);
2886
2887         spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
2888
2889         ret = spi_mem_exec_op(nor->spimem, &op);
2890         if (ret) {
2891                 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
2892                 return;
2893         }
2894
2895         /*
2896          * Software Reset is not instant, and the delay varies from flash to
2897          * flash. Looking at a few flashes, most range somewhere below 100
2898          * microseconds. So, sleep for a range of 200-400 us.
2899          */
2900         usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
2901 }
2902
2903 /* mtd suspend handler */
2904 static int spi_nor_suspend(struct mtd_info *mtd)
2905 {
2906         struct spi_nor *nor = mtd_to_spi_nor(mtd);
2907         int ret;
2908
2909         /* Disable octal DTR mode if we enabled it. */
2910         ret = spi_nor_octal_dtr_enable(nor, false);
2911         if (ret)
2912                 dev_err(nor->dev, "suspend() failed\n");
2913
2914         return ret;
2915 }
2916
2917 /* mtd resume handler */
2918 static void spi_nor_resume(struct mtd_info *mtd)
2919 {
2920         struct spi_nor *nor = mtd_to_spi_nor(mtd);
2921         struct device *dev = nor->dev;
2922         int ret;
2923
2924         /* re-initialize the nor chip */
2925         ret = spi_nor_init(nor);
2926         if (ret)
2927                 dev_err(dev, "resume() failed\n");
2928 }
2929
2930 static int spi_nor_get_device(struct mtd_info *mtd)
2931 {
2932         struct mtd_info *master = mtd_get_master(mtd);
2933         struct spi_nor *nor = mtd_to_spi_nor(master);
2934         struct device *dev;
2935
2936         if (nor->spimem)
2937                 dev = nor->spimem->spi->controller->dev.parent;
2938         else
2939                 dev = nor->dev;
2940
2941         if (!try_module_get(dev->driver->owner))
2942                 return -ENODEV;
2943
2944         return 0;
2945 }
2946
2947 static void spi_nor_put_device(struct mtd_info *mtd)
2948 {
2949         struct mtd_info *master = mtd_get_master(mtd);
2950         struct spi_nor *nor = mtd_to_spi_nor(master);
2951         struct device *dev;
2952
2953         if (nor->spimem)
2954                 dev = nor->spimem->spi->controller->dev.parent;
2955         else
2956                 dev = nor->dev;
2957
2958         module_put(dev->driver->owner);
2959 }
2960
2961 void spi_nor_restore(struct spi_nor *nor)
2962 {
2963         /* restore the addressing mode */
2964         if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
2965             nor->flags & SNOR_F_BROKEN_RESET)
2966                 nor->params->set_4byte_addr_mode(nor, false);
2967
2968         if (nor->flags & SNOR_F_SOFT_RESET)
2969                 spi_nor_soft_reset(nor);
2970 }
2971 EXPORT_SYMBOL_GPL(spi_nor_restore);
2972
2973 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
2974                                                  const char *name)
2975 {
2976         unsigned int i, j;
2977
2978         for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2979                 for (j = 0; j < manufacturers[i]->nparts; j++) {
2980                         if (!strcmp(name, manufacturers[i]->parts[j].name)) {
2981                                 nor->manufacturer = manufacturers[i];
2982                                 return &manufacturers[i]->parts[j];
2983                         }
2984                 }
2985         }
2986
2987         return NULL;
2988 }
2989
2990 static int spi_nor_set_addr_width(struct spi_nor *nor)
2991 {
2992         if (nor->addr_width) {
2993                 /* already configured from SFDP */
2994         } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2995                 /*
2996                  * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
2997                  * in this protocol an odd address width cannot be used because
2998                  * then the address phase would only span a cycle and a half.
2999                  * Half a cycle would be left over. We would then have to start
3000                  * the dummy phase in the middle of a cycle and so too the data
3001                  * phase, and we will end the transaction with half a cycle left
3002                  * over.
3003                  *
3004                  * Force all 8D-8D-8D flashes to use an address width of 4 to
3005                  * avoid this situation.
3006                  */
3007                 nor->addr_width = 4;
3008         } else if (nor->info->addr_width) {
3009                 nor->addr_width = nor->info->addr_width;
3010         } else {
3011                 nor->addr_width = 3;
3012         }
3013
3014         if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
3015                 /* enable 4-byte addressing if the device exceeds 16MiB */
3016                 nor->addr_width = 4;
3017         }
3018
3019         if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3020                 dev_dbg(nor->dev, "address width is too large: %u\n",
3021                         nor->addr_width);
3022                 return -EINVAL;
3023         }
3024
3025         /* Set 4byte opcodes when possible. */
3026         if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
3027             !(nor->flags & SNOR_F_HAS_4BAIT))
3028                 spi_nor_set_4byte_opcodes(nor);
3029
3030         return 0;
3031 }
3032
3033 static void spi_nor_debugfs_init(struct spi_nor *nor,
3034                                  const struct flash_info *info)
3035 {
3036         struct mtd_info *mtd = &nor->mtd;
3037
3038         mtd->dbg.partname = info->name;
3039         mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN",
3040                                          info->id_len, info->id);
3041 }
3042
3043 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3044                                                        const char *name)
3045 {
3046         const struct flash_info *info = NULL;
3047
3048         if (name)
3049                 info = spi_nor_match_id(nor, name);
3050         /* Try to auto-detect if chip name wasn't specified or not found */
3051         if (!info)
3052                 info = spi_nor_read_id(nor);
3053         if (IS_ERR_OR_NULL(info))
3054                 return ERR_PTR(-ENOENT);
3055
3056         /*
3057          * If caller has specified name of flash model that can normally be
3058          * detected using JEDEC, let's verify it.
3059          */
3060         if (name && info->id_len) {
3061                 const struct flash_info *jinfo;
3062
3063                 jinfo = spi_nor_read_id(nor);
3064                 if (IS_ERR(jinfo)) {
3065                         return jinfo;
3066                 } else if (jinfo != info) {
3067                         /*
3068                          * JEDEC knows better, so overwrite platform ID. We
3069                          * can't trust partitions any longer, but we'll let
3070                          * mtd apply them anyway, since some partitions may be
3071                          * marked read-only, and we don't want to lose that
3072                          * information, even if it's not 100% accurate.
3073                          */
3074                         dev_warn(nor->dev, "found %s, expected %s\n",
3075                                  jinfo->name, info->name);
3076                         info = jinfo;
3077                 }
3078         }
3079
3080         return info;
3081 }
3082
3083 int spi_nor_scan(struct spi_nor *nor, const char *name,
3084                  const struct spi_nor_hwcaps *hwcaps)
3085 {
3086         const struct flash_info *info;
3087         struct device *dev = nor->dev;
3088         struct mtd_info *mtd = &nor->mtd;
3089         struct device_node *np = spi_nor_get_flash_node(nor);
3090         int ret;
3091         int i;
3092
3093         ret = spi_nor_check(nor);
3094         if (ret)
3095                 return ret;
3096
3097         /* Reset SPI protocol for all commands. */
3098         nor->reg_proto = SNOR_PROTO_1_1_1;
3099         nor->read_proto = SNOR_PROTO_1_1_1;
3100         nor->write_proto = SNOR_PROTO_1_1_1;
3101
3102         /*
3103          * We need the bounce buffer early to read/write registers when going
3104          * through the spi-mem layer (buffers have to be DMA-able).
3105          * For spi-mem drivers, we'll reallocate a new buffer if
3106          * nor->page_size turns out to be greater than PAGE_SIZE (which
3107          * shouldn't happen before long since NOR pages are usually less
3108          * than 1KB) after spi_nor_scan() returns.
3109          */
3110         nor->bouncebuf_size = PAGE_SIZE;
3111         nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3112                                       GFP_KERNEL);
3113         if (!nor->bouncebuf)
3114                 return -ENOMEM;
3115
3116         info = spi_nor_get_flash_info(nor, name);
3117         if (IS_ERR(info))
3118                 return PTR_ERR(info);
3119
3120         nor->info = info;
3121
3122         spi_nor_debugfs_init(nor, info);
3123
3124         mutex_init(&nor->lock);
3125
3126         /*
3127          * Make sure the XSR_RDY flag is set before calling
3128          * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
3129          * with Atmel SPI NOR.
3130          */
3131         if (info->flags & SPI_NOR_XSR_RDY)
3132                 nor->flags |=  SNOR_F_READY_XSR_RDY;
3133
3134         if (info->flags & SPI_NOR_HAS_LOCK)
3135                 nor->flags |= SNOR_F_HAS_LOCK;
3136
3137         mtd->_write = spi_nor_write;
3138
3139         /* Init flash parameters based on flash_info struct and SFDP */
3140         ret = spi_nor_init_params(nor);
3141         if (ret)
3142                 return ret;
3143
3144         if (!mtd->name)
3145                 mtd->name = dev_name(dev);
3146         mtd->priv = nor;
3147         mtd->type = MTD_NORFLASH;
3148         mtd->writesize = nor->params->writesize;
3149         mtd->flags = MTD_CAP_NORFLASH;
3150         mtd->size = nor->params->size;
3151         mtd->_read = spi_nor_read;
3152         mtd->_suspend = spi_nor_suspend;
3153         mtd->_resume = spi_nor_resume;
3154         mtd->_get_device = spi_nor_get_device;
3155         mtd->_put_device = spi_nor_put_device;
3156
3157         if (info->flags & USE_FSR)
3158                 nor->flags |= SNOR_F_USE_FSR;
3159         if (info->flags & SPI_NOR_HAS_TB) {
3160                 nor->flags |= SNOR_F_HAS_SR_TB;
3161                 if (info->flags & SPI_NOR_TB_SR_BIT6)
3162                         nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
3163         }
3164
3165         if (info->flags & NO_CHIP_ERASE)
3166                 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
3167         if (info->flags & USE_CLSR)
3168                 nor->flags |= SNOR_F_USE_CLSR;
3169         if (info->flags & SPI_NOR_SWP_IS_VOLATILE)
3170                 nor->flags |= SNOR_F_SWP_IS_VOLATILE;
3171
3172         if (info->flags & SPI_NOR_4BIT_BP) {
3173                 nor->flags |= SNOR_F_HAS_4BIT_BP;
3174                 if (info->flags & SPI_NOR_BP3_SR_BIT6)
3175                         nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
3176         }
3177
3178         if (info->flags & SPI_NOR_NO_ERASE)
3179                 mtd->flags |= MTD_NO_ERASE;
3180         else
3181                 mtd->_erase = spi_nor_erase;
3182
3183         mtd->dev.parent = dev;
3184         nor->page_size = nor->params->page_size;
3185         mtd->writebufsize = nor->page_size;
3186
3187         if (of_property_read_bool(np, "broken-flash-reset"))
3188                 nor->flags |= SNOR_F_BROKEN_RESET;
3189
3190         /*
3191          * Configure the SPI memory:
3192          * - select op codes for (Fast) Read, Page Program and Sector Erase.
3193          * - set the number of dummy cycles (mode cycles + wait states).
3194          * - set the SPI protocols for register and memory accesses.
3195          */
3196         ret = spi_nor_setup(nor, hwcaps);
3197         if (ret)
3198                 return ret;
3199
3200         if (info->flags & SPI_NOR_4B_OPCODES)
3201                 nor->flags |= SNOR_F_4B_OPCODES;
3202
3203         if (info->flags & SPI_NOR_IO_MODE_EN_VOLATILE)
3204                 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
3205
3206         ret = spi_nor_set_addr_width(nor);
3207         if (ret)
3208                 return ret;
3209
3210         spi_nor_register_locking_ops(nor);
3211
3212         /* Send all the required SPI flash commands to initialize device */
3213         ret = spi_nor_init(nor);
3214         if (ret)
3215                 return ret;
3216
3217         /* Configure OTP parameters and ops */
3218         spi_nor_otp_init(nor);
3219
3220         dev_info(dev, "%s (%lld Kbytes)\n", info->name,
3221                         (long long)mtd->size >> 10);
3222
3223         dev_dbg(dev,
3224                 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
3225                 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
3226                 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
3227                 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
3228
3229         if (mtd->numeraseregions)
3230                 for (i = 0; i < mtd->numeraseregions; i++)
3231                         dev_dbg(dev,
3232                                 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
3233                                 ".erasesize = 0x%.8x (%uKiB), "
3234                                 ".numblocks = %d }\n",
3235                                 i, (long long)mtd->eraseregions[i].offset,
3236                                 mtd->eraseregions[i].erasesize,
3237                                 mtd->eraseregions[i].erasesize / 1024,
3238                                 mtd->eraseregions[i].numblocks);
3239         return 0;
3240 }
3241 EXPORT_SYMBOL_GPL(spi_nor_scan);
3242
3243 static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3244 {
3245         struct spi_mem_dirmap_info info = {
3246                 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
3247                                       SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3248                                       SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3249                                       SPI_MEM_OP_DATA_IN(0, NULL, 0)),
3250                 .offset = 0,
3251                 .length = nor->mtd.size,
3252         };
3253         struct spi_mem_op *op = &info.op_tmpl;
3254
3255         spi_nor_spimem_setup_op(nor, op, nor->read_proto);
3256
3257         /* convert the dummy cycles to the number of bytes */
3258         op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3259         if (spi_nor_protocol_is_dtr(nor->read_proto))
3260                 op->dummy.nbytes *= 2;
3261
3262         /*
3263          * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3264          * of data bytes is non-zero, the data buswidth won't be set here. So,
3265          * do it explicitly.
3266          */
3267         op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3268
3269         nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3270                                                        &info);
3271         return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3272 }
3273
3274 static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3275 {
3276         struct spi_mem_dirmap_info info = {
3277                 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
3278                                       SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
3279                                       SPI_MEM_OP_NO_DUMMY,
3280                                       SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
3281                 .offset = 0,
3282                 .length = nor->mtd.size,
3283         };
3284         struct spi_mem_op *op = &info.op_tmpl;
3285
3286         if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3287                 op->addr.nbytes = 0;
3288
3289         spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3290
3291         /*
3292          * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3293          * of data bytes is non-zero, the data buswidth won't be set here. So,
3294          * do it explicitly.
3295          */
3296         op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3297
3298         nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3299                                                        &info);
3300         return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3301 }
3302
3303 static int spi_nor_probe(struct spi_mem *spimem)
3304 {
3305         struct spi_device *spi = spimem->spi;
3306         struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3307         struct spi_nor *nor;
3308         /*
3309          * Enable all caps by default. The core will mask them after
3310          * checking what's really supported using spi_mem_supports_op().
3311          */
3312         const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3313         char *flash_name;
3314         int ret;
3315
3316         nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3317         if (!nor)
3318                 return -ENOMEM;
3319
3320         nor->spimem = spimem;
3321         nor->dev = &spi->dev;
3322         spi_nor_set_flash_node(nor, spi->dev.of_node);
3323
3324         spi_mem_set_drvdata(spimem, nor);
3325
3326         if (data && data->name)
3327                 nor->mtd.name = data->name;
3328
3329         if (!nor->mtd.name)
3330                 nor->mtd.name = spi_mem_get_name(spimem);
3331
3332         /*
3333          * For some (historical?) reason many platforms provide two different
3334          * names in flash_platform_data: "name" and "type". Quite often name is
3335          * set to "m25p80" and then "type" provides a real chip name.
3336          * If that's the case, respect "type" and ignore a "name".
3337          */
3338         if (data && data->type)
3339                 flash_name = data->type;
3340         else if (!strcmp(spi->modalias, "spi-nor"))
3341                 flash_name = NULL; /* auto-detect */
3342         else
3343                 flash_name = spi->modalias;
3344
3345         ret = spi_nor_scan(nor, flash_name, &hwcaps);
3346         if (ret)
3347                 return ret;
3348
3349         /*
3350          * None of the existing parts have > 512B pages, but let's play safe
3351          * and add this logic so that if anyone ever adds support for such
3352          * a NOR we don't end up with buffer overflows.
3353          */
3354         if (nor->page_size > PAGE_SIZE) {
3355                 nor->bouncebuf_size = nor->page_size;
3356                 devm_kfree(nor->dev, nor->bouncebuf);
3357                 nor->bouncebuf = devm_kmalloc(nor->dev,
3358                                               nor->bouncebuf_size,
3359                                               GFP_KERNEL);
3360                 if (!nor->bouncebuf)
3361                         return -ENOMEM;
3362         }
3363
3364         ret = spi_nor_create_read_dirmap(nor);
3365         if (ret)
3366                 return ret;
3367
3368         ret = spi_nor_create_write_dirmap(nor);
3369         if (ret)
3370                 return ret;
3371
3372         return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3373                                    data ? data->nr_parts : 0);
3374 }
3375
3376 static int spi_nor_remove(struct spi_mem *spimem)
3377 {
3378         struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3379
3380         spi_nor_restore(nor);
3381
3382         /* Clean up MTD stuff. */
3383         return mtd_device_unregister(&nor->mtd);
3384 }
3385
3386 static void spi_nor_shutdown(struct spi_mem *spimem)
3387 {
3388         struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3389
3390         spi_nor_restore(nor);
3391 }
3392
3393 /*
3394  * Do NOT add to this array without reading the following:
3395  *
3396  * Historically, many flash devices are bound to this driver by their name. But
3397  * since most of these flash are compatible to some extent, and their
3398  * differences can often be differentiated by the JEDEC read-ID command, we
3399  * encourage new users to add support to the spi-nor library, and simply bind
3400  * against a generic string here (e.g., "jedec,spi-nor").
3401  *
3402  * Many flash names are kept here in this list (as well as in spi-nor.c) to
3403  * keep them available as module aliases for existing platforms.
3404  */
3405 static const struct spi_device_id spi_nor_dev_ids[] = {
3406         /*
3407          * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3408          * hack around the fact that the SPI core does not provide uevent
3409          * matching for .of_match_table
3410          */
3411         {"spi-nor"},
3412
3413         /*
3414          * Entries not used in DTs that should be safe to drop after replacing
3415          * them with "spi-nor" in platform data.
3416          */
3417         {"s25sl064a"},  {"w25x16"},     {"m25p10"},     {"m25px64"},
3418
3419         /*
3420          * Entries that were used in DTs without "jedec,spi-nor" fallback and
3421          * should be kept for backward compatibility.
3422          */
3423         {"at25df321a"}, {"at25df641"},  {"at26df081a"},
3424         {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3425         {"mx25l25635e"},{"mx66l51235l"},
3426         {"n25q064"},    {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3427         {"s25fl256s1"}, {"s25fl512s"},  {"s25sl12801"}, {"s25fl008k"},
3428         {"s25fl064k"},
3429         {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3430         {"m25p40"},     {"m25p80"},     {"m25p16"},     {"m25p32"},
3431         {"m25p64"},     {"m25p128"},
3432         {"w25x80"},     {"w25x32"},     {"w25q32"},     {"w25q32dw"},
3433         {"w25q80bl"},   {"w25q128"},    {"w25q256"},
3434
3435         /* Flashes that can't be detected using JEDEC */
3436         {"m25p05-nonjedec"},    {"m25p10-nonjedec"},    {"m25p20-nonjedec"},
3437         {"m25p40-nonjedec"},    {"m25p80-nonjedec"},    {"m25p16-nonjedec"},
3438         {"m25p32-nonjedec"},    {"m25p64-nonjedec"},    {"m25p128-nonjedec"},
3439
3440         /* Everspin MRAMs (non-JEDEC) */
3441         { "mr25h128" }, /* 128 Kib, 40 MHz */
3442         { "mr25h256" }, /* 256 Kib, 40 MHz */
3443         { "mr25h10" },  /*   1 Mib, 40 MHz */
3444         { "mr25h40" },  /*   4 Mib, 40 MHz */
3445
3446         { },
3447 };
3448 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3449
3450 static const struct of_device_id spi_nor_of_table[] = {
3451         /*
3452          * Generic compatibility for SPI NOR that can be identified by the
3453          * JEDEC READ ID opcode (0x9F). Use this, if possible.
3454          */
3455         { .compatible = "jedec,spi-nor" },
3456         { /* sentinel */ },
3457 };
3458 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3459
3460 /*
3461  * REVISIT: many of these chips have deep power-down modes, which
3462  * should clearly be entered on suspend() to minimize power use.
3463  * And also when they're otherwise idle...
3464  */
3465 static struct spi_mem_driver spi_nor_driver = {
3466         .spidrv = {
3467                 .driver = {
3468                         .name = "spi-nor",
3469                         .of_match_table = spi_nor_of_table,
3470                         .dev_groups = spi_nor_sysfs_groups,
3471                 },
3472                 .id_table = spi_nor_dev_ids,
3473         },
3474         .probe = spi_nor_probe,
3475         .remove = spi_nor_remove,
3476         .shutdown = spi_nor_shutdown,
3477 };
3478 module_spi_mem_driver(spi_nor_driver);
3479
3480 MODULE_LICENSE("GPL v2");
3481 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3482 MODULE_AUTHOR("Mike Lavender");
3483 MODULE_DESCRIPTION("framework for SPI NOR");