1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HiSilicon FMC SPI NOR flash controller driver
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
7 #include <linux/bitops.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/spi-nor.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
18 /* Hardware register offsets and field definitions */
20 #define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
21 #define FMC_CFG_OP_MODE_BOOT 0
22 #define FMC_CFG_OP_MODE_NORMAL 1
23 #define FMC_CFG_FLASH_SEL(type) (((type) & 0x3) << 1)
24 #define FMC_CFG_FLASH_SEL_MASK 0x6
25 #define FMC_ECC_TYPE(type) (((type) & 0x7) << 5)
26 #define FMC_ECC_TYPE_MASK GENMASK(7, 5)
27 #define SPI_NOR_ADDR_MODE_MASK BIT_MASK(10)
28 #define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10)
29 #define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10)
30 #define FMC_GLOBAL_CFG 0x04
31 #define FMC_GLOBAL_CFG_WP_ENABLE BIT(6)
32 #define FMC_SPI_TIMING_CFG 0x08
33 #define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8)
34 #define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4)
35 #define TIMING_CFG_TSHSL(nr) ((nr) & 0xf)
36 #define CS_HOLD_TIME 0x6
37 #define CS_SETUP_TIME 0x6
38 #define CS_DESELECT_TIME 0xf
40 #define FMC_INT_OP_DONE BIT(0)
41 #define FMC_INT_CLR 0x20
43 #define FMC_CMD_CMD1(cmd) ((cmd) & 0xff)
44 #define FMC_ADDRL 0x2c
45 #define FMC_OP_CFG 0x30
46 #define OP_CFG_FM_CS(cs) ((cs) << 11)
47 #define OP_CFG_MEM_IF_TYPE(type) (((type) & 0x7) << 7)
48 #define OP_CFG_ADDR_NUM(addr) (((addr) & 0x7) << 4)
49 #define OP_CFG_DUMMY_NUM(dummy) ((dummy) & 0xf)
50 #define FMC_DATA_NUM 0x38
51 #define FMC_DATA_NUM_CNT(cnt) ((cnt) & GENMASK(13, 0))
53 #define FMC_OP_DUMMY_EN BIT(8)
54 #define FMC_OP_CMD1_EN BIT(7)
55 #define FMC_OP_ADDR_EN BIT(6)
56 #define FMC_OP_WRITE_DATA_EN BIT(5)
57 #define FMC_OP_READ_DATA_EN BIT(2)
58 #define FMC_OP_READ_STATUS_EN BIT(1)
59 #define FMC_OP_REG_OP_START BIT(0)
60 #define FMC_DMA_LEN 0x40
61 #define FMC_DMA_LEN_SET(len) ((len) & GENMASK(27, 0))
62 #define FMC_DMA_SADDR_D0 0x4c
63 #define HIFMC_DMA_MAX_LEN (4096)
64 #define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
65 #define FMC_OP_DMA 0x68
66 #define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16)
67 #define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8)
68 #define OP_CTRL_RW_OP(op) ((op) << 1)
69 #define OP_CTRL_DMA_OP_READY BIT(0)
70 #define FMC_OP_READ 0x0
71 #define FMC_OP_WRITE 0x1
72 #define FMC_WAIT_TIMEOUT 1000000
85 struct hifmc_host *host;
88 #define HIFMC_MAX_CHIP_NUM 2
93 void __iomem *regbase;
97 dma_addr_t dma_buffer;
99 struct spi_nor *nor[HIFMC_MAX_CHIP_NUM];
103 static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
107 return readl_poll_timeout(host->regbase + FMC_INT, reg,
108 (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
111 static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
113 enum hifmc_iftype if_type;
116 case SNOR_PROTO_1_1_2:
117 if_type = IF_TYPE_DUAL;
119 case SNOR_PROTO_1_2_2:
120 if_type = IF_TYPE_DIO;
122 case SNOR_PROTO_1_1_4:
123 if_type = IF_TYPE_QUAD;
125 case SNOR_PROTO_1_4_4:
126 if_type = IF_TYPE_QIO;
128 case SNOR_PROTO_1_1_1:
130 if_type = IF_TYPE_STD;
137 static void hisi_spi_nor_init(struct hifmc_host *host)
141 reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
142 | TIMING_CFG_TCSS(CS_SETUP_TIME)
143 | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
147 static int hisi_spi_nor_prep(struct spi_nor *nor)
149 struct hifmc_priv *priv = nor->priv;
150 struct hifmc_host *host = priv->host;
153 mutex_lock(&host->lock);
155 ret = clk_set_rate(host->clk, priv->clkrate);
159 ret = clk_prepare_enable(host->clk);
166 mutex_unlock(&host->lock);
170 static void hisi_spi_nor_unprep(struct spi_nor *nor)
172 struct hifmc_priv *priv = nor->priv;
173 struct hifmc_host *host = priv->host;
175 clk_disable_unprepare(host->clk);
176 mutex_unlock(&host->lock);
179 static int hisi_spi_nor_op_reg(struct spi_nor *nor,
180 u8 opcode, size_t len, u8 optype)
182 struct hifmc_priv *priv = nor->priv;
183 struct hifmc_host *host = priv->host;
186 reg = FMC_CMD_CMD1(opcode);
187 writel(reg, host->regbase + FMC_CMD);
189 reg = FMC_DATA_NUM_CNT(len);
190 writel(reg, host->regbase + FMC_DATA_NUM);
192 reg = OP_CFG_FM_CS(priv->chipselect);
193 writel(reg, host->regbase + FMC_OP_CFG);
195 writel(0xff, host->regbase + FMC_INT_CLR);
196 reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
197 writel(reg, host->regbase + FMC_OP);
199 return hisi_spi_nor_wait_op_finish(host);
202 static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
205 struct hifmc_priv *priv = nor->priv;
206 struct hifmc_host *host = priv->host;
209 ret = hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN);
213 memcpy_fromio(buf, host->iobase, len);
217 static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
218 const u8 *buf, size_t len)
220 struct hifmc_priv *priv = nor->priv;
221 struct hifmc_host *host = priv->host;
224 memcpy_toio(host->iobase, buf, len);
226 return hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN);
229 static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
230 dma_addr_t dma_buf, size_t len, u8 op_type)
232 struct hifmc_priv *priv = nor->priv;
233 struct hifmc_host *host = priv->host;
237 reg = readl(host->regbase + FMC_CFG);
238 reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
239 reg |= FMC_CFG_OP_MODE_NORMAL;
240 reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES
241 : SPI_NOR_ADDR_MODE_3BYTES;
242 writel(reg, host->regbase + FMC_CFG);
244 writel(start_off, host->regbase + FMC_ADDRL);
245 writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
246 writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
248 reg = OP_CFG_FM_CS(priv->chipselect);
249 if (op_type == FMC_OP_READ)
250 if_type = hisi_spi_nor_get_if_type(nor->read_proto);
252 if_type = hisi_spi_nor_get_if_type(nor->write_proto);
253 reg |= OP_CFG_MEM_IF_TYPE(if_type);
254 if (op_type == FMC_OP_READ)
255 reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
256 writel(reg, host->regbase + FMC_OP_CFG);
258 writel(0xff, host->regbase + FMC_INT_CLR);
259 reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
260 reg |= (op_type == FMC_OP_READ)
261 ? OP_CTRL_RD_OPCODE(nor->read_opcode)
262 : OP_CTRL_WR_OPCODE(nor->program_opcode);
263 writel(reg, host->regbase + FMC_OP_DMA);
265 return hisi_spi_nor_wait_op_finish(host);
268 static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
271 struct hifmc_priv *priv = nor->priv;
272 struct hifmc_host *host = priv->host;
276 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
277 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
279 ret = hisi_spi_nor_dma_transfer(nor,
280 from + offset, host->dma_buffer, trans, FMC_OP_READ);
282 dev_warn(nor->dev, "DMA read timeout\n");
285 memcpy(read_buf + offset, host->buffer, trans);
291 static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
292 size_t len, const u_char *write_buf)
294 struct hifmc_priv *priv = nor->priv;
295 struct hifmc_host *host = priv->host;
299 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
300 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
302 memcpy(host->buffer, write_buf + offset, trans);
303 ret = hisi_spi_nor_dma_transfer(nor,
304 to + offset, host->dma_buffer, trans, FMC_OP_WRITE);
306 dev_warn(nor->dev, "DMA write timeout\n");
314 static const struct spi_nor_controller_ops hisi_controller_ops = {
315 .prepare = hisi_spi_nor_prep,
316 .unprepare = hisi_spi_nor_unprep,
317 .read_reg = hisi_spi_nor_read_reg,
318 .write_reg = hisi_spi_nor_write_reg,
319 .read = hisi_spi_nor_read,
320 .write = hisi_spi_nor_write,
324 * Get spi flash device information and register it as a mtd device.
326 static int hisi_spi_nor_register(struct device_node *np,
327 struct hifmc_host *host)
329 const struct spi_nor_hwcaps hwcaps = {
330 .mask = SNOR_HWCAPS_READ |
331 SNOR_HWCAPS_READ_FAST |
332 SNOR_HWCAPS_READ_1_1_2 |
333 SNOR_HWCAPS_READ_1_1_4 |
336 struct device *dev = host->dev;
338 struct hifmc_priv *priv;
339 struct mtd_info *mtd;
342 nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
347 spi_nor_set_flash_node(nor, np);
349 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
353 ret = of_property_read_u32(np, "reg", &priv->chipselect);
355 dev_err(dev, "There's no reg property for %pOF\n",
360 ret = of_property_read_u32(np, "spi-max-frequency",
363 dev_err(dev, "There's no spi-max-frequency property for %pOF\n",
369 nor->controller_ops = &hisi_controller_ops;
371 ret = spi_nor_scan(nor, NULL, &hwcaps);
376 mtd->name = np->name;
377 ret = mtd_device_register(mtd, NULL, 0);
381 host->nor[host->num_chip] = nor;
386 static void hisi_spi_nor_unregister_all(struct hifmc_host *host)
390 for (i = 0; i < host->num_chip; i++)
391 mtd_device_unregister(&host->nor[i]->mtd);
394 static int hisi_spi_nor_register_all(struct hifmc_host *host)
396 struct device *dev = host->dev;
397 struct device_node *np;
400 for_each_available_child_of_node(dev->of_node, np) {
401 ret = hisi_spi_nor_register(np, host);
407 if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
408 dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n");
417 hisi_spi_nor_unregister_all(host);
421 static int hisi_spi_nor_probe(struct platform_device *pdev)
423 struct device *dev = &pdev->dev;
424 struct resource *res;
425 struct hifmc_host *host;
428 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
432 platform_set_drvdata(pdev, host);
435 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
436 host->regbase = devm_ioremap_resource(dev, res);
437 if (IS_ERR(host->regbase))
438 return PTR_ERR(host->regbase);
440 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
441 host->iobase = devm_ioremap_resource(dev, res);
442 if (IS_ERR(host->iobase))
443 return PTR_ERR(host->iobase);
445 host->clk = devm_clk_get(dev, NULL);
446 if (IS_ERR(host->clk))
447 return PTR_ERR(host->clk);
449 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
451 dev_warn(dev, "Unable to set dma mask\n");
455 host->buffer = dmam_alloc_coherent(dev, HIFMC_DMA_MAX_LEN,
456 &host->dma_buffer, GFP_KERNEL);
460 ret = clk_prepare_enable(host->clk);
464 mutex_init(&host->lock);
465 hisi_spi_nor_init(host);
466 ret = hisi_spi_nor_register_all(host);
468 mutex_destroy(&host->lock);
470 clk_disable_unprepare(host->clk);
474 static int hisi_spi_nor_remove(struct platform_device *pdev)
476 struct hifmc_host *host = platform_get_drvdata(pdev);
478 hisi_spi_nor_unregister_all(host);
479 mutex_destroy(&host->lock);
483 static const struct of_device_id hisi_spi_nor_dt_ids[] = {
484 { .compatible = "hisilicon,fmc-spi-nor"},
487 MODULE_DEVICE_TABLE(of, hisi_spi_nor_dt_ids);
489 static struct platform_driver hisi_spi_nor_driver = {
492 .of_match_table = hisi_spi_nor_dt_ids,
494 .probe = hisi_spi_nor_probe,
495 .remove = hisi_spi_nor_remove,
497 module_platform_driver(hisi_spi_nor_driver);
499 MODULE_LICENSE("GPL v2");
500 MODULE_DESCRIPTION("HiSilicon SPI Nor Flash Controller Driver");