drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/mtd/spi-nor.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/sched.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/timer.h>
  37
  38 #define CQSPI_NAME                      "cadence-qspi"
  39 #define CQSPI_MAX_CHIPSELECT            16
  40
  41 /* Quirks */
  42 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  43
  44 struct cqspi_st;
  45
  46 struct cqspi_flash_pdata {
  47         struct spi_nor  nor;
  48         struct cqspi_st *cqspi;
  49         u32             clk_rate;
  50         u32             read_delay;
  51         u32             tshsl_ns;
  52         u32             tsd2d_ns;
  53         u32             tchsh_ns;
  54         u32             tslch_ns;
  55         u8              inst_width;
  56         u8              addr_width;
  57         u8              data_width;
  58         u8              cs;
  59         bool            registered;
  60 };
  61
  62 struct cqspi_st {
  63         struct platform_device  *pdev;
  64
  65         struct clk              *clk;
  66         unsigned int            sclk;
  67
  68         void __iomem            *iobase;
  69         void __iomem            *ahb_base;
  70         struct completion       transfer_complete;
  71         struct mutex            bus_mutex;
  72
  73         int                     current_cs;
  74         int                     current_page_size;
  75         int                     current_erase_size;
  76         int                     current_addr_width;
  77         unsigned long           master_ref_clk_hz;
  78         bool                    is_decoded_cs;
  79         u32                     fifo_depth;
  80         u32                     fifo_width;
  81         u32                     trigger_address;
  82         u32                     wr_delay;
  83         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  84 };
  85
  86 /* Operation timeout value */
  87 #define CQSPI_TIMEOUT_MS                        500
  88 #define CQSPI_READ_TIMEOUT_MS                   10
  89
  90 /* Instruction type */
  91 #define CQSPI_INST_TYPE_SINGLE                  0
  92 #define CQSPI_INST_TYPE_DUAL                    1
  93 #define CQSPI_INST_TYPE_QUAD                    2
  94
  95 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  96 #define CQSPI_DUMMY_BYTES_MAX                   4
  97 #define CQSPI_DUMMY_CLKS_MAX                    31
  98
  99 #define CQSPI_STIG_DATA_LEN_MAX                 8
 100
 101 /* Register map */
 102 #define CQSPI_REG_CONFIG                        0x00
 103 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 104 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 105 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 106 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 107 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 108 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 109 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 110 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 111
 112 #define CQSPI_REG_RD_INSTR                      0x04
 113 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 114 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 115 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 116 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 117 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 118 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 119 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 120 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 121 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 122 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 123
 124 #define CQSPI_REG_WR_INSTR                      0x08
 125 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 126 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 127 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 128
 129 #define CQSPI_REG_DELAY                         0x0C
 130 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 131 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 132 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 133 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 134 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 135 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 136 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 137 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 138
 139 #define CQSPI_REG_READCAPTURE                   0x10
 140 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 141 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 142 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 143
 144 #define CQSPI_REG_SIZE                          0x14
 145 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 146 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 147 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 148 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 149 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 150 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 151
 152 #define CQSPI_REG_SRAMPARTITION                 0x18
 153 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 154
 155 #define CQSPI_REG_DMA                           0x20
 156 #define CQSPI_REG_DMA_SINGLE_LSB                0
 157 #define CQSPI_REG_DMA_BURST_LSB                 8
 158 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 159 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 160
 161 #define CQSPI_REG_REMAP                         0x24
 162 #define CQSPI_REG_MODE_BIT                      0x28
 163
 164 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 165 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 166 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 167 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 168 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 169
 170 #define CQSPI_REG_IRQSTATUS                     0x40
 171 #define CQSPI_REG_IRQMASK                       0x44
 172
 173 #define CQSPI_REG_INDIRECTRD                    0x60
 174 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 175 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 176 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 177
 178 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 179 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 180 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 181
 182 #define CQSPI_REG_CMDCTRL                       0x90
 183 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 184 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 185 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 186 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 187 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 188 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 189 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 190 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 191 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 192 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 193 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 194 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 195
 196 #define CQSPI_REG_INDIRECTWR                    0x70
 197 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 198 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 199 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 200
 201 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 202 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 203 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 204
 205 #define CQSPI_REG_CMDADDRESS                    0x94
 206 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 207 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 208 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 209 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 210
 211 /* Interrupt status bits */
 212 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 213 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 214 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 215 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 216 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 217 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 218 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 219 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 220
 221 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 222                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 223                                          CQSPI_REG_IRQ_IND_COMP)
 224
 225 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 226                                          CQSPI_REG_IRQ_WATERMARK        | \
 227                                          CQSPI_REG_IRQ_UNDERFLOW)
 228
 229 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 230
 231 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 232 {
 233         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 234         u32 val;
 235
 236         while (1) {
 237                 val = readl(reg);
 238                 if (clear)
 239                         val = ~val;
 240                 val &= mask;
 241
 242                 if (val == mask)
 243                         return 0;
 244
 245                 if (time_after(jiffies, end))
 246                         return -ETIMEDOUT;
 247         }
 248 }
 249
 250 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 251 {
 252         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 253
 254         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 255 }
 256
 257 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 258 {
 259         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 260
 261         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 262         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 263 }
 264
 265 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 266 {
 267         struct cqspi_st *cqspi = dev;
 268         unsigned int irq_status;
 269
 270         /* Read interrupt status */
 271         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 272
 273         /* Clear interrupt */
 274         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 275
 276         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 277
 278         if (irq_status)
 279                 complete(&cqspi->transfer_complete);
 280
 281         return IRQ_HANDLED;
 282 }
 283
 284 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 285 {
 286         struct cqspi_flash_pdata *f_pdata = nor->priv;
 287         u32 rdreg = 0;
 288
 289         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 290         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 291         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 292
 293         return rdreg;
 294 }
 295
 296 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 297 {
 298         const unsigned int poll_idle_retry = 3;
 299         unsigned int count = 0;
 300         unsigned long timeout;
 301
 302         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 303         while (1) {
 304                 /*
 305                  * Read few times in succession to ensure the controller
 306                  * is indeed idle, that is, the bit does not transition
 307                  * low again.
 308                  */
 309                 if (cqspi_is_idle(cqspi))
 310                         count++;
 311                 else
 312                         count = 0;
 313
 314                 if (count >= poll_idle_retry)
 315                         return 0;
 316
 317                 if (time_after(jiffies, timeout)) {
 318                         /* Timeout, in busy mode. */
 319                         dev_err(&cqspi->pdev->dev,
 320                                 "QSPI is still busy after %dms timeout.\n",
 321                                 CQSPI_TIMEOUT_MS);
 322                         return -ETIMEDOUT;
 323                 }
 324
 325                 cpu_relax();
 326         }
 327 }
 328
 329 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 330 {
 331         void __iomem *reg_base = cqspi->iobase;
 332         int ret;
 333
 334         /* Write the CMDCTRL without start execution. */
 335         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 336         /* Start execute */
 337         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 338         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 339
 340         /* Polling for completion. */
 341         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 342                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 343         if (ret) {
 344                 dev_err(&cqspi->pdev->dev,
 345                         "Flash command execution timed out.\n");
 346                 return ret;
 347         }
 348
 349         /* Polling QSPI idle status. */
 350         return cqspi_wait_idle(cqspi);
 351 }
 352
 353 static int cqspi_command_read(struct spi_nor *nor,
 354                               const u8 *txbuf, const unsigned n_tx,
 355                               u8 *rxbuf, const unsigned n_rx)
 356 {
 357         struct cqspi_flash_pdata *f_pdata = nor->priv;
 358         struct cqspi_st *cqspi = f_pdata->cqspi;
 359         void __iomem *reg_base = cqspi->iobase;
 360         unsigned int rdreg;
 361         unsigned int reg;
 362         unsigned int read_len;
 363         int status;
 364
 365         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 366                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 367                         n_rx, rxbuf);
 368                 return -EINVAL;
 369         }
 370
 371         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 372
 373         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 374         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 375
 376         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 377
 378         /* 0 means 1 byte. */
 379         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 380                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 381         status = cqspi_exec_flash_cmd(cqspi, reg);
 382         if (status)
 383                 return status;
 384
 385         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 386
 387         /* Put the read value into rx_buf */
 388         read_len = (n_rx > 4) ? 4 : n_rx;
 389         memcpy(rxbuf, &reg, read_len);
 390         rxbuf += read_len;
 391
 392         if (n_rx > 4) {
 393                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 394
 395                 read_len = n_rx - read_len;
 396                 memcpy(rxbuf, &reg, read_len);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 403                                const u8 *txbuf, const unsigned n_tx)
 404 {
 405         struct cqspi_flash_pdata *f_pdata = nor->priv;
 406         struct cqspi_st *cqspi = f_pdata->cqspi;
 407         void __iomem *reg_base = cqspi->iobase;
 408         unsigned int reg;
 409         unsigned int data;
 410         int ret;
 411
 412         if (n_tx > 4 || (n_tx && !txbuf)) {
 413                 dev_err(nor->dev,
 414                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 415                         n_tx, txbuf);
 416                 return -EINVAL;
 417         }
 418
 419         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 420         if (n_tx) {
 421                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 422                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 423                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 424                 data = 0;
 425                 memcpy(&data, txbuf, n_tx);
 426                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 427         }
 428
 429         ret = cqspi_exec_flash_cmd(cqspi, reg);
 430         return ret;
 431 }
 432
 433 static int cqspi_command_write_addr(struct spi_nor *nor,
 434                                     const u8 opcode, const unsigned int addr)
 435 {
 436         struct cqspi_flash_pdata *f_pdata = nor->priv;
 437         struct cqspi_st *cqspi = f_pdata->cqspi;
 438         void __iomem *reg_base = cqspi->iobase;
 439         unsigned int reg;
 440
 441         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 442         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 443         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 444                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 445
 446         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 447
 448         return cqspi_exec_flash_cmd(cqspi, reg);
 449 }
 450
 451 static int cqspi_indirect_read_setup(struct spi_nor *nor,
 452                                      const unsigned int from_addr)
 453 {
 454         struct cqspi_flash_pdata *f_pdata = nor->priv;
 455         struct cqspi_st *cqspi = f_pdata->cqspi;
 456         void __iomem *reg_base = cqspi->iobase;
 457         unsigned int dummy_clk = 0;
 458         unsigned int reg;
 459
 460         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 461
 462         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 463         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 464
 465         /* Setup dummy clock cycles */
 466         dummy_clk = nor->read_dummy;
 467         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 468                 return -EOPNOTSUPP;
 469
 470         if (dummy_clk / 8) {
 471                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 472                 /* Set mode bits high to ensure chip doesn't enter XIP */
 473                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 474
 475                 /* Need to subtract the mode byte (8 clocks). */
 476                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 477                         dummy_clk -= 8;
 478
 479                 if (dummy_clk)
 480                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 481                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 482         }
 483
 484         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 485
 486         /* Set address width */
 487         reg = readl(reg_base + CQSPI_REG_SIZE);
 488         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 489         reg |= (nor->addr_width - 1);
 490         writel(reg, reg_base + CQSPI_REG_SIZE);
 491         return 0;
 492 }
 493
 494 static int cqspi_indirect_read_execute(struct spi_nor *nor,
 495                                        u8 *rxbuf, const unsigned n_rx)
 496 {
 497         struct cqspi_flash_pdata *f_pdata = nor->priv;
 498         struct cqspi_st *cqspi = f_pdata->cqspi;
 499         void __iomem *reg_base = cqspi->iobase;
 500         void __iomem *ahb_base = cqspi->ahb_base;
 501         unsigned int remaining = n_rx;
 502         unsigned int mod_bytes = n_rx % 4;
 503         unsigned int bytes_to_read = 0;
 504         u8 *rxbuf_end = rxbuf + n_rx;
 505         int ret = 0;
 506
 507         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 508
 509         /* Clear all interrupts. */
 510         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 511
 512         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 513
 514         reinit_completion(&cqspi->transfer_complete);
 515         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 516                reg_base + CQSPI_REG_INDIRECTRD);
 517
 518         while (remaining > 0) {
 519                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 520                                                   msecs_to_jiffies
 521                                                   (CQSPI_READ_TIMEOUT_MS));
 522
 523                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 524
 525                 if (!ret && bytes_to_read == 0) {
 526                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 527                         ret = -ETIMEDOUT;
 528                         goto failrd;
 529                 }
 530
 531                 while (bytes_to_read != 0) {
 532                         unsigned int word_remain = round_down(remaining, 4);
 533
 534                         bytes_to_read *= cqspi->fifo_width;
 535                         bytes_to_read = bytes_to_read > remaining ?
 536                                         remaining : bytes_to_read;
 537                         bytes_to_read = round_down(bytes_to_read, 4);
 538                         /* Read 4 byte word chunks then single bytes */
 539                         if (bytes_to_read) {
 540                                 ioread32_rep(ahb_base, rxbuf,
 541                                              (bytes_to_read / 4));
 542                         } else if (!word_remain && mod_bytes) {
 543                                 unsigned int temp = ioread32(ahb_base);
 544
 545                                 bytes_to_read = mod_bytes;
 546                                 memcpy(rxbuf, &temp, min((unsigned int)
 547                                                          (rxbuf_end - rxbuf),
 548                                                          bytes_to_read));
 549                         }
 550                         rxbuf += bytes_to_read;
 551                         remaining -= bytes_to_read;
 552                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 553                 }
 554
 555                 if (remaining > 0)
 556                         reinit_completion(&cqspi->transfer_complete);
 557         }
 558
 559         /* Check indirect done status */
 560         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 561                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 562         if (ret) {
 563                 dev_err(nor->dev,
 564                         "Indirect read completion error (%i)\n", ret);
 565                 goto failrd;
 566         }
 567
 568         /* Disable interrupt */
 569         writel(0, reg_base + CQSPI_REG_IRQMASK);
 570
 571         /* Clear indirect completion status */
 572         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 573
 574         return 0;
 575
 576 failrd:
 577         /* Disable interrupt */
 578         writel(0, reg_base + CQSPI_REG_IRQMASK);
 579
 580         /* Cancel the indirect read */
 581         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 582                reg_base + CQSPI_REG_INDIRECTRD);
 583         return ret;
 584 }
 585
 586 static int cqspi_indirect_write_setup(struct spi_nor *nor,
 587                                       const unsigned int to_addr)
 588 {
 589         unsigned int reg;
 590         struct cqspi_flash_pdata *f_pdata = nor->priv;
 591         struct cqspi_st *cqspi = f_pdata->cqspi;
 592         void __iomem *reg_base = cqspi->iobase;
 593
 594         /* Set opcode. */
 595         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 596         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 597         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 598         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 599
 600         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 601
 602         reg = readl(reg_base + CQSPI_REG_SIZE);
 603         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 604         reg |= (nor->addr_width - 1);
 605         writel(reg, reg_base + CQSPI_REG_SIZE);
 606         return 0;
 607 }
 608
 609 static int cqspi_indirect_write_execute(struct spi_nor *nor,
 610                                         const u8 *txbuf, const unsigned n_tx)
 611 {
 612         const unsigned int page_size = nor->page_size;
 613         struct cqspi_flash_pdata *f_pdata = nor->priv;
 614         struct cqspi_st *cqspi = f_pdata->cqspi;
 615         void __iomem *reg_base = cqspi->iobase;
 616         unsigned int remaining = n_tx;
 617         unsigned int write_bytes;
 618         int ret;
 619
 620         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 621
 622         /* Clear all interrupts. */
 623         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 624
 625         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 626
 627         reinit_completion(&cqspi->transfer_complete);
 628         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 629                reg_base + CQSPI_REG_INDIRECTWR);
 630         /*
 631          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 632          * Controller programming sequence, couple of cycles of
 633          * QSPI_REF_CLK delay is required for the above bit to
 634          * be internally synchronized by the QSPI module. Provide 5
 635          * cycles of delay.
 636          */
 637         if (cqspi->wr_delay)
 638                 ndelay(cqspi->wr_delay);
 639
 640         while (remaining > 0) {
 641                 size_t write_words, mod_bytes;
 642
 643                 write_bytes = remaining > page_size ? page_size : remaining;
 644                 write_words = write_bytes / 4;
 645                 mod_bytes = write_bytes % 4;
 646                 /* Write 4 bytes at a time then single bytes. */
 647                 if (write_words) {
 648                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 649                         txbuf += (write_words * 4);
 650                 }
 651                 if (mod_bytes) {
 652                         unsigned int temp = 0xFFFFFFFF;
 653
 654                         memcpy(&temp, txbuf, mod_bytes);
 655                         iowrite32(temp, cqspi->ahb_base);
 656                         txbuf += mod_bytes;
 657                 }
 658
 659                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 660                                                   msecs_to_jiffies
 661                                                   (CQSPI_TIMEOUT_MS));
 662                 if (!ret) {
 663                         dev_err(nor->dev, "Indirect write timeout\n");
 664                         ret = -ETIMEDOUT;
 665                         goto failwr;
 666                 }
 667
 668                 remaining -= write_bytes;
 669
 670                 if (remaining > 0)
 671                         reinit_completion(&cqspi->transfer_complete);
 672         }
 673
 674         /* Check indirect done status */
 675         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 676                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 677         if (ret) {
 678                 dev_err(nor->dev,
 679                         "Indirect write completion error (%i)\n", ret);
 680                 goto failwr;
 681         }
 682
 683         /* Disable interrupt. */
 684         writel(0, reg_base + CQSPI_REG_IRQMASK);
 685
 686         /* Clear indirect completion status */
 687         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 688
 689         cqspi_wait_idle(cqspi);
 690
 691         return 0;
 692
 693 failwr:
 694         /* Disable interrupt. */
 695         writel(0, reg_base + CQSPI_REG_IRQMASK);
 696
 697         /* Cancel the indirect write */
 698         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 699                reg_base + CQSPI_REG_INDIRECTWR);
 700         return ret;
 701 }
 702
 703 static void cqspi_chipselect(struct spi_nor *nor)
 704 {
 705         struct cqspi_flash_pdata *f_pdata = nor->priv;
 706         struct cqspi_st *cqspi = f_pdata->cqspi;
 707         void __iomem *reg_base = cqspi->iobase;
 708         unsigned int chip_select = f_pdata->cs;
 709         unsigned int reg;
 710
 711         reg = readl(reg_base + CQSPI_REG_CONFIG);
 712         if (cqspi->is_decoded_cs) {
 713                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 714         } else {
 715                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 716
 717                 /* Convert CS if without decoder.
 718                  * CS0 to 4b'1110
 719                  * CS1 to 4b'1101
 720                  * CS2 to 4b'1011
 721                  * CS3 to 4b'0111
 722                  */
 723                 chip_select = 0xF & ~(1 << chip_select);
 724         }
 725
 726         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 727                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 728         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 729             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 730         writel(reg, reg_base + CQSPI_REG_CONFIG);
 731 }
 732
 733 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 734 {
 735         struct cqspi_flash_pdata *f_pdata = nor->priv;
 736         struct cqspi_st *cqspi = f_pdata->cqspi;
 737         void __iomem *iobase = cqspi->iobase;
 738         unsigned int reg;
 739
 740         /* configure page size and block size. */
 741         reg = readl(iobase + CQSPI_REG_SIZE);
 742         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 743         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 744         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 745         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 746         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 747         reg |= (nor->addr_width - 1);
 748         writel(reg, iobase + CQSPI_REG_SIZE);
 749
 750         /* configure the chip select */
 751         cqspi_chipselect(nor);
 752
 753         /* Store the new configuration of the controller */
 754         cqspi->current_page_size = nor->page_size;
 755         cqspi->current_erase_size = nor->mtd.erasesize;
 756         cqspi->current_addr_width = nor->addr_width;
 757 }
 758
 759 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 760                                            const unsigned int ns_val)
 761 {
 762         unsigned int ticks;
 763
 764         ticks = ref_clk_hz / 1000;      /* kHz */
 765         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 766
 767         return ticks;
 768 }
 769
 770 static void cqspi_delay(struct spi_nor *nor)
 771 {
 772         struct cqspi_flash_pdata *f_pdata = nor->priv;
 773         struct cqspi_st *cqspi = f_pdata->cqspi;
 774         void __iomem *iobase = cqspi->iobase;
 775         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 776         unsigned int tshsl, tchsh, tslch, tsd2d;
 777         unsigned int reg;
 778         unsigned int tsclk;
 779
 780         /* calculate the number of ref ticks for one sclk tick */
 781         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 782
 783         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 784         /* this particular value must be at least one sclk */
 785         if (tshsl < tsclk)
 786                 tshsl = tsclk;
 787
 788         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 789         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 790         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 791
 792         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 793                << CQSPI_REG_DELAY_TSHSL_LSB;
 794         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 795                 << CQSPI_REG_DELAY_TCHSH_LSB;
 796         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 797                 << CQSPI_REG_DELAY_TSLCH_LSB;
 798         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 799                 << CQSPI_REG_DELAY_TSD2D_LSB;
 800         writel(reg, iobase + CQSPI_REG_DELAY);
 801 }
 802
 803 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 804 {
 805         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 806         void __iomem *reg_base = cqspi->iobase;
 807         u32 reg, div;
 808
 809         /* Recalculate the baudrate divisor based on QSPI specification. */
 810         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 811
 812         reg = readl(reg_base + CQSPI_REG_CONFIG);
 813         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 814         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 815         writel(reg, reg_base + CQSPI_REG_CONFIG);
 816 }
 817
 818 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 819                                    const unsigned int bypass,
 820                                    const unsigned int delay)
 821 {
 822         void __iomem *reg_base = cqspi->iobase;
 823         unsigned int reg;
 824
 825         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 826
 827         if (bypass)
 828                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 829         else
 830                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 831
 832         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 833                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 834
 835         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 836                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 837
 838         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 839 }
 840
 841 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 842 {
 843         void __iomem *reg_base = cqspi->iobase;
 844         unsigned int reg;
 845
 846         reg = readl(reg_base + CQSPI_REG_CONFIG);
 847
 848         if (enable)
 849                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 850         else
 851                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 852
 853         writel(reg, reg_base + CQSPI_REG_CONFIG);
 854 }
 855
 856 static void cqspi_configure(struct spi_nor *nor)
 857 {
 858         struct cqspi_flash_pdata *f_pdata = nor->priv;
 859         struct cqspi_st *cqspi = f_pdata->cqspi;
 860         const unsigned int sclk = f_pdata->clk_rate;
 861         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 862         int switch_ck = (cqspi->sclk != sclk);
 863
 864         if ((cqspi->current_page_size != nor->page_size) ||
 865             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 866             (cqspi->current_addr_width != nor->addr_width))
 867                 switch_cs = 1;
 868
 869         if (switch_cs || switch_ck)
 870                 cqspi_controller_enable(cqspi, 0);
 871
 872         /* Switch chip select. */
 873         if (switch_cs) {
 874                 cqspi->current_cs = f_pdata->cs;
 875                 cqspi_configure_cs_and_sizes(nor);
 876         }
 877
 878         /* Setup baudrate divisor and delays */
 879         if (switch_ck) {
 880                 cqspi->sclk = sclk;
 881                 cqspi_config_baudrate_div(cqspi);
 882                 cqspi_delay(nor);
 883                 cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
 884         }
 885
 886         if (switch_cs || switch_ck)
 887                 cqspi_controller_enable(cqspi, 1);
 888 }
 889
 890 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 891 {
 892         struct cqspi_flash_pdata *f_pdata = nor->priv;
 893
 894         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 895         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 896         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 897
 898         if (read) {
 899                 switch (nor->read_proto) {
 900                 case SNOR_PROTO_1_1_1:
 901                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 902                         break;
 903                 case SNOR_PROTO_1_1_2:
 904                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 905                         break;
 906                 case SNOR_PROTO_1_1_4:
 907                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 908                         break;
 909                 default:
 910                         return -EINVAL;
 911                 }
 912         }
 913
 914         cqspi_configure(nor);
 915
 916         return 0;
 917 }
 918
 919 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 920                            size_t len, const u_char *buf)
 921 {
 922         int ret;
 923
 924         ret = cqspi_set_protocol(nor, 0);
 925         if (ret)
 926                 return ret;
 927
 928         ret = cqspi_indirect_write_setup(nor, to);
 929         if (ret)
 930                 return ret;
 931
 932         ret = cqspi_indirect_write_execute(nor, buf, len);
 933         if (ret)
 934                 return ret;
 935
 936         return len;
 937 }
 938
 939 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 940                           size_t len, u_char *buf)
 941 {
 942         int ret;
 943
 944         ret = cqspi_set_protocol(nor, 1);
 945         if (ret)
 946                 return ret;
 947
 948         ret = cqspi_indirect_read_setup(nor, from);
 949         if (ret)
 950                 return ret;
 951
 952         ret = cqspi_indirect_read_execute(nor, buf, len);
 953         if (ret)
 954                 return ret;
 955
 956         return len;
 957 }
 958
 959 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
 960 {
 961         int ret;
 962
 963         ret = cqspi_set_protocol(nor, 0);
 964         if (ret)
 965                 return ret;
 966
 967         /* Send write enable, then erase commands. */
 968         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 969         if (ret)
 970                 return ret;
 971
 972         /* Set up command buffer. */
 973         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
 974         if (ret)
 975                 return ret;
 976
 977         return 0;
 978 }
 979
 980 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 981 {
 982         struct cqspi_flash_pdata *f_pdata = nor->priv;
 983         struct cqspi_st *cqspi = f_pdata->cqspi;
 984
 985         mutex_lock(&cqspi->bus_mutex);
 986
 987         return 0;
 988 }
 989
 990 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 991 {
 992         struct cqspi_flash_pdata *f_pdata = nor->priv;
 993         struct cqspi_st *cqspi = f_pdata->cqspi;
 994
 995         mutex_unlock(&cqspi->bus_mutex);
 996 }
 997
 998 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 999 {
1000         int ret;
1001
1002         ret = cqspi_set_protocol(nor, 0);
1003         if (!ret)
1004                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1005
1006         return ret;
1007 }
1008
1009 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1010 {
1011         int ret;
1012
1013         ret = cqspi_set_protocol(nor, 0);
1014         if (!ret)
1015                 ret = cqspi_command_write(nor, opcode, buf, len);
1016
1017         return ret;
1018 }
1019
1020 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1021                                     struct cqspi_flash_pdata *f_pdata,
1022                                     struct device_node *np)
1023 {
1024         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1025                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1026                 return -ENXIO;
1027         }
1028
1029         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1030                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1031                 return -ENXIO;
1032         }
1033
1034         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1035                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1036                 return -ENXIO;
1037         }
1038
1039         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1040                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1041                 return -ENXIO;
1042         }
1043
1044         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1045                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1046                 return -ENXIO;
1047         }
1048
1049         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1050                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1051                 return -ENXIO;
1052         }
1053
1054         return 0;
1055 }
1056
1057 static int cqspi_of_get_pdata(struct platform_device *pdev)
1058 {
1059         struct device_node *np = pdev->dev.of_node;
1060         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1061
1062         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1063
1064         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1065                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1066                 return -ENXIO;
1067         }
1068
1069         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1070                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1071                 return -ENXIO;
1072         }
1073
1074         if (of_property_read_u32(np, "cdns,trigger-address",
1075                                  &cqspi->trigger_address)) {
1076                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1077                 return -ENXIO;
1078         }
1079
1080         return 0;
1081 }
1082
1083 static void cqspi_controller_init(struct cqspi_st *cqspi)
1084 {
1085         cqspi_controller_enable(cqspi, 0);
1086
1087         /* Configure the remap address register, no remap */
1088         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1089
1090         /* Disable all interrupts. */
1091         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1092
1093         /* Configure the SRAM split to 1:1 . */
1094         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1095
1096         /* Load indirect trigger address. */
1097         writel(cqspi->trigger_address,
1098                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1099
1100         /* Program read watermark -- 1/2 of the FIFO. */
1101         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1102                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1103         /* Program write watermark -- 1/8 of the FIFO. */
1104         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1105                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1106
1107         cqspi_controller_enable(cqspi, 1);
1108 }
1109
1110 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1111 {
1112         const struct spi_nor_hwcaps hwcaps = {
1113                 .mask = SNOR_HWCAPS_READ |
1114                         SNOR_HWCAPS_READ_FAST |
1115                         SNOR_HWCAPS_READ_1_1_2 |
1116                         SNOR_HWCAPS_READ_1_1_4 |
1117                         SNOR_HWCAPS_PP,
1118         };
1119         struct platform_device *pdev = cqspi->pdev;
1120         struct device *dev = &pdev->dev;
1121         struct cqspi_flash_pdata *f_pdata;
1122         struct spi_nor *nor;
1123         struct mtd_info *mtd;
1124         unsigned int cs;
1125         int i, ret;
1126
1127         /* Get flash device data */
1128         for_each_available_child_of_node(dev->of_node, np) {
1129                 ret = of_property_read_u32(np, "reg", &cs);
1130                 if (ret) {
1131                         dev_err(dev, "Couldn't determine chip select.\n");
1132                         goto err;
1133                 }
1134
1135                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1136                         ret = -EINVAL;
1137                         dev_err(dev, "Chip select %d out of range.\n", cs);
1138                         goto err;
1139                 }
1140
1141                 f_pdata = &cqspi->f_pdata[cs];
1142                 f_pdata->cqspi = cqspi;
1143                 f_pdata->cs = cs;
1144
1145                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1146                 if (ret)
1147                         goto err;
1148
1149                 nor = &f_pdata->nor;
1150                 mtd = &nor->mtd;
1151
1152                 mtd->priv = nor;
1153
1154                 nor->dev = dev;
1155                 spi_nor_set_flash_node(nor, np);
1156                 nor->priv = f_pdata;
1157
1158                 nor->read_reg = cqspi_read_reg;
1159                 nor->write_reg = cqspi_write_reg;
1160                 nor->read = cqspi_read;
1161                 nor->write = cqspi_write;
1162                 nor->erase = cqspi_erase;
1163                 nor->prepare = cqspi_prep;
1164                 nor->unprepare = cqspi_unprep;
1165
1166                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1167                                            dev_name(dev), cs);
1168                 if (!mtd->name) {
1169                         ret = -ENOMEM;
1170                         goto err;
1171                 }
1172
1173                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1174                 if (ret)
1175                         goto err;
1176
1177                 ret = mtd_device_register(mtd, NULL, 0);
1178                 if (ret)
1179                         goto err;
1180
1181                 f_pdata->registered = true;
1182         }
1183
1184         return 0;
1185
1186 err:
1187         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1188                 if (cqspi->f_pdata[i].registered)
1189                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1190         return ret;
1191 }
1192
1193 static int cqspi_probe(struct platform_device *pdev)
1194 {
1195         struct device_node *np = pdev->dev.of_node;
1196         struct device *dev = &pdev->dev;
1197         struct cqspi_st *cqspi;
1198         struct resource *res;
1199         struct resource *res_ahb;
1200         unsigned long data;
1201         int ret;
1202         int irq;
1203
1204         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1205         if (!cqspi)
1206                 return -ENOMEM;
1207
1208         mutex_init(&cqspi->bus_mutex);
1209         cqspi->pdev = pdev;
1210         platform_set_drvdata(pdev, cqspi);
1211
1212         /* Obtain configuration from OF. */
1213         ret = cqspi_of_get_pdata(pdev);
1214         if (ret) {
1215                 dev_err(dev, "Cannot get mandatory OF data.\n");
1216                 return -ENODEV;
1217         }
1218
1219         /* Obtain QSPI clock. */
1220         cqspi->clk = devm_clk_get(dev, NULL);
1221         if (IS_ERR(cqspi->clk)) {
1222                 dev_err(dev, "Cannot claim QSPI clock.\n");
1223                 return PTR_ERR(cqspi->clk);
1224         }
1225
1226         /* Obtain and remap controller address. */
1227         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228         cqspi->iobase = devm_ioremap_resource(dev, res);
1229         if (IS_ERR(cqspi->iobase)) {
1230                 dev_err(dev, "Cannot remap controller address.\n");
1231                 return PTR_ERR(cqspi->iobase);
1232         }
1233
1234         /* Obtain and remap AHB address. */
1235         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1236         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1237         if (IS_ERR(cqspi->ahb_base)) {
1238                 dev_err(dev, "Cannot remap AHB address.\n");
1239                 return PTR_ERR(cqspi->ahb_base);
1240         }
1241
1242         init_completion(&cqspi->transfer_complete);
1243
1244         /* Obtain IRQ line. */
1245         irq = platform_get_irq(pdev, 0);
1246         if (irq < 0) {
1247                 dev_err(dev, "Cannot obtain IRQ.\n");
1248                 return -ENXIO;
1249         }
1250
1251         ret = clk_prepare_enable(cqspi->clk);
1252         if (ret) {
1253                 dev_err(dev, "Cannot enable QSPI clock.\n");
1254                 return ret;
1255         }
1256
1257         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1258         data  = (unsigned long)of_device_get_match_data(dev);
1259         if (data & CQSPI_NEEDS_WR_DELAY)
1260                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1261                                                    cqspi->master_ref_clk_hz);
1262
1263         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1264                                pdev->name, cqspi);
1265         if (ret) {
1266                 dev_err(dev, "Cannot request IRQ.\n");
1267                 goto probe_irq_failed;
1268         }
1269
1270         cqspi_wait_idle(cqspi);
1271         cqspi_controller_init(cqspi);
1272         cqspi->current_cs = -1;
1273         cqspi->sclk = 0;
1274
1275         ret = cqspi_setup_flash(cqspi, np);
1276         if (ret) {
1277                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1278                 goto probe_setup_failed;
1279         }
1280
1281         return ret;
1282 probe_irq_failed:
1283         cqspi_controller_enable(cqspi, 0);
1284 probe_setup_failed:
1285         clk_disable_unprepare(cqspi->clk);
1286         return ret;
1287 }
1288
1289 static int cqspi_remove(struct platform_device *pdev)
1290 {
1291         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1292         int i;
1293
1294         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1295                 if (cqspi->f_pdata[i].registered)
1296                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1297
1298         cqspi_controller_enable(cqspi, 0);
1299
1300         clk_disable_unprepare(cqspi->clk);
1301
1302         return 0;
1303 }
1304
1305 #ifdef CONFIG_PM_SLEEP
1306 static int cqspi_suspend(struct device *dev)
1307 {
1308         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1309
1310         cqspi_controller_enable(cqspi, 0);
1311         return 0;
1312 }
1313
1314 static int cqspi_resume(struct device *dev)
1315 {
1316         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1317
1318         cqspi_controller_enable(cqspi, 1);
1319         return 0;
1320 }
1321
1322 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1323         .suspend = cqspi_suspend,
1324         .resume = cqspi_resume,
1325 };
1326
1327 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1328 #else
1329 #define CQSPI_DEV_PM_OPS        NULL
1330 #endif
1331
1332 static const struct of_device_id cqspi_dt_ids[] = {
1333         {
1334                 .compatible = "cdns,qspi-nor",
1335                 .data = (void *)0,
1336         },
1337         {
1338                 .compatible = "ti,k2g-qspi",
1339                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1340         },
1341         { /* end of table */ }
1342 };
1343
1344 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1345
1346 static struct platform_driver cqspi_platform_driver = {
1347         .probe = cqspi_probe,
1348         .remove = cqspi_remove,
1349         .driver = {
1350                 .name = CQSPI_NAME,
1351                 .pm = CQSPI_DEV_PM_OPS,
1352                 .of_match_table = cqspi_dt_ids,
1353         },
1354 };
1355
1356 module_platform_driver(cqspi_platform_driver);
1357
1358 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1359 MODULE_LICENSE("GPL v2");
1360 MODULE_ALIAS("platform:" CQSPI_NAME);
1361 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1362 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");