2 * Driver for Cadence QSPI Controller
4 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
25 #include <linux/jiffies.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mtd/spi-nor.h>
31 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/sched.h>
35 #include <linux/spi/spi.h>
36 #include <linux/timer.h>
38 #define CQSPI_NAME "cadence-qspi"
39 #define CQSPI_MAX_CHIPSELECT 16
42 #define CQSPI_NEEDS_WR_DELAY BIT(0)
46 struct cqspi_flash_pdata {
48 struct cqspi_st *cqspi;
63 struct platform_device *pdev;
69 void __iomem *ahb_base;
70 struct completion transfer_complete;
71 struct mutex bus_mutex;
74 int current_page_size;
75 int current_erase_size;
76 int current_addr_width;
77 unsigned long master_ref_clk_hz;
83 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
86 /* Operation timeout value */
87 #define CQSPI_TIMEOUT_MS 500
88 #define CQSPI_READ_TIMEOUT_MS 10
90 /* Instruction type */
91 #define CQSPI_INST_TYPE_SINGLE 0
92 #define CQSPI_INST_TYPE_DUAL 1
93 #define CQSPI_INST_TYPE_QUAD 2
95 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
96 #define CQSPI_DUMMY_BYTES_MAX 4
97 #define CQSPI_DUMMY_CLKS_MAX 31
99 #define CQSPI_STIG_DATA_LEN_MAX 8
102 #define CQSPI_REG_CONFIG 0x00
103 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
104 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
105 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
106 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
107 #define CQSPI_REG_CONFIG_BAUD_LSB 19
108 #define CQSPI_REG_CONFIG_IDLE_LSB 31
109 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
110 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
112 #define CQSPI_REG_RD_INSTR 0x04
113 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
114 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
115 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
116 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
117 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
118 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
119 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
120 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
121 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
122 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
124 #define CQSPI_REG_WR_INSTR 0x08
125 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
126 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
127 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
129 #define CQSPI_REG_DELAY 0x0C
130 #define CQSPI_REG_DELAY_TSLCH_LSB 0
131 #define CQSPI_REG_DELAY_TCHSH_LSB 8
132 #define CQSPI_REG_DELAY_TSD2D_LSB 16
133 #define CQSPI_REG_DELAY_TSHSL_LSB 24
134 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
135 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
136 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
137 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
139 #define CQSPI_REG_READCAPTURE 0x10
140 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
141 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
142 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
144 #define CQSPI_REG_SIZE 0x14
145 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
146 #define CQSPI_REG_SIZE_PAGE_LSB 4
147 #define CQSPI_REG_SIZE_BLOCK_LSB 16
148 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
149 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
150 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
152 #define CQSPI_REG_SRAMPARTITION 0x18
153 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
155 #define CQSPI_REG_DMA 0x20
156 #define CQSPI_REG_DMA_SINGLE_LSB 0
157 #define CQSPI_REG_DMA_BURST_LSB 8
158 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
159 #define CQSPI_REG_DMA_BURST_MASK 0xFF
161 #define CQSPI_REG_REMAP 0x24
162 #define CQSPI_REG_MODE_BIT 0x28
164 #define CQSPI_REG_SDRAMLEVEL 0x2C
165 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
166 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
167 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
168 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
170 #define CQSPI_REG_IRQSTATUS 0x40
171 #define CQSPI_REG_IRQMASK 0x44
173 #define CQSPI_REG_INDIRECTRD 0x60
174 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
175 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
176 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
178 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
179 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
180 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
182 #define CQSPI_REG_CMDCTRL 0x90
183 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
184 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
185 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
186 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
187 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
188 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
189 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
190 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
191 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
192 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
193 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
194 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
196 #define CQSPI_REG_INDIRECTWR 0x70
197 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
198 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
199 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
201 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
202 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
203 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
205 #define CQSPI_REG_CMDADDRESS 0x94
206 #define CQSPI_REG_CMDREADDATALOWER 0xA0
207 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
208 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
209 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
211 /* Interrupt status bits */
212 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
213 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
214 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
215 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
216 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
217 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
218 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
219 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
221 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
222 CQSPI_REG_IRQ_IND_SRAM_FULL | \
223 CQSPI_REG_IRQ_IND_COMP)
225 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
226 CQSPI_REG_IRQ_WATERMARK | \
227 CQSPI_REG_IRQ_UNDERFLOW)
229 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
231 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
233 unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
245 if (time_after(jiffies, end))
250 static bool cqspi_is_idle(struct cqspi_st *cqspi)
252 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
254 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
257 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
259 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
261 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
262 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
265 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
267 struct cqspi_st *cqspi = dev;
268 unsigned int irq_status;
270 /* Read interrupt status */
271 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
273 /* Clear interrupt */
274 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
276 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
279 complete(&cqspi->transfer_complete);
284 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
286 struct cqspi_flash_pdata *f_pdata = nor->priv;
289 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
290 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
291 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
296 static int cqspi_wait_idle(struct cqspi_st *cqspi)
298 const unsigned int poll_idle_retry = 3;
299 unsigned int count = 0;
300 unsigned long timeout;
302 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
305 * Read few times in succession to ensure the controller
306 * is indeed idle, that is, the bit does not transition
309 if (cqspi_is_idle(cqspi))
314 if (count >= poll_idle_retry)
317 if (time_after(jiffies, timeout)) {
318 /* Timeout, in busy mode. */
319 dev_err(&cqspi->pdev->dev,
320 "QSPI is still busy after %dms timeout.\n",
329 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
331 void __iomem *reg_base = cqspi->iobase;
334 /* Write the CMDCTRL without start execution. */
335 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
337 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
338 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
340 /* Polling for completion. */
341 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
342 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
344 dev_err(&cqspi->pdev->dev,
345 "Flash command execution timed out.\n");
349 /* Polling QSPI idle status. */
350 return cqspi_wait_idle(cqspi);
353 static int cqspi_command_read(struct spi_nor *nor,
354 const u8 *txbuf, const unsigned n_tx,
355 u8 *rxbuf, const unsigned n_rx)
357 struct cqspi_flash_pdata *f_pdata = nor->priv;
358 struct cqspi_st *cqspi = f_pdata->cqspi;
359 void __iomem *reg_base = cqspi->iobase;
362 unsigned int read_len;
365 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
366 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
371 reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
373 rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
374 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
376 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
378 /* 0 means 1 byte. */
379 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
380 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
381 status = cqspi_exec_flash_cmd(cqspi, reg);
385 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
387 /* Put the read value into rx_buf */
388 read_len = (n_rx > 4) ? 4 : n_rx;
389 memcpy(rxbuf, ®, read_len);
393 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
395 read_len = n_rx - read_len;
396 memcpy(rxbuf, ®, read_len);
402 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
403 const u8 *txbuf, const unsigned n_tx)
405 struct cqspi_flash_pdata *f_pdata = nor->priv;
406 struct cqspi_st *cqspi = f_pdata->cqspi;
407 void __iomem *reg_base = cqspi->iobase;
412 if (n_tx > 4 || (n_tx && !txbuf)) {
414 "Invalid input argument, cmdlen %d txbuf 0x%p\n",
419 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
421 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
422 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
423 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
425 memcpy(&data, txbuf, n_tx);
426 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
429 ret = cqspi_exec_flash_cmd(cqspi, reg);
433 static int cqspi_command_write_addr(struct spi_nor *nor,
434 const u8 opcode, const unsigned int addr)
436 struct cqspi_flash_pdata *f_pdata = nor->priv;
437 struct cqspi_st *cqspi = f_pdata->cqspi;
438 void __iomem *reg_base = cqspi->iobase;
441 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
442 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
443 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
444 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
446 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
448 return cqspi_exec_flash_cmd(cqspi, reg);
451 static int cqspi_indirect_read_setup(struct spi_nor *nor,
452 const unsigned int from_addr)
454 struct cqspi_flash_pdata *f_pdata = nor->priv;
455 struct cqspi_st *cqspi = f_pdata->cqspi;
456 void __iomem *reg_base = cqspi->iobase;
457 unsigned int dummy_clk = 0;
460 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
462 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
463 reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
465 /* Setup dummy clock cycles */
466 dummy_clk = nor->read_dummy;
467 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
471 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
472 /* Set mode bits high to ensure chip doesn't enter XIP */
473 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
475 /* Need to subtract the mode byte (8 clocks). */
476 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
480 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
481 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
484 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
486 /* Set address width */
487 reg = readl(reg_base + CQSPI_REG_SIZE);
488 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
489 reg |= (nor->addr_width - 1);
490 writel(reg, reg_base + CQSPI_REG_SIZE);
494 static int cqspi_indirect_read_execute(struct spi_nor *nor,
495 u8 *rxbuf, const unsigned n_rx)
497 struct cqspi_flash_pdata *f_pdata = nor->priv;
498 struct cqspi_st *cqspi = f_pdata->cqspi;
499 void __iomem *reg_base = cqspi->iobase;
500 void __iomem *ahb_base = cqspi->ahb_base;
501 unsigned int remaining = n_rx;
502 unsigned int mod_bytes = n_rx % 4;
503 unsigned int bytes_to_read = 0;
504 u8 *rxbuf_end = rxbuf + n_rx;
507 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
509 /* Clear all interrupts. */
510 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
512 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
514 reinit_completion(&cqspi->transfer_complete);
515 writel(CQSPI_REG_INDIRECTRD_START_MASK,
516 reg_base + CQSPI_REG_INDIRECTRD);
518 while (remaining > 0) {
519 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
521 (CQSPI_READ_TIMEOUT_MS));
523 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
525 if (!ret && bytes_to_read == 0) {
526 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
531 while (bytes_to_read != 0) {
532 unsigned int word_remain = round_down(remaining, 4);
534 bytes_to_read *= cqspi->fifo_width;
535 bytes_to_read = bytes_to_read > remaining ?
536 remaining : bytes_to_read;
537 bytes_to_read = round_down(bytes_to_read, 4);
538 /* Read 4 byte word chunks then single bytes */
540 ioread32_rep(ahb_base, rxbuf,
541 (bytes_to_read / 4));
542 } else if (!word_remain && mod_bytes) {
543 unsigned int temp = ioread32(ahb_base);
545 bytes_to_read = mod_bytes;
546 memcpy(rxbuf, &temp, min((unsigned int)
550 rxbuf += bytes_to_read;
551 remaining -= bytes_to_read;
552 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
556 reinit_completion(&cqspi->transfer_complete);
559 /* Check indirect done status */
560 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
561 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
564 "Indirect read completion error (%i)\n", ret);
568 /* Disable interrupt */
569 writel(0, reg_base + CQSPI_REG_IRQMASK);
571 /* Clear indirect completion status */
572 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
577 /* Disable interrupt */
578 writel(0, reg_base + CQSPI_REG_IRQMASK);
580 /* Cancel the indirect read */
581 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
582 reg_base + CQSPI_REG_INDIRECTRD);
586 static int cqspi_indirect_write_setup(struct spi_nor *nor,
587 const unsigned int to_addr)
590 struct cqspi_flash_pdata *f_pdata = nor->priv;
591 struct cqspi_st *cqspi = f_pdata->cqspi;
592 void __iomem *reg_base = cqspi->iobase;
595 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
596 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
597 reg = cqspi_calc_rdreg(nor, nor->program_opcode);
598 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
600 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
602 reg = readl(reg_base + CQSPI_REG_SIZE);
603 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
604 reg |= (nor->addr_width - 1);
605 writel(reg, reg_base + CQSPI_REG_SIZE);
609 static int cqspi_indirect_write_execute(struct spi_nor *nor,
610 const u8 *txbuf, const unsigned n_tx)
612 const unsigned int page_size = nor->page_size;
613 struct cqspi_flash_pdata *f_pdata = nor->priv;
614 struct cqspi_st *cqspi = f_pdata->cqspi;
615 void __iomem *reg_base = cqspi->iobase;
616 unsigned int remaining = n_tx;
617 unsigned int write_bytes;
620 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
622 /* Clear all interrupts. */
623 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
625 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
627 reinit_completion(&cqspi->transfer_complete);
628 writel(CQSPI_REG_INDIRECTWR_START_MASK,
629 reg_base + CQSPI_REG_INDIRECTWR);
631 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
632 * Controller programming sequence, couple of cycles of
633 * QSPI_REF_CLK delay is required for the above bit to
634 * be internally synchronized by the QSPI module. Provide 5
638 ndelay(cqspi->wr_delay);
640 while (remaining > 0) {
641 size_t write_words, mod_bytes;
643 write_bytes = remaining > page_size ? page_size : remaining;
644 write_words = write_bytes / 4;
645 mod_bytes = write_bytes % 4;
646 /* Write 4 bytes at a time then single bytes. */
648 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
649 txbuf += (write_words * 4);
652 unsigned int temp = 0xFFFFFFFF;
654 memcpy(&temp, txbuf, mod_bytes);
655 iowrite32(temp, cqspi->ahb_base);
659 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
663 dev_err(nor->dev, "Indirect write timeout\n");
668 remaining -= write_bytes;
671 reinit_completion(&cqspi->transfer_complete);
674 /* Check indirect done status */
675 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
676 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
679 "Indirect write completion error (%i)\n", ret);
683 /* Disable interrupt. */
684 writel(0, reg_base + CQSPI_REG_IRQMASK);
686 /* Clear indirect completion status */
687 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
689 cqspi_wait_idle(cqspi);
694 /* Disable interrupt. */
695 writel(0, reg_base + CQSPI_REG_IRQMASK);
697 /* Cancel the indirect write */
698 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
699 reg_base + CQSPI_REG_INDIRECTWR);
703 static void cqspi_chipselect(struct spi_nor *nor)
705 struct cqspi_flash_pdata *f_pdata = nor->priv;
706 struct cqspi_st *cqspi = f_pdata->cqspi;
707 void __iomem *reg_base = cqspi->iobase;
708 unsigned int chip_select = f_pdata->cs;
711 reg = readl(reg_base + CQSPI_REG_CONFIG);
712 if (cqspi->is_decoded_cs) {
713 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
715 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
717 /* Convert CS if without decoder.
723 chip_select = 0xF & ~(1 << chip_select);
726 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
727 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
728 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
729 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
730 writel(reg, reg_base + CQSPI_REG_CONFIG);
733 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
735 struct cqspi_flash_pdata *f_pdata = nor->priv;
736 struct cqspi_st *cqspi = f_pdata->cqspi;
737 void __iomem *iobase = cqspi->iobase;
740 /* configure page size and block size. */
741 reg = readl(iobase + CQSPI_REG_SIZE);
742 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
743 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
744 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
745 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
746 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
747 reg |= (nor->addr_width - 1);
748 writel(reg, iobase + CQSPI_REG_SIZE);
750 /* configure the chip select */
751 cqspi_chipselect(nor);
753 /* Store the new configuration of the controller */
754 cqspi->current_page_size = nor->page_size;
755 cqspi->current_erase_size = nor->mtd.erasesize;
756 cqspi->current_addr_width = nor->addr_width;
759 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
760 const unsigned int ns_val)
764 ticks = ref_clk_hz / 1000; /* kHz */
765 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
770 static void cqspi_delay(struct spi_nor *nor)
772 struct cqspi_flash_pdata *f_pdata = nor->priv;
773 struct cqspi_st *cqspi = f_pdata->cqspi;
774 void __iomem *iobase = cqspi->iobase;
775 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
776 unsigned int tshsl, tchsh, tslch, tsd2d;
780 /* calculate the number of ref ticks for one sclk tick */
781 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
783 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
784 /* this particular value must be at least one sclk */
788 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
789 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
790 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
792 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
793 << CQSPI_REG_DELAY_TSHSL_LSB;
794 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
795 << CQSPI_REG_DELAY_TCHSH_LSB;
796 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
797 << CQSPI_REG_DELAY_TSLCH_LSB;
798 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
799 << CQSPI_REG_DELAY_TSD2D_LSB;
800 writel(reg, iobase + CQSPI_REG_DELAY);
803 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
805 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
806 void __iomem *reg_base = cqspi->iobase;
809 /* Recalculate the baudrate divisor based on QSPI specification. */
810 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
812 reg = readl(reg_base + CQSPI_REG_CONFIG);
813 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
814 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
815 writel(reg, reg_base + CQSPI_REG_CONFIG);
818 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
819 const unsigned int bypass,
820 const unsigned int delay)
822 void __iomem *reg_base = cqspi->iobase;
825 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
828 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
830 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
832 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
833 << CQSPI_REG_READCAPTURE_DELAY_LSB);
835 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
836 << CQSPI_REG_READCAPTURE_DELAY_LSB;
838 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
841 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
843 void __iomem *reg_base = cqspi->iobase;
846 reg = readl(reg_base + CQSPI_REG_CONFIG);
849 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
851 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
853 writel(reg, reg_base + CQSPI_REG_CONFIG);
856 static void cqspi_configure(struct spi_nor *nor)
858 struct cqspi_flash_pdata *f_pdata = nor->priv;
859 struct cqspi_st *cqspi = f_pdata->cqspi;
860 const unsigned int sclk = f_pdata->clk_rate;
861 int switch_cs = (cqspi->current_cs != f_pdata->cs);
862 int switch_ck = (cqspi->sclk != sclk);
864 if ((cqspi->current_page_size != nor->page_size) ||
865 (cqspi->current_erase_size != nor->mtd.erasesize) ||
866 (cqspi->current_addr_width != nor->addr_width))
869 if (switch_cs || switch_ck)
870 cqspi_controller_enable(cqspi, 0);
872 /* Switch chip select. */
874 cqspi->current_cs = f_pdata->cs;
875 cqspi_configure_cs_and_sizes(nor);
878 /* Setup baudrate divisor and delays */
881 cqspi_config_baudrate_div(cqspi);
883 cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
886 if (switch_cs || switch_ck)
887 cqspi_controller_enable(cqspi, 1);
890 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
892 struct cqspi_flash_pdata *f_pdata = nor->priv;
894 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
895 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
896 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
899 switch (nor->read_proto) {
900 case SNOR_PROTO_1_1_1:
901 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
903 case SNOR_PROTO_1_1_2:
904 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
906 case SNOR_PROTO_1_1_4:
907 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
914 cqspi_configure(nor);
919 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
920 size_t len, const u_char *buf)
924 ret = cqspi_set_protocol(nor, 0);
928 ret = cqspi_indirect_write_setup(nor, to);
932 ret = cqspi_indirect_write_execute(nor, buf, len);
939 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
940 size_t len, u_char *buf)
944 ret = cqspi_set_protocol(nor, 1);
948 ret = cqspi_indirect_read_setup(nor, from);
952 ret = cqspi_indirect_read_execute(nor, buf, len);
959 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
963 ret = cqspi_set_protocol(nor, 0);
967 /* Send write enable, then erase commands. */
968 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
972 /* Set up command buffer. */
973 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
980 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
982 struct cqspi_flash_pdata *f_pdata = nor->priv;
983 struct cqspi_st *cqspi = f_pdata->cqspi;
985 mutex_lock(&cqspi->bus_mutex);
990 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
992 struct cqspi_flash_pdata *f_pdata = nor->priv;
993 struct cqspi_st *cqspi = f_pdata->cqspi;
995 mutex_unlock(&cqspi->bus_mutex);
998 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1002 ret = cqspi_set_protocol(nor, 0);
1004 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1009 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1013 ret = cqspi_set_protocol(nor, 0);
1015 ret = cqspi_command_write(nor, opcode, buf, len);
1020 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1021 struct cqspi_flash_pdata *f_pdata,
1022 struct device_node *np)
1024 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1025 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1029 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1030 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1034 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1035 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1039 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1040 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1044 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1045 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1049 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1050 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1057 static int cqspi_of_get_pdata(struct platform_device *pdev)
1059 struct device_node *np = pdev->dev.of_node;
1060 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1062 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1064 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1065 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1069 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1070 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1074 if (of_property_read_u32(np, "cdns,trigger-address",
1075 &cqspi->trigger_address)) {
1076 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1083 static void cqspi_controller_init(struct cqspi_st *cqspi)
1085 cqspi_controller_enable(cqspi, 0);
1087 /* Configure the remap address register, no remap */
1088 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1090 /* Disable all interrupts. */
1091 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1093 /* Configure the SRAM split to 1:1 . */
1094 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1096 /* Load indirect trigger address. */
1097 writel(cqspi->trigger_address,
1098 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1100 /* Program read watermark -- 1/2 of the FIFO. */
1101 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1102 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1103 /* Program write watermark -- 1/8 of the FIFO. */
1104 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1105 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1107 cqspi_controller_enable(cqspi, 1);
1110 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1112 const struct spi_nor_hwcaps hwcaps = {
1113 .mask = SNOR_HWCAPS_READ |
1114 SNOR_HWCAPS_READ_FAST |
1115 SNOR_HWCAPS_READ_1_1_2 |
1116 SNOR_HWCAPS_READ_1_1_4 |
1119 struct platform_device *pdev = cqspi->pdev;
1120 struct device *dev = &pdev->dev;
1121 struct cqspi_flash_pdata *f_pdata;
1122 struct spi_nor *nor;
1123 struct mtd_info *mtd;
1127 /* Get flash device data */
1128 for_each_available_child_of_node(dev->of_node, np) {
1129 ret = of_property_read_u32(np, "reg", &cs);
1131 dev_err(dev, "Couldn't determine chip select.\n");
1135 if (cs >= CQSPI_MAX_CHIPSELECT) {
1137 dev_err(dev, "Chip select %d out of range.\n", cs);
1141 f_pdata = &cqspi->f_pdata[cs];
1142 f_pdata->cqspi = cqspi;
1145 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1149 nor = &f_pdata->nor;
1155 spi_nor_set_flash_node(nor, np);
1156 nor->priv = f_pdata;
1158 nor->read_reg = cqspi_read_reg;
1159 nor->write_reg = cqspi_write_reg;
1160 nor->read = cqspi_read;
1161 nor->write = cqspi_write;
1162 nor->erase = cqspi_erase;
1163 nor->prepare = cqspi_prep;
1164 nor->unprepare = cqspi_unprep;
1166 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1173 ret = spi_nor_scan(nor, NULL, &hwcaps);
1177 ret = mtd_device_register(mtd, NULL, 0);
1181 f_pdata->registered = true;
1187 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1188 if (cqspi->f_pdata[i].registered)
1189 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1193 static int cqspi_probe(struct platform_device *pdev)
1195 struct device_node *np = pdev->dev.of_node;
1196 struct device *dev = &pdev->dev;
1197 struct cqspi_st *cqspi;
1198 struct resource *res;
1199 struct resource *res_ahb;
1204 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1208 mutex_init(&cqspi->bus_mutex);
1210 platform_set_drvdata(pdev, cqspi);
1212 /* Obtain configuration from OF. */
1213 ret = cqspi_of_get_pdata(pdev);
1215 dev_err(dev, "Cannot get mandatory OF data.\n");
1219 /* Obtain QSPI clock. */
1220 cqspi->clk = devm_clk_get(dev, NULL);
1221 if (IS_ERR(cqspi->clk)) {
1222 dev_err(dev, "Cannot claim QSPI clock.\n");
1223 return PTR_ERR(cqspi->clk);
1226 /* Obtain and remap controller address. */
1227 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228 cqspi->iobase = devm_ioremap_resource(dev, res);
1229 if (IS_ERR(cqspi->iobase)) {
1230 dev_err(dev, "Cannot remap controller address.\n");
1231 return PTR_ERR(cqspi->iobase);
1234 /* Obtain and remap AHB address. */
1235 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1236 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1237 if (IS_ERR(cqspi->ahb_base)) {
1238 dev_err(dev, "Cannot remap AHB address.\n");
1239 return PTR_ERR(cqspi->ahb_base);
1242 init_completion(&cqspi->transfer_complete);
1244 /* Obtain IRQ line. */
1245 irq = platform_get_irq(pdev, 0);
1247 dev_err(dev, "Cannot obtain IRQ.\n");
1251 ret = clk_prepare_enable(cqspi->clk);
1253 dev_err(dev, "Cannot enable QSPI clock.\n");
1257 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1258 data = (unsigned long)of_device_get_match_data(dev);
1259 if (data & CQSPI_NEEDS_WR_DELAY)
1260 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1261 cqspi->master_ref_clk_hz);
1263 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1266 dev_err(dev, "Cannot request IRQ.\n");
1267 goto probe_irq_failed;
1270 cqspi_wait_idle(cqspi);
1271 cqspi_controller_init(cqspi);
1272 cqspi->current_cs = -1;
1275 ret = cqspi_setup_flash(cqspi, np);
1277 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1278 goto probe_setup_failed;
1283 cqspi_controller_enable(cqspi, 0);
1285 clk_disable_unprepare(cqspi->clk);
1289 static int cqspi_remove(struct platform_device *pdev)
1291 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1294 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1295 if (cqspi->f_pdata[i].registered)
1296 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1298 cqspi_controller_enable(cqspi, 0);
1300 clk_disable_unprepare(cqspi->clk);
1305 #ifdef CONFIG_PM_SLEEP
1306 static int cqspi_suspend(struct device *dev)
1308 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1310 cqspi_controller_enable(cqspi, 0);
1314 static int cqspi_resume(struct device *dev)
1316 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1318 cqspi_controller_enable(cqspi, 1);
1322 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1323 .suspend = cqspi_suspend,
1324 .resume = cqspi_resume,
1327 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1329 #define CQSPI_DEV_PM_OPS NULL
1332 static const struct of_device_id cqspi_dt_ids[] = {
1334 .compatible = "cdns,qspi-nor",
1338 .compatible = "ti,k2g-qspi",
1339 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1341 { /* end of table */ }
1344 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1346 static struct platform_driver cqspi_platform_driver = {
1347 .probe = cqspi_probe,
1348 .remove = cqspi_remove,
1351 .pm = CQSPI_DEV_PM_OPS,
1352 .of_match_table = cqspi_dt_ids,
1356 module_platform_driver(cqspi_platform_driver);
1358 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1359 MODULE_LICENSE("GPL v2");
1360 MODULE_ALIAS("platform:" CQSPI_NAME);
1361 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1362 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");